93 lines
1.6 KiB
Systemverilog
93 lines
1.6 KiB
Systemverilog
//`timescale 1ns / 1ns
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module tb();
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bit clk;
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bit clk_enable;
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bit reset;
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real data[8];
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real i_data[8];
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real q_data[8];
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, tb);
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end
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initial begin
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#0;
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reset = 1'b1;
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#100;
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reset = 1'b0;
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end
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//clk
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initial begin
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#0;
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clk = 1'b1;
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end
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always #5 clk = ~clk;
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logic [21:0] cnt;
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always@(posedge clk or negedge reset)begin
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if(reset)
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cnt <= 22'd0;
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else
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cnt <= cnt + 22'd1;
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end
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initial begin
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wait(cnt[14]==1'b1)
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$finish(0);
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end
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logic [10:0] i=0;
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always@(posedge clk or negedge reset)begin
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if(reset&(i==11'd8))begin
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i <= 11'b0;
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end else begin
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i <= i+1'b1;
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end
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end
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real data_reg[0:7];
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always@(posedge clk or negedge reset)begin
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data_reg[i] <= 64'b0+i+3;
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end
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hilbert_fir_dpi inst_hilbert_fir_dpi(
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.clk(clk),
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.clk_enable(1'b1),
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.reset(reset),
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.data(data_reg),
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.i_data(i_data),
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.q_data(q_data)
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);
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initial begin
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#160000
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$display("data_reg is:%d%d%d%d%d%d%d%d",data_reg[0],data_reg[1],data_reg[2],data_reg[3],data_reg[4],data_reg[5],data_reg[6],data_reg[7]);
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$display("i_data0 is :",i_data[0]);
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$display("i_data1 is :",i_data[1]);
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$display("i_data2 is :",i_data[2]);
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$display("i_data3 is :",i_data[3]);
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$display("i_data4 is :",i_data[4]);
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$display("i_data5 is :",i_data[5]);
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$display("i_data6 is :",i_data[6]);
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$display("i_data7 is :",i_data[7]);
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$display("q_data0 is :",q_data[0]);
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$display("q_data1 is :",q_data[1]);
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$display("q_data2 is :",q_data[2]);
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$display("q_data3 is :",q_data[3]);
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$display("q_data4 is :",q_data[4]);
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$display("q_data5 is :",q_data[5]);
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$display("q_data6 is :",q_data[6]);
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$display("q_data7 is :",q_data[7]);
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end
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endmodule
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