77 lines
1.1 KiB
Systemverilog
77 lines
1.1 KiB
Systemverilog
//`timescale 1ns / 1ns
|
|
module tb();
|
|
logic clk;
|
|
logic clk_enable;
|
|
logic reset;
|
|
logic [63:0] fcw;
|
|
logic [63:0] ptw;
|
|
logic clr;
|
|
logic [63:0] acc;
|
|
logic [63:0] result_cos;
|
|
logic [63:0] result_sin;
|
|
logic [63:0] result_acc;
|
|
|
|
initial
|
|
begin
|
|
$fsdbDumpfile("TB.fsdb");
|
|
$fsdbDumpvars(0, tb);
|
|
end
|
|
|
|
logic [21:0] cnt;
|
|
always@(posedge clk or negedge reset)begin
|
|
if(reset)
|
|
cnt <= 22'd0;
|
|
else
|
|
cnt <= cnt + 22'd1;
|
|
end
|
|
initial begin
|
|
wait(cnt[14]==1'b1)
|
|
$finish(0);
|
|
end
|
|
|
|
initial begin
|
|
#0;
|
|
reset = 1'b1;
|
|
#100;
|
|
reset = 1'b0;
|
|
end
|
|
//clk
|
|
initial begin
|
|
#0;
|
|
clk = 1'b1;
|
|
end
|
|
always #5 clk = ~clk;
|
|
|
|
initial begin
|
|
#0;
|
|
clk_enable = 1'b1;
|
|
clr = 1'b0;
|
|
fcw = 48'h0010_0000_0000;
|
|
ptw = 16'h0;
|
|
acc = 16'h0;
|
|
end
|
|
logic [63:0] acc_reg;
|
|
always@(posedge clk or negedge reset)begin
|
|
if(reset)
|
|
acc_reg <= 63'd0;
|
|
else
|
|
acc_reg <= result_acc + fcw;
|
|
end
|
|
|
|
nco_dpi inst_nco_dpi(
|
|
.clk(clk),
|
|
.clk_enable(clk_enable),
|
|
.reset(reset),
|
|
.fcw(fcw),
|
|
.ptw(ptw),
|
|
.clr(clr),
|
|
.acc(acc_reg),
|
|
.result_cos(result_cos),
|
|
.result_sin(result_sin),
|
|
.result_acc(result_acc)
|
|
);
|
|
|
|
|
|
endmodule
|
|
|