65 lines
1.5 KiB
Systemverilog
65 lines
1.5 KiB
Systemverilog
// ======================================== //
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// CopyRight(C) 2024 HFNL-CMOS
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// ALL RIGHTS RESERVED.
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// FileName : mcu_cw_item.sv
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// Author : WuJin
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// Email : wujin@hfnl.cn
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// Created : 2024-12-30
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// History : v1.0
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// ======================================= //
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`ifndef _MCU_ITEM_
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`define _MCU_ITEM_
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class mcu_cw_item extends uvm_sequence_item;
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rand bit [63:0] clock_cycle;
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rand bit [31:0] cw_data;
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rand bit wr_ram;
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rand bit [31:0] wr_ram_addr;
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rand bit [31:0] wr_ram_data;
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rand bit [3:0] wr_ram_mask;
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rand bit wr_reg;
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rand bit [4:0] wr_reg_addr;
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rand bit [31:0] wr_reg_data;
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function new(string name = "");
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super.new(name);
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endfunction : new
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function void post_randomize();
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//ToDo
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endfunction : post_randomize
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`uvm_object_utils_begin(mcu_cw_item)
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`uvm_field_int(clock_cycle,UVM_ALL_ON)
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`uvm_field_int(cw_data,UVM_ALL_ON)
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`uvm_field_int(wr_ram,UVM_ALL_ON)
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`uvm_field_int(wr_ram_addr,UVM_ALL_ON)
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`uvm_field_int(wr_ram_data,UVM_ALL_ON)
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`uvm_field_int(wr_ram_mask,UVM_ALL_ON)
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`uvm_field_int(wr_reg,UVM_ALL_ON)
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`uvm_field_int(wr_reg_addr,UVM_ALL_ON)
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`uvm_field_int(wr_reg_data,UVM_ALL_ON)
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`uvm_object_utils_end
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function void do_pack(uvm_packer packer);
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super.do_pack(packer);
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endfunction : do_pack
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//do_unpack
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function void do_unpack(uvm_packer packer);
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super.do_unpack(packer);
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endfunction : do_unpack
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endclass
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`endif
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