//FILE_HEADER------------------------------------------------------- //FILE_NAME : readout_daq_rm.sv //DEPARTEMENT : QuantumCTek-ASIC //AUTHOR : Yunzhuo Zhang //TIME : 2025.3.10 //******************************************************************* //DESCRIPTION : daq reference model define //******************************************************************* //END_HEADER********************************************************* `ifndef READOUT_DAQ_RM `define READOUT_DAQ_RM `include "../testbench/refm/mcu_cw_item.sv" //`include "../testbench/refm/reg_rfm.sv" class readout_daq_rm extends uvm_component; `uvm_component_utils(readout_daq_rm); virtual rm_if rm_if; //sync uvm_blocking_get_port #(EZQ_readout_adc_item) adc_get_port; //get adc wave uvm_blocking_get_port #(mcu_cw_item) mcu_get_port; //get cw_data uvm_analysis_port #(spi_item) spi_rm2scb_port; //send iq_sum, iq_state to scb // parameter NUM_QUBIT = 1; // parameter NUM_WAY = 1; bit [31:0] ram_data[bit[31:0]]; bit [31:0] wr_data; bit [31:0] wr_addr; bit [63:0] clock_cycle ; bit [31:0] cw_data ; bit cw_valid ; bit [63:0] adc_wave[$]; bit [31:0] delay_cycle; bit [31:0] all_queue[$]; bit [31:0] cw_data_cur; bit [31:0] clock_cycle_cur; bit cw_valid_cur; bit [63:0] adc_wave_cur[$]; bit [31:0] delay_cycle_cur; bit [31:0] time_interval; bit flag; mcu_cw_item cw_queue[$]; bit [63:0] adc_data_queue[$]; bit [31:0] mcu_timer; bit [31:0] mcu_counter; bit [31:0] loc_state; bit [31:0] glb_state; bit [31:0] feed_data; bit [31:0] send_data; bit [31:0] sram_count; bit [31:0] push_count; bit [31:0] command; bit [31:0] func_ctrl; bit [31:0] sample_depth; bit [31:0] int_threshold; bit [31:0] qubit_state; bit [31:0] read_req_ctrl; bit [31:0] demod_width [15:0]; bit [31:0] demod_freq [15:0]; bit [31:0] count_state_0 [15:0]; bit [31:0] count_state_1 [15:0]; bit [31:0] count_state_2 [15:0]; bit [31:0] count_state_3 [15:0]; bit [31:0] i_sum [15:0]; bit [31:0] q_sum [15:0]; bit [31:0] para_ab0 [15:0]; bit [31:0] para_ab1 [15:0]; bit [31:0] para_ab2 [15:0]; bit [31:0] para_c0 [15:0]; bit [31:0] para_c1 [15:0]; bit [31:0] para_c2 [15:0]; extern function new(string name,uvm_component parent); extern function void build_phase(uvm_phase phase); extern virtual task run_phase(uvm_phase phase); extern task get_mcu_cw_item(); extern task get_adc_item(); extern task get_spi_item(); extern task get_config_data(); extern task send_spi_item(); extern task daq_exe( ref bit [31:0] mcu_timer, ref bit [31:0] mcu_counter, ref bit [31:0] loc_state, ref bit [31:0] glb_state, ref bit [31:0] feed_data, ref bit [31:0] sram_count, ref bit [31:0] push_count, ref bit [31:0] qubit_state, ref bit [31:0] i_sum [15:0], ref bit [31:0] q_sum [15:0], ref bit [31:0] count_state_0 [15:0], ref bit [31:0] count_state_1 [15:0], ref bit [31:0] count_state_2 [15:0], ref bit [31:0] count_state_3 [15:0] ); extern task daq_block( input bit [15:0] i, input bit demod_valid, input bit [31:0]demod_freq , input bit [31:0]demod_width , input bit [31:0]para_ab0 , input bit [31:0]para_ab1 , input bit [31:0]para_ab2 , input bit [31:0]para_c0 , input bit [31:0]para_c1 , input bit [31:0]para_c2 , ref bit [1 :0]state_data , ref bit [31:0]i_sum , ref bit [31:0]q_sum , ref bit [31:0]count_state_0 , ref bit [31:0]count_state_1 , ref bit [31:0]count_state_2 , ref bit [31:0]count_state_3 ); extern task dds( input bit unsigned[9 :0] address, output bit signed[7 :0] dds_cos, output bit signed[7 :0] dds_sin ); endclass function readout_daq_rm::new(string name,uvm_component parent); super.new(name,parent); endfunction : new function void readout_daq_rm::build_phase(uvm_phase phase); super.build_phase(phase); if(!uvm_config_db#(virtual rm_if)::get(this,"","rm_if",rm_if)) `uvm_fatal("CFGERR",{"virtual interface must be set for: ",get_full_name(),".vif"}); //create port mcu_get_port = new("mcu_get_port",this); adc_get_port = new("adc_get_port",this); spi_rm2scb_port = new("spi_rm2scb_port",this); endfunction //task get_adc_item task readout_daq_rm::get_adc_item(); EZQ_readout_adc_item EZQ_readout_adc_item; forever begin adc_get_port.get(EZQ_readout_adc_item); adc_wave = EZQ_readout_adc_item.adc_wave; `uvm_info(get_type_name(),$sformatf("get_adc_data = %0p",adc_wave),UVM_LOW) for(int i = 0; i < adc_wave.size(); i++)begin adc_data_queue.push_back(adc_wave[i]); end `uvm_info(get_type_name(),$sformatf("adc_data_queue.size = %0h",adc_data_queue.size()),UVM_LOW) end endtask //task get_mcu_cw_item task readout_daq_rm::get_mcu_cw_item(); mcu_cw_item mcu_cw_item; forever begin mcu_get_port.get(mcu_cw_item); clock_cycle = mcu_cw_item.clock_cycle; cw_data = mcu_cw_item.cw_data; cw_valid = mcu_cw_item.cw_valid; `uvm_info(get_type_name(),$sformatf("mcu_cw_data = %0h,mcu_cw_valid = %0h,mcu_cycle = %0h",mcu_cw_item.cw_data,mcu_cw_item.cw_valid,mcu_cw_item.clock_cycle),UVM_LOW) if(cw_valid)begin cw_queue.push_back(mcu_cw_item); `uvm_info(get_type_name(),$sformatf("cw_queue_size = %0h",cw_queue.size()),UVM_LOW) end end endtask //task get_spi_item task readout_daq_rm::get_spi_item(); forever begin @(wr_addr or wr_data); `uvm_info(get_type_name(),$sformatf("wr_data=%0h, wr_addr=%h",wr_data,wr_addr),UVM_LOW) ram_data[wr_addr] = wr_data; end endtask //task send_spi_item task readout_daq_rm::send_spi_item(); spi_item spi_item; bit [31:0]spi_item_addr=32'h600000; wait(int_threshold!=0) `uvm_info(get_type_name(),$sformatf("int_threshold = %0h",int_threshold),UVM_LOW) forever begin if(all_queue.size()> int_threshold)begin spi_item = new(); spi_item.cmd = 1 ; spi_item.addr = spi_item_addr ; spi_item.cfgid = 5'd0 ; for (int i = 0; i < int_threshold; i++) begin spi_item.data.push_back(all_queue[i]); end spi_rm2scb_port.write(spi_item); `uvm_info(get_type_name(),"daq_rm send spi_item",UVM_LOW) spi_item.print(); `uvm_info(get_type_name(),$sformatf("int_threshold = %0h",int_threshold),UVM_LOW) `uvm_info(get_type_name(),$sformatf("send_spi_item = %0p",spi_item.data),UVM_LOW) `uvm_info(get_type_name(),$sformatf("spi_item_size = %0p",spi_item.data.size()),UVM_LOW) all_queue = all_queue[int_threshold:$]; spi_item_addr = spi_item_addr + 25'h4 * int_threshold ; end @(posedge `CLK); end endtask task readout_daq_rm::run_phase(uvm_phase phase);//main task fork get_mcu_cw_item(); get_adc_item(); get_spi_item(); get_config_data(); daq_exe( mcu_timer, mcu_counter, loc_state, glb_state, feed_data, sram_count, push_count, qubit_state, i_sum , q_sum , count_state_0 , count_state_1 , count_state_2 , count_state_3 ); send_spi_item(); join endtask task readout_daq_rm::daq_exe( ref bit [31:0] mcu_timer, ref bit [31:0] mcu_counter, ref bit [31:0] loc_state, ref bit [31:0] glb_state, ref bit [31:0] feed_data, ref bit [31:0] sram_count, ref bit [31:0] push_count, ref bit [31:0] qubit_state, ref bit [31:0] i_sum [15:0], ref bit [31:0] q_sum [15:0], ref bit [31:0] count_state_0 [15:0], ref bit [31:0] count_state_1 [15:0], ref bit [31:0] count_state_2 [15:0], ref bit [31:0] count_state_3 [15:0] ); //DAQ signal bit [15:0] iq_save_en; bit [15:0] state_save_en; bit [15:0] count_save_en; bit [1 :0] state_data[15:0]; bit [15:0] demod_valid; bit [15:0] i; //wait sync signal `uvm_info(get_type_name(),"daq wait sync_in",UVM_LOW) wait (`SYNC_IN); `uvm_info(get_type_name(),"daq sync_in come",UVM_LOW) // sync_in = rm_if.sync_in; forever begin mcu_cw_item mcu_cw_item; // @(posedge `CLK) wait(cw_queue.size()>0 ); mcu_cw_item = cw_queue.pop_front(); cw_data_cur = mcu_cw_item.cw_data; clock_cycle_cur = mcu_cw_item.clock_cycle; cw_valid_cur = mcu_cw_item.cw_valid; wait(adc_data_queue.size()> clock_cycle_cur + sample_depth + 4); adc_wave_cur = adc_data_queue[clock_cycle_cur+4 : clock_cycle_cur + sample_depth + 3]; `uvm_info(get_type_name(),$sformatf("mcu_cw_item.cw_data = %0h,mcu_cw_item.cycle = %0h,mcu_cw_item.cw_valid = %0h",mcu_cw_item.cw_data,mcu_cw_item.clock_cycle,mcu_cw_item.cw_valid),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("adc_wave_cur = %0p,adc_wave_cur.size = %0h",adc_wave_cur,adc_wave_cur.size()),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("adc_data_queue.size = %0h",adc_data_queue.size()),UVM_HIGH) //////////////////////////////////////////////////////////////////// //DAQ functions //////////////////////////////////////////////////////////////////// demod_valid = cw_data_cur[31:16]; if(adc_wave_cur.size()>0)begin for(i = 0; i < adc_wave_cur.size(); i++)begin adc_wave_cur[i] = adc_wave_cur[i] ^ 64'h8080_8080_8080_8080; end for(i = 0; i < adc_wave_cur.size(); i++)begin all_queue.push_back(adc_wave_cur[i][31:0]); all_queue.push_back(adc_wave_cur[i][63:32]); `uvm_info(get_type_name(),$sformatf("the %d data:adc_wave_cur[31:0] = %0h,adc_wave_cur[63:32] = %0h",i,adc_wave_cur[i][31:0],adc_wave_cur[i][63:32]),UVM_HIGH) if(adc_wave_cur[i][31:0] == 32'hb0f | adc_wave_cur[i][63:32] == 32'hb0f)begin `uvm_info(get_type_name(),("error data"),UVM_HIGH) end end `uvm_info(get_type_name(),("store wave done"),UVM_HIGH) end for(i = 0; i < `NUM_QUBIT; i++)begin iq_save_en[i] = demod_valid[i] ? (cw_data_cur[2:0]==3'b101 | cw_data_cur[13]):iq_save_en[i] ; state_save_en[i] = demod_valid[i] ? (cw_data_cur[2:0]==3'b110 | cw_data_cur[14]):state_save_en[i] ; count_save_en[i] = demod_valid[i] ? (cw_data_cur[2:0]==3'b111 | cw_data_cur[15]):count_save_en[i] ; // loc_fb_en[k] <= demod_valid_buf[k] ? (cw_data_buf[6] & !cw_data_buf[3]) : loc_fb_en[k]; // glb_fb_en[k] <= demod_valid_buf[k] ? (cw_data_buf[7] & !cw_data_buf[3]) : glb_fb_en[k]; // send_loc_vld[k] <= demod_valid_buf[k] & cw_data_buf[3] & cw_data_buf[6]; // send_glb_vld[k] <= demod_valid_buf[k] & cw_data_buf[3] & cw_data_buf[7]; daq_block( //in i, demod_valid[i], demod_freq[i], demod_width[i], para_ab0[i], para_ab1[i], para_ab2[i], para_c0[i], para_c1[i], para_c2[i], //out state_data[i] , i_sum[i] , q_sum[i] , count_state_0[i], count_state_1[i], count_state_2[i], count_state_3[i] ); qubit_state[i*2+: 2] = state_data[i]; end for(i = 0; i < `NUM_QUBIT; i++)begin if(iq_save_en[i])begin all_queue.push_back(i_sum[i]); all_queue.push_back(q_sum[i]); `uvm_info(get_type_name(),$sformatf("store i_sum[%0h] = %h",i,i_sum[i]),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("store q_sum[%0h] = %h",i,q_sum[i]),UVM_HIGH) `uvm_info(get_type_name(),("store iq_sum done"),UVM_HIGH) end end if(state_save_en)begin all_queue.push_back(qubit_state); `uvm_info(get_type_name(),$sformatf("store qubit_state = %h",qubit_state),UVM_HIGH) `uvm_info(get_type_name(),("store qubit_state done"),UVM_HIGH) end for(i = 0; i < `NUM_QUBIT; i++)begin if(count_save_en[i])begin all_queue.push_back(count_state_0[i]); all_queue.push_back(count_state_1[i]); all_queue.push_back(count_state_2[i]); all_queue.push_back(count_state_3[i]); `uvm_info(get_type_name(),("store count_state done"),UVM_HIGH) end end `uvm_info(get_type_name(),$sformatf("all_queue.size() = %0h",all_queue.size()),UVM_HIGH) end endtask task readout_daq_rm::daq_block( input bit [15:0] i , input bit demod_valid , input bit [31:0]demod_freq , input bit [31:0]demod_width , input bit [31:0]para_ab0 , input bit [31:0]para_ab1 , input bit [31:0]para_ab2 , input bit [31:0]para_c0 , input bit [31:0]para_c1 , input bit [31:0]para_c2 , ref bit [1 :0]state_data , ref bit [31:0]i_sum , ref bit [31:0]q_sum , ref bit [31:0]count_state_0 , ref bit [31:0]count_state_1 , ref bit [31:0]count_state_2 , ref bit [31:0]count_state_3 ); // codeword bit iq_sum_en = demod_valid ? cw_data_cur[4] : iq_sum_en ; bit count_add_en = demod_valid ? cw_data_cur[5] : count_add_en ; bit loc_fb_en = demod_valid ? cw_data_cur[6] & !cw_data_cur[3]: loc_fb_en ; bit glb_fb_en = demod_valid ? cw_data_cur[7] & !cw_data_cur[3]: glb_fb_en ; bit iq_clr_en = demod_valid ? cw_data_cur[8] : iq_clr_en ; bit count_clr_en = demod_valid ? cw_data_cur[9] : count_clr_en ; bit [15:0] j; bit [15:0] k; bit [31:0] base_addr; // mtf_gen signal bit [19:0] accumulator [`NUM_WAY-1 :0]; bit signed[7 :0] dds_cos[`NUM_WAY-1 :0]; bit signed[7 :0] dds_sin[`NUM_WAY-1 :0]; bit [2 :0] step_ctrl; bit const_en; bit [7 :0] weight_iq; bit [24:0] read_addr; bit [24:0] ram_addr; bit [31:0] mtf_queue_i[$]; bit [31:0] mtf_queue_q[$]; bit [31:0] match_filter_i; bit [31:0] match_filter_q; bit signed[15:0] mtf_i_temp[`NUM_WAY-1:0]; bit signed[15:0] mtf_q_temp[`NUM_WAY-1:0]; bit signed[7 :0] i_mult; bit signed[7 :0] q_mult; bit [7 :0] byte_sel; bit [9 :0] address[`NUM_WAY-1:0]; bit signed[7 :0] mtf_i[`NUM_WAY-1:0]; bit signed[7 :0] mtf_q[`NUM_WAY-1:0]; //demod_algorithm signal bit signed[15:0] demod_i[`NUM_WAY-1:0]; bit signed[15:0] demod_q[`NUM_WAY-1:0]; bit [63:0] adc_wave_one; bit signed[31:0] demod_i_sum[`NUM_WAY-1:0]; bit signed[31:0] demod_q_sum[`NUM_WAY-1:0]; bit signed[31:0] demod_i_sum_final; bit signed[31:0] demod_q_sum_final; //iq_sum signal bit [15:0] scale_data_i; bit [15:0] scale_data_q; //state_estimate bit [2:0] compare_result; base_addr = 25'h500000 + 25'h400 * i; `uvm_info(get_type_name(),$sformatf("daq_func_ctrl = %h",func_ctrl),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("demod_freq = %h",demod_freq),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("channel %0h : base_addr = %h",i,base_addr),UVM_HIGH) for(int k = 0; k < demod_width ; k++)begin //mtf_gen bit [19:0] fcw = demod_freq[31:12]; bit [19:0] fcw_buf = {demod_freq[31:12],3'b0}; bit [19:0] pcw_buf [`NUM_WAY-1 :0]; for(int j = 0; j < `NUM_WAY; j++)begin pcw_buf[j] = {demod_freq[11:0],8'b0} + fcw*(j+1); accumulator[j] = fcw_buf*k + pcw_buf[j]; address[j] = accumulator[j][19:10]; dds(address[j],dds_cos[j],dds_sin[j]); `uvm_info(get_type_name(),$sformatf("channel %d:address = %h; dds_cos= %h; dds_sin=%h",j,address[j],dds_cos[j],dds_sin[j]),UVM_HIGH) end step_ctrl = func_ctrl[6:4]; const_en = func_ctrl[7]; weight_iq = func_ctrl[15:8]; if(const_en)begin i_mult = weight_iq; q_mult = weight_iq; end else begin ram_addr = base_addr+{read_addr[12:6],2'b0}; match_filter_i = ram_data[ram_addr]; match_filter_q = ram_data[ram_addr + 25'h200]; //mtf_queue_i.push_back(match_filter_i); //mtf_queue_q.push_back(match_filter_q); byte_sel = read_addr[5:4]; i_mult = match_filter_i[byte_sel*8+:8]; q_mult = match_filter_q[byte_sel*8+:8]; case(step_ctrl) 3'b000 : read_addr = read_addr + 16; 3'b001 : read_addr = read_addr + 8; 3'b010 : read_addr = read_addr + 4; 3'b011 : read_addr = read_addr + 2; 3'b100 : read_addr = read_addr + 1; endcase `uvm_info(get_type_name(),$sformatf("step_ctrl = %h",step_ctrl),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("read_addr = %h",read_addr),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("ram_addr= %h",ram_addr),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("match_filter_i= %h",match_filter_i),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("byte_sel= %h",byte_sel),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("i_mult= %h",i_mult),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("q_mult= %h",q_mult),UVM_HIGH) end for(int j = 0; j < `NUM_WAY; j++)begin mtf_i_temp[j] = i_mult*dds_cos[j]; mtf_q_temp[j] = q_mult*dds_sin[j]; mtf_i[j] = {mtf_i_temp[j][14],mtf_i_temp[j][13:7]}; mtf_q[j] = {mtf_q_temp[j][14],mtf_q_temp[j][13:7]}; `uvm_info(get_type_name(),$sformatf("mtf_i_temp[%h] = %h",j,mtf_i_temp[j]),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("mtf_q_temp[%h] = %h",j,mtf_q_temp[j]),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("mtf_i[%h] = %h",j,mtf_i[j]),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("mtf_q[%h] = %h",j,mtf_q[j]),UVM_HIGH) end //demod_algorithm if(adc_wave_cur.size()>0)begin adc_wave_one = adc_wave_cur.pop_front(); `uvm_info(get_type_name(),$sformatf("adc_wave_one = %h",adc_wave_one),UVM_HIGH) end else begin adc_wave_one = 64'b0; end for(j = 0; j < `NUM_WAY; j++)begin demod_i[j] = $signed(adc_wave_one[j*8+:8])*mtf_i[j]; demod_q[j] = $signed(adc_wave_one[j*8+:8])*mtf_q[j]; demod_i_sum[j] = demod_i_sum[j] + demod_i[j]; demod_q_sum[j] = demod_q_sum[j] + demod_q[j]; // `uvm_info(get_type_name(),$sformatf("adc_wave_one = %h",adc_wave_one),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("demod_i[%h] = %h,mtf_i[%0h]=%0h",j,demod_i[j],j,mtf_i[j]),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("demod_q[%h] = %h,mtf_q[%0h]=%0h",j,demod_q[j],j,mtf_q[j]),UVM_HIGH) end for(j = 0; j < `NUM_WAY; j++)begin `uvm_info(get_type_name(),$sformatf("demod_i_sum[%h]= %h",j,demod_i_sum[j]),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("demod_q_sum[%h]= %h",j,demod_q_sum[j]),UVM_HIGH) end end for(j = 0; j < `NUM_WAY; j++)begin demod_i_sum_final = demod_i_sum_final + demod_i_sum[j]; demod_q_sum_final = demod_q_sum_final + demod_q_sum[j]; end `uvm_info(get_type_name(),$sformatf("demod_i_sum_final= %h",demod_i_sum_final),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("demod_q_sum_final= %h",demod_q_sum_final),UVM_HIGH) //iq_sum scale_data_i = func_ctrl[3] ? demod_i_sum_final[31:12] : demod_i_sum_final[27:8]; scale_data_q = func_ctrl[3] ? demod_q_sum_final[31:12] : demod_q_sum_final[27:8]; if(iq_sum_en) begin i_sum = i_sum + scale_data_i; q_sum = q_sum + scale_data_q; end else if(iq_clr_en)begin i_sum = 0; q_sum = 0; end `uvm_info(get_type_name(),$sformatf("iq_sum_en= %h",iq_sum_en),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("scale_data_i = %h",scale_data_i),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("i_sum = %h",i_sum),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("scale_data_q = %h",scale_data_q),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("q_sum = %h",q_sum),UVM_HIGH) //state_estimate compare_result[0] = (para_ab0[15:0]*demod_i_sum_final + para_ab0[31:16]*demod_q_sum_final <= para_c0) ? 1 : 0; compare_result[1] = (para_ab1[15:0]*demod_i_sum_final + para_ab1[31:16]*demod_q_sum_final <= para_c1) ? 1 : 0; compare_result[2] = (para_ab2[15:0]*demod_i_sum_final + para_ab2[31:16]*demod_q_sum_final <= para_c2) ? 1 : 0; if(compare_result[0] & (~compare_result[1])) state_data = 2'b00; else if (compare_result[1] & (~compare_result[2])) state_data = 2'b01; else if (compare_result[2] & (~compare_result[0])) state_data = 2'b10; else state_data = 2'b11; `uvm_info(get_type_name(),$sformatf("compare_result = %b ,state_data = %h",compare_result,state_data),UVM_HIGH) //state_statistics if(count_clr_en)begin count_state_0 = 32'd0; count_state_1 = 32'd0; count_state_2 = 32'd0; count_state_3 = 32'd0; end else if(count_add_en)begin count_state_0 = (state_data == 2'b00) ? count_state_0 + 1 : count_state_0; count_state_1 = (state_data == 2'b01) ? count_state_1 + 1 : count_state_1; count_state_2 = (state_data == 2'b10) ? count_state_2 + 1 : count_state_2; count_state_3 = (state_data == 2'b11) ? count_state_3 + 1 : count_state_3; end `uvm_info(get_type_name(),$sformatf("count_clr_en = %h",count_clr_en),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("count_add_en = %h",count_add_en),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("count_state_0 = %h",count_state_0),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("count_state_1 = %h",count_state_1),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("count_state_2 = %h",count_state_2),UVM_HIGH) `uvm_info(get_type_name(),$sformatf("count_state_3 = %h",count_state_3),UVM_HIGH) endtask task readout_daq_rm::dds( input bit unsigned[9 :0] address, output bit signed[7 :0] dds_cos, output bit signed[7 :0] dds_sin ); bit [6:0]coefficients [0:255] = { 7'd0, 7'd1, 7'd2, 7'd2, 7'd3, 7'd4, 7'd5, 7'd5, 7'd6, 7'd7, 7'd8, 7'd9, 7'd9, 7'd10, 7'd11, 7'd12, 7'd12, 7'd13, 7'd14, 7'd15, 7'd16, 7'd16, 7'd17, 7'd18, 7'd19, 7'd19, 7'd20, 7'd21, 7'd22, 7'd23, 7'd23, 7'd24, 7'd25, 7'd26, 7'd26, 7'd27, 7'd28, 7'd29, 7'd29, 7'd30, 7'd31, 7'd32, 7'd32, 7'd33, 7'd34, 7'd35, 7'd36, 7'd36, 7'd37, 7'd38, 7'd39, 7'd39, 7'd40, 7'd41, 7'd41, 7'd42, 7'd43, 7'd44, 7'd44, 7'd45, 7'd46, 7'd47, 7'd47, 7'd48, 7'd49, 7'd50, 7'd50, 7'd51, 7'd52, 7'd52, 7'd53, 7'd54, 7'd55, 7'd55, 7'd56, 7'd57, 7'd57, 7'd58, 7'd59, 7'd59, 7'd60, 7'd61, 7'd61, 7'd62, 7'd63, 7'd64, 7'd64, 7'd65, 7'd66, 7'd66, 7'd67, 7'd68, 7'd68, 7'd69, 7'd70, 7'd70, 7'd71, 7'd71, 7'd72, 7'd73, 7'd73, 7'd74, 7'd75, 7'd75, 7'd76, 7'd77, 7'd77, 7'd78, 7'd78, 7'd79, 7'd80, 7'd80, 7'd81, 7'd81, 7'd82, 7'd83, 7'd83, 7'd84, 7'd84, 7'd85, 7'd86, 7'd86, 7'd87, 7'd87, 7'd88, 7'd88, 7'd89, 7'd90, 7'd90, 7'd91, 7'd91, 7'd92, 7'd92, 7'd93, 7'd93, 7'd94, 7'd94, 7'd95, 7'd96, 7'd96, 7'd97, 7'd97, 7'd98, 7'd98, 7'd99, 7'd99, 7'd100, 7'd100, 7'd101, 7'd101, 7'd101, 7'd102, 7'd102, 7'd103, 7'd103, 7'd104, 7'd104, 7'd105, 7'd105, 7'd106, 7'd106, 7'd106, 7'd107, 7'd107, 7'd108, 7'd108, 7'd109, 7'd109, 7'd109, 7'd110, 7'd110, 7'd111, 7'd111, 7'd111, 7'd112, 7'd112, 7'd112, 7'd113, 7'd113, 7'd114, 7'd114, 7'd114, 7'd115, 7'd115, 7'd115, 7'd116, 7'd116, 7'd116, 7'd117, 7'd117, 7'd117, 7'd117, 7'd118, 7'd118, 7'd118, 7'd119, 7'd119, 7'd119, 7'd120, 7'd120, 7'd120, 7'd120, 7'd121, 7'd121, 7'd121, 7'd121, 7'd122, 7'd122, 7'd122, 7'd122, 7'd122, 7'd123, 7'd123, 7'd123, 7'd123, 7'd123, 7'd124, 7'd124, 7'd124, 7'd124, 7'd124, 7'd125, 7'd125, 7'd125, 7'd125, 7'd125, 7'd125, 7'd125, 7'd126, 7'd126, 7'd126, 7'd126, 7'd126, 7'd126, 7'd126, 7'd126, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127, 7'd127 }; //dds_sin if (address[9:8] == 2'b00) begin dds_sin = coefficients[address[7:0]]; // `uvm_info(get_type_name(),$sformatf("address[7:0] = %h",address[7:0]),UVM_LOW) end else if(address[9:8] == 2'b01) begin dds_sin = coefficients[(address[7:0] == 8'b0) ? 8'hff : 8'd256-address[7:0]]; // `uvm_info(get_type_name(),$sformatf("8'd255-address[7:0]= %h",8'd255-address[7:0]),UVM_LOW) end else if (address[9:8] == 2'b10) begin dds_sin = -coefficients[address[7:0]]; // `uvm_info(get_type_name(),$sformatf("address[7:0] = %h",address[7:0]),UVM_LOW) end else if(address[9:8] == 2'b11) begin dds_sin = -coefficients[(address[7:0] == 8'b0) ? 8'hff : 8'd256-address[7:0]]; // `uvm_info(get_type_name(),$sformatf("8'd255-address[7:0] = %h",8'd255-address[7:0]),UVM_LOW) end //dds_cos if (address[9:8] == 2'b00) begin dds_cos = coefficients[(address[7:0] == 8'b0) ? 8'hff : 8'd256-address[7:0]]; end else if(address[9:8] == 2'b01) begin dds_cos = -coefficients[address[7:0]]; end else if (address[9:8] == 2'b10) begin dds_cos = -coefficients[(address[7:0] == 8'b0) ? 8'hff : 8'd256-address[7:0]]; end else if(address[9:8] == 2'b11) begin dds_cos = coefficients[address[7:0]]; end endtask : dds task readout_daq_rm::get_config_data(); forever begin @(posedge `CLK); ///////////////////////////////////////////////////// //daq_config_reg ///////////////////////////////////////////////////// /* if(ram_data.exists(`DAQ_MCU_TIMER)) begin mcu_timer = ram_data[`DAQ_MCU_TIMER]; end if(ram_data.exists(`DAQ_MCU_COUNTER)) begin mcu_counter = ram_data[`DAQ_MCU_COUNTER]; end if(ram_data.exists(`DAQ_LOCAL_STATE)) begin loc_state = ram_data[`DAQ_LOCAL_STATE]; end if(ram_data.exists(`DAQ_GLB_STATE)) begin glb_state = ram_data[`DAQ_GLB_STATE]; end if(ram_data.exists(`DAQ_FEED_DATA)) begin feed_data = ram_data[`DAQ_FEED_DATA]; end if(ram_data.exists(`DAQ_SRAM_COUNT)) begin sram_count= ram_data[`DAQ_SRAM_COUNT]; end if(ram_data.exists(`DAQ_PUSH_COUNT)) begin push_count = ram_data[`DAQ_PUSH_COUNT]; end */ if(ram_data.exists(`DAQ_SEND_DATA)) begin send_data = ram_data[`DAQ_SEND_DATA]; end if(ram_data.exists(`DAQ_COMMAND)) begin command = ram_data[`DAQ_COMMAND]; end if(ram_data.exists(`DAQ_FUNC)) begin func_ctrl = ram_data[`DAQ_FUNC]; end else begin func_ctrl = 32'h8000; end if(ram_data.exists(`WAVE_SAMPLE_DEPTH)) begin sample_depth = ram_data[`WAVE_SAMPLE_DEPTH]; end else begin sample_depth = 32'h100; end if(ram_data.exists(`READ_THRESHOLD)) begin int_threshold = ram_data[`READ_THRESHOLD]; end else begin int_threshold = 32'h100; end /* if(ram_data.exists(`QUBIT_STATE)) begin qubit_state = ram_data[`QUBIT_STATE]; end */ if(ram_data.exists(`READ_REQ_CTRL)) begin read_req_ctrl= ram_data[`READ_REQ_CTRL]; end else begin read_req_ctrl= 32'h40004; end ///////////////////////////////////////////////////// //demod_width[15:0] //////////////////////////////////////////////////// if(ram_data.exists(`DEMOD_WIDTH_Q0)) begin demod_width[0] = ram_data[`DEMOD_WIDTH_Q0]; // `uvm_info(get_type_name(),$sformatf("demod_width_q0=%0h",demod_width[0]),UVM_LOW) end else begin demod_width[0] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q1)) begin demod_width[1] = ram_data[`DEMOD_WIDTH_Q1]; end else begin demod_width[1] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q2)) begin demod_width[2] = ram_data[`DEMOD_WIDTH_Q2]; end else begin demod_width[2] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q3)) begin demod_width[3] = ram_data[`DEMOD_WIDTH_Q3]; end else begin demod_width[3] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q4)) begin demod_width[4] = ram_data[`DEMOD_WIDTH_Q4]; end else begin demod_width[4] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q5)) begin demod_width[5] = ram_data[`DEMOD_WIDTH_Q5]; end else begin demod_width[5] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q6)) begin demod_width[6] = ram_data[`DEMOD_WIDTH_Q6]; end else begin demod_width[6] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q7)) begin demod_width[7] = ram_data[`DEMOD_WIDTH_Q7]; end else begin demod_width[7] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q8)) begin demod_width[8] = ram_data[`DEMOD_WIDTH_Q8]; end else begin demod_width[8] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q9)) begin demod_width[9] = ram_data[`DEMOD_WIDTH_Q9]; end else begin demod_width[9] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q10)) begin demod_width[10] = ram_data[`DEMOD_WIDTH_Q10]; end else begin demod_width[10] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q11)) begin demod_width[11] = ram_data[`DEMOD_WIDTH_Q11]; end else begin demod_width[11] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q12)) begin demod_width[12] = ram_data[`DEMOD_WIDTH_Q12]; end else begin demod_width[12] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q13)) begin demod_width[13] = ram_data[`DEMOD_WIDTH_Q13]; end else begin demod_width[13] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q14)) begin demod_width[14] = ram_data[`DEMOD_WIDTH_Q14]; end else begin demod_width[14] = 32'h100; end if(ram_data.exists(`DEMOD_WIDTH_Q15)) begin demod_width[15] = ram_data[`DEMOD_WIDTH_Q15]; end else begin demod_width[15] = 32'h100; end ///////////////////////////////////////////////////// //demod_freq[15:0] //////////////////////////////////////////////////// if(ram_data.exists(`DEMOD_FREQ_Q0)) begin demod_freq[0] = ram_data[`DEMOD_FREQ_Q0]; // `uvm_info(get_type_name(),$sformatf("demod_freq=%0h",demod_freq[0]),UVM_LOW) end else begin demod_freq[0] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q1)) begin demod_freq[1] = ram_data[`DEMOD_FREQ_Q1]; end else begin demod_freq[1] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q2)) begin demod_freq[2] = ram_data[`DEMOD_FREQ_Q2]; end else begin demod_freq[2] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q3)) begin demod_freq[3] = ram_data[`DEMOD_FREQ_Q3]; end else begin demod_freq[3] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q4)) begin demod_freq[4] = ram_data[`DEMOD_FREQ_Q4]; end else begin demod_freq[4] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q5)) begin demod_freq[5] = ram_data[`DEMOD_FREQ_Q5]; end else begin demod_freq[5] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q6)) begin demod_freq[6] = ram_data[`DEMOD_FREQ_Q6]; end else begin demod_freq[6] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q7)) begin demod_freq[7] = ram_data[`DEMOD_FREQ_Q7]; end else begin demod_freq[7] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q8)) begin demod_freq[8] = ram_data[`DEMOD_FREQ_Q8]; end else begin demod_freq[8] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q9)) begin demod_freq[9] = ram_data[`DEMOD_FREQ_Q9]; end else begin demod_freq[9] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q10)) begin demod_freq[10] = ram_data[`DEMOD_FREQ_Q10]; end else begin demod_freq[10] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q11)) begin demod_freq[11] = ram_data[`DEMOD_FREQ_Q11]; end else begin demod_freq[11] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q12)) begin demod_freq[12] = ram_data[`DEMOD_FREQ_Q12]; end else begin demod_freq[12] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q13)) begin demod_freq[13] = ram_data[`DEMOD_FREQ_Q13]; end else begin demod_freq[13] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q14)) begin demod_freq[14] = ram_data[`DEMOD_FREQ_Q14]; end else begin demod_freq[14] = 32'h1000_0000; end if(ram_data.exists(`DEMOD_FREQ_Q15)) begin demod_freq[15] = ram_data[`DEMOD_FREQ_Q15]; end else begin demod_freq[15] = 32'h1000_0000; end ///////////////////////////////////////////////////// //para_ab0[15:0] para_c0[15:0] //////////////////////////////////////////////////// if(ram_data.exists(`PARA_AB0_Q0)) begin para_ab0[0] = ram_data[`PARA_AB0_Q0]; end if(ram_data.exists(`PARA_AB0_Q1)) begin para_ab0[1] = ram_data[`PARA_AB0_Q1]; end if(ram_data.exists(`PARA_AB0_Q2)) begin para_ab0[2] = ram_data[`PARA_AB0_Q2]; end if(ram_data.exists(`PARA_AB0_Q3)) begin para_ab0[3] = ram_data[`PARA_AB0_Q3]; end if(ram_data.exists(`PARA_AB0_Q4)) begin para_ab0[4] = ram_data[`PARA_AB0_Q4]; end if(ram_data.exists(`PARA_AB0_Q5)) begin para_ab0[5] = ram_data[`PARA_AB0_Q5]; end if(ram_data.exists(`PARA_AB0_Q6)) begin para_ab0[6] = ram_data[`PARA_AB0_Q6]; end if(ram_data.exists(`PARA_AB0_Q7)) begin para_ab0[7] = ram_data[`PARA_AB0_Q7]; end if(ram_data.exists(`PARA_AB0_Q8)) begin para_ab0[8] = ram_data[`PARA_AB0_Q8]; end if(ram_data.exists(`PARA_AB0_Q9)) begin para_ab0[9] = ram_data[`PARA_AB0_Q9]; end if(ram_data.exists(`PARA_AB0_Q10)) begin para_ab0[10] = ram_data[`PARA_AB0_Q10]; end if(ram_data.exists(`PARA_AB0_Q11)) begin para_ab0[11] = ram_data[`PARA_AB0_Q11]; end if(ram_data.exists(`PARA_AB0_Q12)) begin para_ab0[12] = ram_data[`PARA_AB0_Q12]; end if(ram_data.exists(`PARA_AB0_Q13)) begin para_ab0[13] = ram_data[`PARA_AB0_Q13]; end if(ram_data.exists(`PARA_AB0_Q14)) begin para_ab0[14] = ram_data[`PARA_AB0_Q14]; end if(ram_data.exists(`PARA_AB0_Q15)) begin para_ab0[15] = ram_data[`PARA_AB0_Q15]; end if(ram_data.exists(`PARA_C0_Q0)) begin para_c0[0] = ram_data[`PARA_C0_Q0]; end if(ram_data.exists(`PARA_C0_Q1)) begin para_c0[1] = ram_data[`PARA_C0_Q1]; end if(ram_data.exists(`PARA_C0_Q2)) begin para_c0[2] = ram_data[`PARA_C0_Q2]; end if(ram_data.exists(`PARA_C0_Q3)) begin para_c0[3] = ram_data[`PARA_C0_Q3]; end if(ram_data.exists(`PARA_C0_Q4)) begin para_c0[4] = ram_data[`PARA_C0_Q4]; end if(ram_data.exists(`PARA_C0_Q5)) begin para_c0[5] = ram_data[`PARA_C0_Q5]; end if(ram_data.exists(`PARA_C0_Q6)) begin para_c0[6] = ram_data[`PARA_C0_Q6]; end if(ram_data.exists(`PARA_C0_Q7)) begin para_c0[7] = ram_data[`PARA_C0_Q7]; end if(ram_data.exists(`PARA_C0_Q8)) begin para_c0[8] = ram_data[`PARA_C0_Q8]; end if(ram_data.exists(`PARA_C0_Q9)) begin para_c0[9] = ram_data[`PARA_C0_Q9]; end if(ram_data.exists(`PARA_C0_Q10)) begin para_c0[10] = ram_data[`PARA_C0_Q10]; end if(ram_data.exists(`PARA_C0_Q11)) begin para_c0[11] = ram_data[`PARA_C0_Q11]; end if(ram_data.exists(`PARA_C0_Q12)) begin para_c0[12] = ram_data[`PARA_C0_Q12]; end if(ram_data.exists(`PARA_C0_Q13)) begin para_c0[13] = ram_data[`PARA_C0_Q13]; end if(ram_data.exists(`PARA_C0_Q14)) begin para_c0[14] = ram_data[`PARA_C0_Q14]; end if(ram_data.exists(`PARA_C0_Q15)) begin para_c0[15] = ram_data[`PARA_C0_Q15]; end ///////////////////////////////////////////////////// //para_ab1[15:0] para_c1[15:0] //////////////////////////////////////////////////// if(ram_data.exists(`PARA_AB1_Q0)) begin para_ab1[0] = ram_data[`PARA_AB1_Q0]; end if(ram_data.exists(`PARA_AB1_Q1)) begin para_ab1[1] = ram_data[`PARA_AB1_Q1]; end if(ram_data.exists(`PARA_AB1_Q2)) begin para_ab1[2] = ram_data[`PARA_AB1_Q2]; end if(ram_data.exists(`PARA_AB1_Q3)) begin para_ab1[3] = ram_data[`PARA_AB1_Q3]; end if(ram_data.exists(`PARA_AB1_Q4)) begin para_ab1[4] = ram_data[`PARA_AB1_Q4]; end if(ram_data.exists(`PARA_AB1_Q5)) begin para_ab1[5] = ram_data[`PARA_AB1_Q5]; end if(ram_data.exists(`PARA_AB1_Q6)) begin para_ab1[6] = ram_data[`PARA_AB1_Q6]; end if(ram_data.exists(`PARA_AB1_Q7)) begin para_ab1[7] = ram_data[`PARA_AB1_Q7]; end if(ram_data.exists(`PARA_AB1_Q8)) begin para_ab1[8] = ram_data[`PARA_AB1_Q8]; end if(ram_data.exists(`PARA_AB1_Q9)) begin para_ab1[9] = ram_data[`PARA_AB1_Q9]; end if(ram_data.exists(`PARA_AB1_Q10)) begin para_ab1[10] = ram_data[`PARA_AB1_Q10]; end if(ram_data.exists(`PARA_AB1_Q11)) begin para_ab1[11] = ram_data[`PARA_AB1_Q11]; end if(ram_data.exists(`PARA_AB1_Q12)) begin para_ab1[12] = ram_data[`PARA_AB1_Q12]; end if(ram_data.exists(`PARA_AB1_Q13)) begin para_ab1[13] = ram_data[`PARA_AB1_Q13]; end if(ram_data.exists(`PARA_AB1_Q14)) begin para_ab1[14] = ram_data[`PARA_AB1_Q14]; end if(ram_data.exists(`PARA_AB1_Q15)) begin para_ab1[15] = ram_data[`PARA_AB1_Q15]; end if(ram_data.exists(`PARA_C1_Q0)) begin para_c1[0] = ram_data[`PARA_C1_Q0]; end if(ram_data.exists(`PARA_C1_Q1)) begin para_c1[1] = ram_data[`PARA_C1_Q1]; end if(ram_data.exists(`PARA_C1_Q2)) begin para_c1[2] = ram_data[`PARA_C1_Q2]; end if(ram_data.exists(`PARA_C1_Q3)) begin para_c1[3] = ram_data[`PARA_C1_Q3]; end if(ram_data.exists(`PARA_C1_Q4)) begin para_c1[4] = ram_data[`PARA_C1_Q4]; end if(ram_data.exists(`PARA_C1_Q5)) begin para_c1[5] = ram_data[`PARA_C1_Q5]; end if(ram_data.exists(`PARA_C1_Q6)) begin para_c1[6] = ram_data[`PARA_C1_Q6]; end if(ram_data.exists(`PARA_C1_Q7)) begin para_c1[7] = ram_data[`PARA_C1_Q7]; end if(ram_data.exists(`PARA_C1_Q8)) begin para_c1[8] = ram_data[`PARA_C1_Q8]; end if(ram_data.exists(`PARA_C1_Q9)) begin para_c1[9] = ram_data[`PARA_C1_Q9]; end if(ram_data.exists(`PARA_C1_Q10)) begin para_c1[10] = ram_data[`PARA_C1_Q10]; end if(ram_data.exists(`PARA_C1_Q11)) begin para_c1[11] = ram_data[`PARA_C1_Q11]; end if(ram_data.exists(`PARA_C1_Q12)) begin para_c1[12] = ram_data[`PARA_C1_Q12]; end if(ram_data.exists(`PARA_C1_Q13)) begin para_c1[13] = ram_data[`PARA_C1_Q13]; end if(ram_data.exists(`PARA_C1_Q14)) begin para_c1[14] = ram_data[`PARA_C1_Q14]; end if(ram_data.exists(`PARA_C1_Q15)) begin para_c1[15] = ram_data[`PARA_C1_Q15]; end ///////////////////////////////////////////////////// //para_ab2[15:0] para_c2[15:0] //////////////////////////////////////////////////// if(ram_data.exists(`PARA_AB2_Q0)) begin para_ab2[0] = ram_data[`PARA_AB2_Q0]; end if(ram_data.exists(`PARA_AB2_Q1)) begin para_ab2[1] = ram_data[`PARA_AB2_Q1]; end if(ram_data.exists(`PARA_AB2_Q2)) begin para_ab2[2] = ram_data[`PARA_AB2_Q2]; end if(ram_data.exists(`PARA_AB2_Q3)) begin para_ab2[3] = ram_data[`PARA_AB2_Q3]; end if(ram_data.exists(`PARA_AB2_Q4)) begin para_ab2[4] = ram_data[`PARA_AB2_Q4]; end if(ram_data.exists(`PARA_AB2_Q5)) begin para_ab2[5] = ram_data[`PARA_AB2_Q5]; end if(ram_data.exists(`PARA_AB2_Q6)) begin para_ab2[6] = ram_data[`PARA_AB2_Q6]; end if(ram_data.exists(`PARA_AB2_Q7)) begin para_ab2[7] = ram_data[`PARA_AB2_Q7]; end if(ram_data.exists(`PARA_AB2_Q8)) begin para_ab2[8] = ram_data[`PARA_AB2_Q8]; end if(ram_data.exists(`PARA_AB2_Q9)) begin para_ab2[9] = ram_data[`PARA_AB2_Q9]; end if(ram_data.exists(`PARA_AB2_Q10)) begin para_ab2[10] = ram_data[`PARA_AB2_Q10]; end if(ram_data.exists(`PARA_AB2_Q11)) begin para_ab2[11] = ram_data[`PARA_AB2_Q11]; end if(ram_data.exists(`PARA_AB2_Q12)) begin para_ab2[12] = ram_data[`PARA_AB2_Q12]; end if(ram_data.exists(`PARA_AB2_Q13)) begin para_ab2[13] = ram_data[`PARA_AB2_Q13]; end if(ram_data.exists(`PARA_AB2_Q14)) begin para_ab2[14] = ram_data[`PARA_AB2_Q14]; end if(ram_data.exists(`PARA_AB2_Q15)) begin para_ab2[15] = ram_data[`PARA_AB2_Q15]; end if(ram_data.exists(`PARA_C2_Q0)) begin para_c2[0] = ram_data[`PARA_C2_Q0]; end if(ram_data.exists(`PARA_C2_Q1)) begin para_c2[1] = ram_data[`PARA_C2_Q1]; end if(ram_data.exists(`PARA_C2_Q2)) begin para_c2[2] = ram_data[`PARA_C2_Q2]; end if(ram_data.exists(`PARA_C2_Q3)) begin para_c2[3] = ram_data[`PARA_C2_Q3]; end if(ram_data.exists(`PARA_C2_Q4)) begin para_c2[4] = ram_data[`PARA_C2_Q4]; end if(ram_data.exists(`PARA_C2_Q5)) begin para_c2[5] = ram_data[`PARA_C2_Q5]; end if(ram_data.exists(`PARA_C2_Q6)) begin para_c2[6] = ram_data[`PARA_C2_Q6]; end if(ram_data.exists(`PARA_C2_Q7)) begin para_c2[7] = ram_data[`PARA_C2_Q7]; end if(ram_data.exists(`PARA_C2_Q8)) begin para_c2[8] = ram_data[`PARA_C2_Q8]; end if(ram_data.exists(`PARA_C2_Q9)) begin para_c2[9] = ram_data[`PARA_C2_Q9]; end if(ram_data.exists(`PARA_C2_Q10)) begin para_c2[10] = ram_data[`PARA_C2_Q10]; end if(ram_data.exists(`PARA_C2_Q11)) begin para_c2[11] = ram_data[`PARA_C2_Q11]; end if(ram_data.exists(`PARA_C2_Q12)) begin para_c2[12] = ram_data[`PARA_C2_Q12]; end if(ram_data.exists(`PARA_C2_Q13)) begin para_c2[13] = ram_data[`PARA_C2_Q13]; end if(ram_data.exists(`PARA_C2_Q14)) begin para_c2[14] = ram_data[`PARA_C2_Q14]; end if(ram_data.exists(`PARA_C2_Q15)) begin para_c2[15] = ram_data[`PARA_C2_Q15]; end end endtask `endif