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新增spi_rw模块，新增daq_rm的输出port

This commit is contained in:
zhangyz 2025-03-20 15:28:32 +08:00
parent afae1bd680
commit cdc0bef9d9
2 changed files with 192 additions and 11 deletions
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61
readout_daq_rm.sv
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@ -10,10 +10,11 @@
`ifdef READOUT_DAQ_RM
`ifndef READOUT_DAQ_RM
`define READOUT_DAQ_RM
//import uvm_pkg::*;
//import
class readout_daq_rm extends uvm_component;
`uvm_component_utils(readout_daq_rm);
@ -21,13 +22,15 @@ class readout_daq_rm extends uvm_component;
uvm_blocking_get_port #(EZQ_readout_adc_item) adc_get_port; //get adc wave
uvm_blocking_get_port #(mcu_cw_item) mcu_get_port; //从mcu获取带时间戳的包，包含cw，time
uvm_analysis_port #(spi_item) spi_rm2scb_port; //send spi_item
spi_item spi_item_2scb_queue[$];
extern function new(string name,uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern task get_mcu_cw_item();
extern task get_adc_item();
extern task daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref int clock_cycle);
extern task daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref int clock_cycle, ref spi_item_2scb_queue[$]);
extern task send_spi_item();
extern task daq_block(
ref logic [31:0]i,
ref logic [31:0]cw_data ,
@ -38,7 +41,6 @@ class readout_daq_rm extends uvm_component;
ref logic [31:0]para_ab1 ,
ref logic [31:0]para_ab2 ,
ref logic [31:0]para_c0 ,
ref logic [31:0]para_c0 ,
ref logic [31:0]para_c1 ,
ref logic [31:0]para_c2 ,
ref logic [1 :0]state_data ,
@ -68,10 +70,10 @@ class readout_daq_rm extends uvm_component;
);
static int NUM_WAY = 8;
static int NUM_QUBIT = 16;
bit int clock_cycle ;
int clock_cycle ;
bit [31:0] cw_data ;
logic [63:0] adc_wave ;
endclass
function readout_daq_rm::new(string name,uvm_component parent);
@ -102,7 +104,17 @@ task readout_daq_rm::get_mcu_cw_item();
mcu_get_port.get(mcu_cw_item);
clock_cycle = mcu_cw_item.clock_cycle;
cw_data = mcu_cw_item.cw_data;
`uvm_info(get_type_name(),$sformatf("mcu_cw_data = %0h,mcu_cycle = %0h",mcu_cw_item.cw_data,mcu_cw_item.clock_cycle),UVM_LOW)
`uvm_info(get_type_name(),$sformatf("daq_mcu_cw_data = %0h,daq_mcu_cycle = %0h",mcu_cw_item.cw_data,mcu_cw_item.clock_cycle),UVM_LOW)
end
endtask
task send_spi_item();
spi_item spi_item;
forever begin
if(spi_item_2scb_queue.size > 0)
spi_item = spi_item_2scb_queue.pop_front();
spi_rm2scb_port.write(spi_item);
`uvm_info(get_type_name(),$sformatf("spi_item_data = %0h",spi_item.data),UVM_LOW)
end
endtask
@ -111,8 +123,8 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task
task get_mcu_cw_item();
task get_adc_item();
task daq_exe(cw_data,clock_cycle,adc_wave);
task send_spi_item();
join
endtask
@ -133,7 +145,7 @@ task readout_daq_rm::daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref
logic [31:0] int_threshold;
logic [31:0] qubit_state;
logic [31:0] read_req_ctrl;
spi_item spi_item;
logic [31:0] demod_width [15:0];
logic [31:0] demod_freq [15:0];
logic [31:0] count_state_0 [15:0];
@ -352,8 +364,35 @@ task readout_daq_rm::daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref
.i_sum (i_sum ),
.q_sum (q_sum )
);
//解模数据、态状态、态统计数据，通过spi_item发送给scb,目前只带数据，wave未发送
spi_item.data = qubit_state;
spi_item_2scb_queue.push_back(spi_item);
foreach (count_state_0[i]) begin
spi_item.data = count_state_0[i];
spi_item_2scb_queue.push_back(spi_item);
end
foreach (count_state_1[i]) begin
spi_item.data = count_state_1[i];
spi_item_2scb_queue.push_back(spi_item);
end
foreach (count_state_2[i]) begin
spi_item.data = count_state_2[i];
spi_item_2scb_queue.push_back(spi_item);
end
foreach (count_state_3[i]) begin
spi_item.data = count_state_3[i];
spi_item_2scb_queue.push_back(spi_item);
end
foreach (i_sum[i]) begin
spi_item.data = i_sum[i];
spi_item_2scb_queue.push_back(spi_item);
end
foreach (q_sum[i]) begin
spi_item.data = q_sum[i];
spi_item_2scb_queue.push_back(spi_item);
end
endtask
task readout_daq_rm::daq_block(

142
spi_rw.sv Normal file
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@ -0,0 +1,142 @@
//given a spi_item, and read or write reg_mems.
class spi_rw;
function rw(ref spi_item spi_pkg);
int len = spi_pkg.data.size();
int max_len = 0;
bit [24:0] start;
bit [19:0] addr ;
int i = 0;
start = spi_pkg.addr;
case(start[24:20])
5'h00 : max_len = 32;
5'h01 : max_len = (start[9:8]==2'b01) ? 52 :
(start[9:8]==2'b10) ? 16 :
(start[9:8]==2'b11) ? 44 :
0;
5'h02 : max_len = 32768;
5'h03 : max_len = 32768;
5'h04 : max_len = 1024;
5'h05 : max_len = 524288;
5'h06 : max_len = 524288;
5'h07 : max_len = 32768;
5'h08 : max_len = 32768;
5'h09 : max_len = 80;
5'h0A : max_len = 1024;
5'h0B : max_len = 262144;
5'h1F : max_len = 16;
endcase
for(i=0;i<len;i++) begin
if(start[24:20] == 5'b01) begin
addr = (start[7 :0] + (i[7 :0]<<2)) % (max_len) + {{start[19: 8]}, 8'b0};
end
else begin
addr = (start[19:0] + (i[19:0]<<2)) % (max_len) ;
end
$display("start:%h\taddr:%h",start,addr);
if(spi_pkg.cmd) begin
//$display("rd_data:%h",single_read(spi_pkg.addr + 4*i));
spi_pkg.data[i] = single_read(start, addr);
end
else begin
single_write(start, addr, spi_pkg.data[i]);
end
end
endfunction
function bit[31:0] single_read(bit[24: 0] start, bit[19: 0] addr);
bit[31:0] s_data;//,temp;
//$display("spi read the addr:%h",addr);
//$display(reg_mems::match_filter.data[int'(addr[19: 0]) +: 4]);
//temp={<<byte {reg_mems::match_filter.data[int'(addr[19: 0]) +: 4]}};
//$display("temp=%h",temp);
case(start[24:20])
5'h00 : s_data = reg_mems::sys_regfile.data[int'(addr[19: 2])];
5'h01 : s_data = (start[9:8]==2'b01) ? reg_mems::dac_regfile.data[int'(addr[7:2])] :
(start[9:8]==2'b10) ? reg_mems::adc_regfile.data[int'(addr[7:2])] :
(start[9:8]==2'b11) ? reg_mems::pll_regfile.data[int'(addr[7:2])] :
32'b0;
5'h02 : s_data = {<<byte {reg_mems::daq_inst_ram.data[int'(addr[19: 0]) +: 4]}};
5'h03 : s_data = {<<byte {reg_mems::daq_data_ram.data[int'(addr[19: 0]) +: 4]}};
5'h04 : s_data = reg_mems::daq_regfile.data[int'(addr[19: 2])];
5'h05 : s_data = {<<byte {reg_mems::match_filter.data[int'(addr[19: 0]) +: 4]}};
5'h06 : s_data = {<<byte {reg_mems::read_out_ram.data[int'(addr[19: 0]) +: 4]}};
5'h07 : s_data = {<<byte {reg_mems::awg_inst_ram.data[int'(addr[19: 0]) +: 4]}};
5'h08 : s_data = {<<byte {reg_mems::awg_data_ram.data[int'(addr[19: 0]) +: 4]}};
5'h09 : s_data = reg_mems::awg_regfile.data[int'(addr[19: 2])];
5'h0A : s_data = {<<byte {reg_mems::env_indx_ram.data[int'(addr[19: 0]) +: 4]}};
5'h0B : s_data = {<<byte {reg_mems::env_data_ram.data[int'(addr[19: 0]) +: 4]}};
5'h1F : s_data = reg_mems::clk_regfile.data[int'(addr[19: 2])];
endcase
//$display("s_data=%h",s_data);
return s_data;
endfunction
function single_write(bit[24: 0] start, bit[19: 0] addr, bit[31: 0] s_data);
//$display("single_write: addr=%h, s_data=%h",addr,s_data);
case(start[24:20])
5'h00 : reg_mems::sys_regfile.data[int'(addr[19: 2])] = s_data;
5'h01 : case(start[9:8])
2'b01 : reg_mems::dac_regfile.data[int'(addr[7:2])] = s_data;
2'b10 : reg_mems::adc_regfile.data[int'(addr[7:2])] = s_data;
2'b11 : reg_mems::pll_regfile.data[int'(addr[7:2])] = s_data;
endcase
5'h02 : begin
reg_mems::daq_inst_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
reg_mems::daq_inst_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
reg_mems::daq_inst_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
reg_mems::daq_inst_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
end
5'h03 : begin
reg_mems::daq_data_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
reg_mems::daq_data_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
reg_mems::daq_data_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
reg_mems::daq_data_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
end
5'h04 : reg_mems::daq_regfile.data[int'(addr[19: 2])] = s_data;
5'h05 : begin
reg_mems::match_filter.data[int'(addr[19: 0])+3] = s_data[31:24];
reg_mems::match_filter.data[int'(addr[19: 0])+2] = s_data[23:16];
reg_mems::match_filter.data[int'(addr[19: 0])+1] = s_data[15: 8];
reg_mems::match_filter.data[int'(addr[19: 0])+0] = s_data[7 : 0];
end
5'h06 : begin
reg_mems::read_out_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
reg_mems::read_out_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
reg_mems::read_out_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
reg_mems::read_out_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
end
5'h07 : begin
reg_mems::awg_inst_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
reg_mems::awg_inst_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
reg_mems::awg_inst_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
reg_mems::awg_inst_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
end
5'h08 : begin
reg_mems::awg_data_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
reg_mems::awg_data_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
reg_mems::awg_data_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
reg_mems::awg_data_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
end
5'h09 : reg_mems::awg_regfile.data[int'(addr[19: 2])] = s_data;
5'h0A : begin
reg_mems::env_indx_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
reg_mems::env_indx_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
reg_mems::env_indx_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
reg_mems::env_indx_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
end
5'h0B : begin
reg_mems::env_data_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
reg_mems::env_data_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
reg_mems::env_data_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
reg_mems::env_data_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
end
5'h1F : reg_mems::clk_regfile.data[int'(addr[19: 2])] = s_data;
endcase
endfunction
function new();
endfunction
endclass