修改了部分语法错误
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@ -20,11 +20,14 @@ class readout_daq_rm extends uvm_component;
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virtual rm_if rm_if; //sync
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uvm_blocking_get_port #(EZQ_readout_adc_item) adc_get_port; //get adc wave
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uvm_blocking_get_port #(mcu_cw_item) mcu_get_port; //从mcu获取带时间戳的包，包含cw，time
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uvm_blocking_get_port #(mcu_cw_item) mcu_get_port; //从mcu获取带时间戳的包，包含cw，time
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extern function new(string name,uvm_component parent);
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extern function void build_phase(uvm_phase phase);
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extern virtual task run_phase(uvm_phase phase);
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extern task get_mcu_cw_item();
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extern task get_adc_item();
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extern task daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref int clock_cycle);
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extern task daq_block(
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ref logic [31:0]i,
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ref logic [31:0]cw_data ,
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@ -51,7 +54,7 @@ class readout_daq_rm extends uvm_component;
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extern task dds(
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ref logic [9 :0] address,
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ref logic [7 :0] dds_cos[NUM_WAY-1:0],
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ref logic [7 :0] dds_sin[NUM_WAY-1:0],
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ref logic [7 :0] dds_sin[NUM_WAY-1:0]
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);
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extern task data2sram(
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@ -63,9 +66,12 @@ class readout_daq_rm extends uvm_component;
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ref logic [31:0] i_sum [15:0],
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ref logic [31:0] q_sum [15:0]
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);
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static int NUM_WAY = 8;
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static int NUM_QUBIT = 16;
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bit int clock_cycle ;
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bit [31:0] cw_data ;
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logic [63:0] adc_wave ;
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static logic NUM_WAY = 8;
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static logic NUM_QUBIT = 16;
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endclass
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function readout_daq_rm::new(string name,uvm_component parent);
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@ -81,11 +87,36 @@ function void readout_daq_rm::build_phase(uvm_phase phase);
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adc_get_port = new("adc_get_port",this);
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endfunction
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task readout_daq_rm::get_adc_item();
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EZQ_readout_adc_item EZQ_readout_adc_item;
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forever begin
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adc_get_port.get(EZQ_readout_adc_item);
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adc_wave = EZQ_readout_adc_item.adc_wave;
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`uvm_info(get_type_name(),$sformatf("mcu_cw_data = %0h",EZQ_readout_adc_item.adc_wave),UVM_LOW)
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end
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endtask
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task readout_daq_rm::get_mcu_cw_item();
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mcu_cw_item mcu_cw_item;
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forever begin
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mcu_get_port.get(mcu_cw_item);
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clock_cycle = mcu_cw_item.clock_cycle;
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cw_data = mcu_cw_item.cw_data;
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`uvm_info(get_type_name(),$sformatf("mcu_cw_data = %0h,mcu_cycle = %0h",mcu_cw_item.cw_data,mcu_cw_item.clock_cycle),UVM_LOW)
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end
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endtask
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task readout_daq_rm::run_phase(uvm_phase phase);//main task
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//cw
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logic clk;
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logic [31:0] clock_cycle;//width?
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logic [31:0] cw_data;
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fork
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task get_mcu_cw_item();
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task get_adc_item();
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task daq_exe(cw_data,clock_cycle,adc_wave);
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join
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endtask
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task readout_daq_rm::daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref int clock_cycle);
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logic sync;
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//DAQ reg
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logic [31:0] mcu_timer;
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@ -99,33 +130,33 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task
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logic [31:0] command;
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logic [31:0] func_ctrl;
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logic [31:0] sample_depth;
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logic [31:0] int_threshold,
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logic [31:0] qubit_state,
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logic [31:0] read_req_ctrl,
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logic [31:0] int_threshold;
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logic [31:0] qubit_state;
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logic [31:0] read_req_ctrl;
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logic [31:0] demod_width [15:0];
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logic [31:0] demod_freq [15:0];
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logic [31:0] count_state_0 [15:0],
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logic [31:0] count_state_1 [15:0],
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logic [31:0] count_state_2 [15:0],
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logic [31:0] count_state_3 [15:0],
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logic [31:0] i_sum [15:0],
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logic [31:0] q_sum [15:0],
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logic [31:0] para_ab0 [15:0],
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logic [31:0] para_ab1 [15:0],
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logic [31:0] para_ab2 [15:0],
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logic [31:0] para_c0 [15:0],
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logic [31:0] para_c1 [15:0],
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logic [31:0] para_c2 [15:0],
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logic [31:0] count_state_0 [15:0];
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logic [31:0] count_state_1 [15:0];
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logic [31:0] count_state_2 [15:0];
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logic [31:0] count_state_3 [15:0];
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logic [31:0] i_sum [15:0];
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logic [31:0] q_sum [15:0];
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logic [31:0] para_ab0 [15:0];
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logic [31:0] para_ab1 [15:0];
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logic [31:0] para_ab2 [15:0];
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logic [31:0] para_c0 [15:0];
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logic [31:0] para_c1 [15:0];
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logic [31:0] para_c2 [15:0];
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// sync signal
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wait (`SYNC_IN);
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`uvm_info(get_type_name(),"wait sync_in",UVM_LOW)
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sync = rm_if.sync;
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//MCU packet : get cw_data & cycle
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mcu_get_port.get(mcu_cw_item);
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clock_cycle = mcu_cw_item.clock_cycle;
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cw_data = mcu_cw_item.cw_data;
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//mcu_get_port.get(mcu_cw_item);
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//clock_cycle = mcu_cw_item.clock_cycle;
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//cw_data = mcu_cw_item.cw_data;
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//get DAQ reg
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mcu_timer = reg_mems::daq_regfile.get("timer");
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@ -283,7 +314,7 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task
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////////////////////////////////////////////////////////////////////
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for(i = 0; i < NUM_QUBIT; i++)begin
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fork
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task daq_block(
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daq_block(
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//in
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.i (i ),
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.cw_data (cw_data ),
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@ -306,24 +337,25 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task
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.count_state_0 (count_state_0[i]),
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.count_state_1 (count_state_1[i]),
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.count_state_2 (count_state_2[i]),
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.count_state_3 (count_state_3[i]),
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.count_state_3 (count_state_3[i]),
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);
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join
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qubit_state[i*2+: 2] = state_data[i];
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end
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task data2sram(
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.qubit_total (qubit_total ),
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.count_state_0 (count_state_0 ),
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.count_state_1 (count_state_1 ),
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.count_state_2 (count_state_2 ),
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.count_state_3 (count_state_3 ),
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.i_sum (i_sum ),
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.q_sum (q_sum )
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);
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data2sram(
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.qubit_state (qubit_state ),
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.count_state_0 (count_state_0 ),
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.count_state_1 (count_state_1 ),
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.count_state_2 (count_state_2 ),
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.count_state_3 (count_state_3 ),
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.i_sum (i_sum ),
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.q_sum (q_sum )
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);
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endtask
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task readout_daq_rm::daq_block(
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logic [31:0]i ,
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logic [31:0]cw_data ,
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@ -450,7 +482,7 @@ task readout_daq_rm::daq_block(
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end
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//demod_algorithm
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adc_wave = EZQ_readout_adc_item.adc_wave;
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//adc_wave = EZQ_readout_adc_item.adc_wave;
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for(j = 0; j < NUM_WAY; j++)begin
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demod_i[j][k] = adc_wave[j*8:j*8+7]*mtf_i[j][k];
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demod_q[j][k] = adc_wave[j*8:j*8+7]*mtf_q[j][k];
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