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修改了部分语法错误

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zhangyz 2025-03-19 16:39:54 +08:00
parent e25000939a
commit afae1bd680
1 changed files with 72 additions and 40 deletions
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readout_daq_rm.sv
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@ -20,11 +20,14 @@ class readout_daq_rm extends uvm_component;
virtual rm_if rm_if; //sync virtual rm_if rm_if; //sync
uvm_blocking_get_port #(EZQ_readout_adc_item) adc_get_port; //get adc wave uvm_blocking_get_port #(EZQ_readout_adc_item) adc_get_port; //get adc wave
uvm_blocking_get_port #(mcu_cw_item) mcu_get_port; //从mcu获取带时间戳的包，包含cw，time uvm_blocking_get_port #(mcu_cw_item) mcu_get_port; //从mcu获取带时间戳的包，包含cw，time
extern function new(string name,uvm_component parent); extern function new(string name,uvm_component parent);
extern function void build_phase(uvm_phase phase); extern function void build_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase); extern virtual task run_phase(uvm_phase phase);
extern task get_mcu_cw_item();
extern task get_adc_item();
extern task daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref int clock_cycle);
extern task daq_block( extern task daq_block(
ref logic [31:0]i, ref logic [31:0]i,
ref logic [31:0]cw_data , ref logic [31:0]cw_data ,
@ -51,7 +54,7 @@ class readout_daq_rm extends uvm_component;
extern task dds( extern task dds(
ref logic [9 :0] address, ref logic [9 :0] address,
ref logic [7 :0] dds_cos[NUM_WAY-1:0], ref logic [7 :0] dds_cos[NUM_WAY-1:0],
ref logic [7 :0] dds_sin[NUM_WAY-1:0], ref logic [7 :0] dds_sin[NUM_WAY-1:0]
); );
extern task data2sram( extern task data2sram(
@ -63,9 +66,12 @@ class readout_daq_rm extends uvm_component;
ref logic [31:0] i_sum [15:0], ref logic [31:0] i_sum [15:0],
ref logic [31:0] q_sum [15:0] ref logic [31:0] q_sum [15:0]
); );
static int NUM_WAY = 8;
static int NUM_QUBIT = 16;
bit int clock_cycle ;
bit [31:0] cw_data ;
logic [63:0] adc_wave ;
static logic NUM_WAY = 8;
static logic NUM_QUBIT = 16;
endclass endclass
function readout_daq_rm::new(string name,uvm_component parent); function readout_daq_rm::new(string name,uvm_component parent);
@ -81,11 +87,36 @@ function void readout_daq_rm::build_phase(uvm_phase phase);
adc_get_port = new("adc_get_port",this); adc_get_port = new("adc_get_port",this);
endfunction endfunction
task readout_daq_rm::get_adc_item();
EZQ_readout_adc_item EZQ_readout_adc_item;
forever begin
adc_get_port.get(EZQ_readout_adc_item);
adc_wave = EZQ_readout_adc_item.adc_wave;
`uvm_info(get_type_name(),$sformatf("mcu_cw_data = %0h",EZQ_readout_adc_item.adc_wave),UVM_LOW)
end
endtask
task readout_daq_rm::get_mcu_cw_item();
mcu_cw_item mcu_cw_item;
forever begin
mcu_get_port.get(mcu_cw_item);
clock_cycle = mcu_cw_item.clock_cycle;
cw_data = mcu_cw_item.cw_data;
`uvm_info(get_type_name(),$sformatf("mcu_cw_data = %0h,mcu_cycle = %0h",mcu_cw_item.cw_data,mcu_cw_item.clock_cycle),UVM_LOW)
end
endtask
task readout_daq_rm::run_phase(uvm_phase phase);//main task task readout_daq_rm::run_phase(uvm_phase phase);//main task
//cw fork
logic clk; task get_mcu_cw_item();
logic [31:0] clock_cycle;//width? task get_adc_item();
logic [31:0] cw_data; task daq_exe(cw_data,clock_cycle,adc_wave);
join
endtask
task readout_daq_rm::daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref int clock_cycle);
logic sync; logic sync;
//DAQ reg //DAQ reg
logic [31:0] mcu_timer; logic [31:0] mcu_timer;
@ -99,33 +130,33 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task
logic [31:0] command; logic [31:0] command;
logic [31:0] func_ctrl; logic [31:0] func_ctrl;
logic [31:0] sample_depth; logic [31:0] sample_depth;
logic [31:0] int_threshold, logic [31:0] int_threshold;
logic [31:0] qubit_state, logic [31:0] qubit_state;
logic [31:0] read_req_ctrl, logic [31:0] read_req_ctrl;
logic [31:0] demod_width [15:0]; logic [31:0] demod_width [15:0];
logic [31:0] demod_freq [15:0]; logic [31:0] demod_freq [15:0];
logic [31:0] count_state_0 [15:0], logic [31:0] count_state_0 [15:0];
logic [31:0] count_state_1 [15:0], logic [31:0] count_state_1 [15:0];
logic [31:0] count_state_2 [15:0], logic [31:0] count_state_2 [15:0];
logic [31:0] count_state_3 [15:0], logic [31:0] count_state_3 [15:0];
logic [31:0] i_sum [15:0], logic [31:0] i_sum [15:0];
logic [31:0] q_sum [15:0], logic [31:0] q_sum [15:0];
logic [31:0] para_ab0 [15:0], logic [31:0] para_ab0 [15:0];
logic [31:0] para_ab1 [15:0], logic [31:0] para_ab1 [15:0];
logic [31:0] para_ab2 [15:0], logic [31:0] para_ab2 [15:0];
logic [31:0] para_c0 [15:0], logic [31:0] para_c0 [15:0];
logic [31:0] para_c1 [15:0], logic [31:0] para_c1 [15:0];
logic [31:0] para_c2 [15:0], logic [31:0] para_c2 [15:0];
// sync signal // sync signal
wait (`SYNC_IN); wait (`SYNC_IN);
`uvm_info(get_type_name(),"wait sync_in",UVM_LOW) `uvm_info(get_type_name(),"wait sync_in",UVM_LOW)
sync = rm_if.sync; sync = rm_if.sync;
//MCU packet : get cw_data & cycle //MCU packet : get cw_data & cycle
mcu_get_port.get(mcu_cw_item); //mcu_get_port.get(mcu_cw_item);
clock_cycle = mcu_cw_item.clock_cycle; //clock_cycle = mcu_cw_item.clock_cycle;
cw_data = mcu_cw_item.cw_data; //cw_data = mcu_cw_item.cw_data;
//get DAQ reg //get DAQ reg
mcu_timer = reg_mems::daq_regfile.get("timer"); mcu_timer = reg_mems::daq_regfile.get("timer");
@ -283,7 +314,7 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task
//////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////
for(i = 0; i < NUM_QUBIT; i++)begin for(i = 0; i < NUM_QUBIT; i++)begin
fork fork
task daq_block( daq_block(
//in //in
.i (i ), .i (i ),
.cw_data (cw_data ), .cw_data (cw_data ),
@ -306,24 +337,25 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task
.count_state_0 (count_state_0[i]), .count_state_0 (count_state_0[i]),
.count_state_1 (count_state_1[i]), .count_state_1 (count_state_1[i]),
.count_state_2 (count_state_2[i]), .count_state_2 (count_state_2[i]),
.count_state_3 (count_state_3[i]), .count_state_3 (count_state_3[i]),
);
join join
qubit_state[i*2+: 2] = state_data[i]; qubit_state[i*2+: 2] = state_data[i];
end end
task data2sram( data2sram(
.qubit_total (qubit_total ), .qubit_state (qubit_state ),
.count_state_0 (count_state_0 ), .count_state_0 (count_state_0 ),
.count_state_1 (count_state_1 ), .count_state_1 (count_state_1 ),
.count_state_2 (count_state_2 ), .count_state_2 (count_state_2 ),
.count_state_3 (count_state_3 ), .count_state_3 (count_state_3 ),
.i_sum (i_sum ), .i_sum (i_sum ),
.q_sum (q_sum ) .q_sum (q_sum )
); );
endtask endtask
task readout_daq_rm::daq_block( task readout_daq_rm::daq_block(
logic [31:0]i , logic [31:0]i ,
logic [31:0]cw_data , logic [31:0]cw_data ,
@ -450,7 +482,7 @@ task readout_daq_rm::daq_block(
end end
//demod_algorithm //demod_algorithm
adc_wave = EZQ_readout_adc_item.adc_wave; //adc_wave = EZQ_readout_adc_item.adc_wave;
for(j = 0; j < NUM_WAY; j++)begin for(j = 0; j < NUM_WAY; j++)begin
demod_i[j][k] = adc_wave[j*8:j*8+7]*mtf_i[j][k]; demod_i[j][k] = adc_wave[j*8:j*8+7]*mtf_i[j][k];
demod_q[j][k] = adc_wave[j*8:j*8+7]*mtf_q[j][k]; demod_q[j][k] = adc_wave[j*8:j*8+7]*mtf_q[j][k];