From afae1bd680ddfb61e858c5bfc79d66ca6eb2137f Mon Sep 17 00:00:00 2001 From: zhangyz Date: Wed, 19 Mar 2025 16:39:54 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E4=BA=86=E9=83=A8=E5=88=86?= =?UTF-8?q?=E8=AF=AD=E6=B3=95=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- readout_daq_rm.sv | 112 +++++++++++++++++++++++++++++----------------- 1 file changed, 72 insertions(+), 40 deletions(-) diff --git a/readout_daq_rm.sv b/readout_daq_rm.sv index 82826b6..76f1d92 100644 --- a/readout_daq_rm.sv +++ b/readout_daq_rm.sv @@ -20,11 +20,14 @@ class readout_daq_rm extends uvm_component; virtual rm_if rm_if; //sync uvm_blocking_get_port #(EZQ_readout_adc_item) adc_get_port; //get adc wave - uvm_blocking_get_port #(mcu_cw_item) mcu_get_port; //从mcu获取带时间戳的包，包含cw，time + uvm_blocking_get_port #(mcu_cw_item) mcu_get_port; //从mcu获取带时间戳的包，包含cw，time extern function new(string name,uvm_component parent); extern function void build_phase(uvm_phase phase); extern virtual task run_phase(uvm_phase phase); + extern task get_mcu_cw_item(); + extern task get_adc_item(); + extern task daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref int clock_cycle); extern task daq_block( ref logic [31:0]i, ref logic [31:0]cw_data , @@ -51,7 +54,7 @@ class readout_daq_rm extends uvm_component; extern task dds( ref logic [9 :0] address, ref logic [7 :0] dds_cos[NUM_WAY-1:0], - ref logic [7 :0] dds_sin[NUM_WAY-1:0], + ref logic [7 :0] dds_sin[NUM_WAY-1:0] ); extern task data2sram( @@ -63,9 +66,12 @@ class readout_daq_rm extends uvm_component; ref logic [31:0] i_sum [15:0], ref logic [31:0] q_sum [15:0] ); + static int NUM_WAY = 8; + static int NUM_QUBIT = 16; + bit int clock_cycle ; + bit [31:0] cw_data ; + logic [63:0] adc_wave ; - static logic NUM_WAY = 8; - static logic NUM_QUBIT = 16; endclass function readout_daq_rm::new(string name,uvm_component parent); @@ -81,11 +87,36 @@ function void readout_daq_rm::build_phase(uvm_phase phase); adc_get_port = new("adc_get_port",this); endfunction +task readout_daq_rm::get_adc_item(); + EZQ_readout_adc_item EZQ_readout_adc_item; + forever begin + adc_get_port.get(EZQ_readout_adc_item); + adc_wave = EZQ_readout_adc_item.adc_wave; + `uvm_info(get_type_name(),$sformatf("mcu_cw_data = %0h",EZQ_readout_adc_item.adc_wave),UVM_LOW) + end +endtask + +task readout_daq_rm::get_mcu_cw_item(); + mcu_cw_item mcu_cw_item; + forever begin + mcu_get_port.get(mcu_cw_item); + clock_cycle = mcu_cw_item.clock_cycle; + cw_data = mcu_cw_item.cw_data; + `uvm_info(get_type_name(),$sformatf("mcu_cw_data = %0h,mcu_cycle = %0h",mcu_cw_item.cw_data,mcu_cw_item.clock_cycle),UVM_LOW) + end +endtask + task readout_daq_rm::run_phase(uvm_phase phase);//main task -//cw - logic clk; - logic [31:0] clock_cycle;//width? - logic [31:0] cw_data; + fork + task get_mcu_cw_item(); + task get_adc_item(); + task daq_exe(cw_data,clock_cycle,adc_wave); + join + +endtask + + +task readout_daq_rm::daq_exe(ref bit[31:0]cw_data, ref logic[63:0]adc_wave, ref int clock_cycle); logic sync; //DAQ reg logic [31:0] mcu_timer; @@ -99,33 +130,33 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task logic [31:0] command; logic [31:0] func_ctrl; logic [31:0] sample_depth; - logic [31:0] int_threshold, - logic [31:0] qubit_state, - logic [31:0] read_req_ctrl, + logic [31:0] int_threshold; + logic [31:0] qubit_state; + logic [31:0] read_req_ctrl; logic [31:0] demod_width [15:0]; logic [31:0] demod_freq [15:0]; - logic [31:0] count_state_0 [15:0], - logic [31:0] count_state_1 [15:0], - logic [31:0] count_state_2 [15:0], - logic [31:0] count_state_3 [15:0], - logic [31:0] i_sum [15:0], - logic [31:0] q_sum [15:0], - logic [31:0] para_ab0 [15:0], - logic [31:0] para_ab1 [15:0], - logic [31:0] para_ab2 [15:0], - logic [31:0] para_c0 [15:0], - logic [31:0] para_c1 [15:0], - logic [31:0] para_c2 [15:0], + logic [31:0] count_state_0 [15:0]; + logic [31:0] count_state_1 [15:0]; + logic [31:0] count_state_2 [15:0]; + logic [31:0] count_state_3 [15:0]; + logic [31:0] i_sum [15:0]; + logic [31:0] q_sum [15:0]; + logic [31:0] para_ab0 [15:0]; + logic [31:0] para_ab1 [15:0]; + logic [31:0] para_ab2 [15:0]; + logic [31:0] para_c0 [15:0]; + logic [31:0] para_c1 [15:0]; + logic [31:0] para_c2 [15:0]; // sync signal wait (`SYNC_IN); `uvm_info(get_type_name(),"wait sync_in",UVM_LOW) sync = rm_if.sync; //MCU packet : get cw_data & cycle - mcu_get_port.get(mcu_cw_item); - clock_cycle = mcu_cw_item.clock_cycle; - cw_data = mcu_cw_item.cw_data; + //mcu_get_port.get(mcu_cw_item); + //clock_cycle = mcu_cw_item.clock_cycle; + //cw_data = mcu_cw_item.cw_data; //get DAQ reg mcu_timer = reg_mems::daq_regfile.get("timer"); @@ -283,7 +314,7 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task //////////////////////////////////////////////////////////////////// for(i = 0; i < NUM_QUBIT; i++)begin fork - task daq_block( + daq_block( //in .i (i ), .cw_data (cw_data ), @@ -306,24 +337,25 @@ task readout_daq_rm::run_phase(uvm_phase phase);//main task .count_state_0 (count_state_0[i]), .count_state_1 (count_state_1[i]), .count_state_2 (count_state_2[i]), - .count_state_3 (count_state_3[i]), + .count_state_3 (count_state_3[i]), + ); join qubit_state[i*2+: 2] = state_data[i]; end - task data2sram( - .qubit_total (qubit_total ), - .count_state_0 (count_state_0 ), - .count_state_1 (count_state_1 ), - .count_state_2 (count_state_2 ), - .count_state_3 (count_state_3 ), - .i_sum (i_sum ), - .q_sum (q_sum ) - ); + data2sram( + .qubit_state (qubit_state ), + .count_state_0 (count_state_0 ), + .count_state_1 (count_state_1 ), + .count_state_2 (count_state_2 ), + .count_state_3 (count_state_3 ), + .i_sum (i_sum ), + .q_sum (q_sum ) + ); + + endtask - - task readout_daq_rm::daq_block( logic [31:0]i , logic [31:0]cw_data , @@ -450,7 +482,7 @@ task readout_daq_rm::daq_block( end //demod_algorithm - adc_wave = EZQ_readout_adc_item.adc_wave; + //adc_wave = EZQ_readout_adc_item.adc_wave; for(j = 0; j < NUM_WAY; j++)begin demod_i[j][k] = adc_wave[j*8:j*8+7]*mtf_i[j][k]; demod_q[j][k] = adc_wave[j*8:j*8+7]*mtf_q[j][k];