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mcu_cw_item.sv

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+// ======================================== //
+// CopyRight(C) 2024 HFNL-CMOS
+// ALL RIGHTS RESERVED.
+// FileName : mcu_cw_item.sv
+// Author   : WuJin
+// Email    : wujin@hfnl.cn
+// Created  : 2024-12-30
+// History  : v1.0
+// ======================================= //
+`ifndef _MCU_ITEM_
+`define _MCU_ITEM_
+
+class mcu_cw_item extends uvm_sequence_item;
+    rand bit [63:0] clock_cycle;
+    rand bit [31:0] cw_data;
+    rand bit        wr_ram;
+    rand bit [31:0] wr_ram_addr;
+    rand bit [31:0] wr_ram_data;
+    rand bit [3:0]  wr_ram_mask;
+    rand bit        wr_reg;
+    rand bit [4:0]  wr_reg_addr;
+    rand bit [31:0] wr_reg_data;
+
+
+
+  function new(string name = "");
+    super.new(name);
+  endfunction : new
+
+  function void post_randomize();
+
+  	//ToDo
+
+  endfunction : post_randomize
+
+
+   `uvm_object_utils_begin(mcu_cw_item)
+       `uvm_field_int(clock_cycle,UVM_ALL_ON)
+       `uvm_field_int(cw_data,UVM_ALL_ON)
+       `uvm_field_int(wr_ram,UVM_ALL_ON)
+       `uvm_field_int(wr_ram_addr,UVM_ALL_ON)
+       `uvm_field_int(wr_ram_data,UVM_ALL_ON)
+       `uvm_field_int(wr_ram_mask,UVM_ALL_ON)
+       `uvm_field_int(wr_reg,UVM_ALL_ON)
+       `uvm_field_int(wr_reg_addr,UVM_ALL_ON)
+       `uvm_field_int(wr_reg_data,UVM_ALL_ON)
+
+   `uvm_object_utils_end
+
+
+
+   function void do_pack(uvm_packer packer);
+	super.do_pack(packer);
+   endfunction : do_pack
+
+   //do_unpack
+   function void do_unpack(uvm_packer packer);
+	super.do_unpack(packer);
+   endfunction : do_unpack
+
+
+endclass
+
+`endif