143 lines
5.8 KiB
Systemverilog
143 lines
5.8 KiB
Systemverilog
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//given a spi_item, and read or write reg_mems.
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class spi_rw;
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function rw(ref spi_item spi_pkg);
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int len = spi_pkg.data.size();
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int max_len = 0;
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bit [24:0] start;
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bit [19:0] addr ;
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int i = 0;
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start = spi_pkg.addr;
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case(start[24:20])
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5'h00 : max_len = 32;
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5'h01 : max_len = (start[9:8]==2'b01) ? 52 :
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(start[9:8]==2'b10) ? 16 :
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(start[9:8]==2'b11) ? 44 :
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0;
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5'h02 : max_len = 32768;
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5'h03 : max_len = 32768;
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5'h04 : max_len = 1024;
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5'h05 : max_len = 524288;
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5'h06 : max_len = 524288;
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5'h07 : max_len = 32768;
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5'h08 : max_len = 32768;
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5'h09 : max_len = 80;
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5'h0A : max_len = 1024;
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5'h0B : max_len = 262144;
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5'h1F : max_len = 16;
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endcase
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for(i=0;i<len;i++) begin
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if(start[24:20] == 5'b01) begin
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addr = (start[7 :0] + (i[7 :0]<<2)) % (max_len) + {{start[19: 8]}, 8'b0};
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end
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else begin
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addr = (start[19:0] + (i[19:0]<<2)) % (max_len) ;
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end
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$display("start:%h\taddr:%h",start,addr);
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if(spi_pkg.cmd) begin
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//$display("rd_data:%h",single_read(spi_pkg.addr + 4*i));
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spi_pkg.data[i] = single_read(start, addr);
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end
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else begin
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single_write(start, addr, spi_pkg.data[i]);
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end
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end
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endfunction
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function bit[31:0] single_read(bit[24: 0] start, bit[19: 0] addr);
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bit[31:0] s_data;//,temp;
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//$display("spi read the addr:%h",addr);
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//$display(reg_mems::match_filter.data[int'(addr[19: 0]) +: 4]);
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//temp={<<byte {reg_mems::match_filter.data[int'(addr[19: 0]) +: 4]}};
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//$display("temp=%h",temp);
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case(start[24:20])
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5'h00 : s_data = reg_mems::sys_regfile.data[int'(addr[19: 2])];
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5'h01 : s_data = (start[9:8]==2'b01) ? reg_mems::dac_regfile.data[int'(addr[7:2])] :
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(start[9:8]==2'b10) ? reg_mems::adc_regfile.data[int'(addr[7:2])] :
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(start[9:8]==2'b11) ? reg_mems::pll_regfile.data[int'(addr[7:2])] :
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32'b0;
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5'h02 : s_data = {<<byte {reg_mems::daq_inst_ram.data[int'(addr[19: 0]) +: 4]}};
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5'h03 : s_data = {<<byte {reg_mems::daq_data_ram.data[int'(addr[19: 0]) +: 4]}};
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5'h04 : s_data = reg_mems::daq_regfile.data[int'(addr[19: 2])];
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5'h05 : s_data = {<<byte {reg_mems::match_filter.data[int'(addr[19: 0]) +: 4]}};
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5'h06 : s_data = {<<byte {reg_mems::read_out_ram.data[int'(addr[19: 0]) +: 4]}};
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5'h07 : s_data = {<<byte {reg_mems::awg_inst_ram.data[int'(addr[19: 0]) +: 4]}};
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5'h08 : s_data = {<<byte {reg_mems::awg_data_ram.data[int'(addr[19: 0]) +: 4]}};
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5'h09 : s_data = reg_mems::awg_regfile.data[int'(addr[19: 2])];
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5'h0A : s_data = {<<byte {reg_mems::env_indx_ram.data[int'(addr[19: 0]) +: 4]}};
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5'h0B : s_data = {<<byte {reg_mems::env_data_ram.data[int'(addr[19: 0]) +: 4]}};
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5'h1F : s_data = reg_mems::clk_regfile.data[int'(addr[19: 2])];
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endcase
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//$display("s_data=%h",s_data);
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return s_data;
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endfunction
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function single_write(bit[24: 0] start, bit[19: 0] addr, bit[31: 0] s_data);
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//$display("single_write: addr=%h, s_data=%h",addr,s_data);
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case(start[24:20])
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5'h00 : reg_mems::sys_regfile.data[int'(addr[19: 2])] = s_data;
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5'h01 : case(start[9:8])
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2'b01 : reg_mems::dac_regfile.data[int'(addr[7:2])] = s_data;
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2'b10 : reg_mems::adc_regfile.data[int'(addr[7:2])] = s_data;
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2'b11 : reg_mems::pll_regfile.data[int'(addr[7:2])] = s_data;
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endcase
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5'h02 : begin
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reg_mems::daq_inst_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
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reg_mems::daq_inst_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
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reg_mems::daq_inst_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
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reg_mems::daq_inst_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
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end
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5'h03 : begin
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reg_mems::daq_data_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
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reg_mems::daq_data_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
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reg_mems::daq_data_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
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reg_mems::daq_data_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
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end
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5'h04 : reg_mems::daq_regfile.data[int'(addr[19: 2])] = s_data;
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5'h05 : begin
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reg_mems::match_filter.data[int'(addr[19: 0])+3] = s_data[31:24];
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reg_mems::match_filter.data[int'(addr[19: 0])+2] = s_data[23:16];
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reg_mems::match_filter.data[int'(addr[19: 0])+1] = s_data[15: 8];
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reg_mems::match_filter.data[int'(addr[19: 0])+0] = s_data[7 : 0];
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end
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5'h06 : begin
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reg_mems::read_out_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
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reg_mems::read_out_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
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reg_mems::read_out_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
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reg_mems::read_out_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
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end
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5'h07 : begin
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reg_mems::awg_inst_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
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reg_mems::awg_inst_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
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reg_mems::awg_inst_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
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reg_mems::awg_inst_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
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end
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5'h08 : begin
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reg_mems::awg_data_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
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reg_mems::awg_data_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
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reg_mems::awg_data_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
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reg_mems::awg_data_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
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end
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5'h09 : reg_mems::awg_regfile.data[int'(addr[19: 2])] = s_data;
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5'h0A : begin
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reg_mems::env_indx_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
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reg_mems::env_indx_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
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reg_mems::env_indx_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
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reg_mems::env_indx_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
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end
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5'h0B : begin
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reg_mems::env_data_ram.data[int'(addr[19: 0])+3] = s_data[31:24];
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reg_mems::env_data_ram.data[int'(addr[19: 0])+2] = s_data[23:16];
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reg_mems::env_data_ram.data[int'(addr[19: 0])+1] = s_data[15: 8];
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reg_mems::env_data_ram.data[int'(addr[19: 0])+0] = s_data[7 : 0];
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end
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5'h1F : reg_mems::clk_regfile.data[int'(addr[19: 2])] = s_data;
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endcase
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endfunction
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function new();
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endfunction
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endclass
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