155 lines
4.7 KiB
Systemverilog
155 lines
4.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module TB_top();
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// ==========================================
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// 参数与信号定义
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// ==========================================
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parameter CLK_PERIOD = 20; // 50MHz
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parameter BAUD = 115200;
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localparam BIT_TIME = 1_000_000_000 / BAUD;
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reg clk;
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reg rst_n;
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reg uart_rx; // 对应 DUT 的 RX
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wire uart_tx; // 对应 DUT 的 TX
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// 时钟生成
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initial clk = 0;
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always #(CLK_PERIOD/2) clk = ~clk;
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// ==========================================
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// 实例化被测设计 (DUT)
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// ==========================================
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digital_top u_digital_top(
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.clk (clk),
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.rst_n (rst_n),
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.uart_rx (uart_rx),
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.uart_tx (uart_tx)
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);
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// ==========================================
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// 任务：发送一个字节 (Serial TX)
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// ==========================================
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task automatic send_byte(input [7:0] data);
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begin
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uart_rx = 0; // 起始位
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#(BIT_TIME);
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for (int i = 0; i < 8; i++) begin
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uart_rx = data[i]; // LSB First
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#(BIT_TIME);
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end
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uart_rx = 1; // 停止位
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#(BIT_TIME);
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end
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endtask
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// 任务：发送 32/64 位数据
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task automatic send_data(input [63:0] data, input int len_bits);
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int bytes = len_bits / 8;
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for (int i = 0; i < bytes; i++) begin
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// 默认小端发送：低字节在前
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send_byte(data[i*8 +: 8]);
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end
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endtask
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// ==========================================
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// 流程控制：TX 驱动 (从 case.txt 读取)
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// ==========================================
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initial begin
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int file_h;
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int status;
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logic [63:0] val;
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// 初始化信号
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rst_n = 0;
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uart_rx = 1;
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#(CLK_PERIOD * 10);
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rst_n = 1;
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file_h = $fopen("case.txt", "r");
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if (!file_h) begin
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$display("[TX ERROR] Cannot open case.txt");
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$finish;
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end
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$display("[TX] Starting transmission...");
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while (!$feof(file_h)) begin
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// 假设文件中每行是一个 hex 数据
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status = $fscanf(file_h, "%h\n", val);
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if (status == 1) begin
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if (val > 64'hFFFF_FFFF) begin
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$display("[%t] TX CMD: %h", $time, val);
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send_data(val, 64);
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end else begin
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$display("[%t] TX DATA: %h", $time, val[31:0]);
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send_data(val[31:0], 32);
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end
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#(BIT_TIME * 5); // 帧间隙
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end
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end
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$fclose(file_h);
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$display("[TX] All cases sent.");
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// 等待一段时间观察 RX 是否还有回传，然后结束
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#(BIT_TIME * 500);
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$display("[SIM] Simulation finished.");
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$finish;
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end
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// ==========================================
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// 流程控制：RX 监听 (保存到 rx_data.txt)
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// ==========================================
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int rx_file_h;
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initial begin
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logic [7:0] rx_byte;
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rx_file_h = $fopen("rx_data.txt", "w");
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if (!rx_file_h) begin
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$display("[RX ERROR] Cannot create rx_data.txt");
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$finish;
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end
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forever begin
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logic [31:0] packet_word; // 32位数据包
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logic [7:0] rx_byte;
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// 收集4个字节并组合成32位数据
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for (int byte_idx = 0; byte_idx < 4; byte_idx++) begin
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// 1. 等待起始位 (下降沿)
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@(negedge uart_tx);
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// 2. 跳过起始位，采样数据中心点
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#(BIT_TIME / 2);
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#(BIT_TIME);
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// 读取8个数据位
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for (int i = 0; i < 8; i++) begin
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rx_byte[i] = uart_tx;
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#(BIT_TIME);
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end
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// 组合成32位数据（小端序：先收到的在低位）
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packet_word[8*byte_idx +: 8] = rx_byte;
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$display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte);
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// 等待停止位结束
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if (byte_idx < 3) begin
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#(BIT_TIME / 2);
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end
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end
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// 写入文件（一行一个32位数据）
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$fdisplay(rx_file_h, "%08h", packet_word);
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$display("[%t] Packet (32-bit): 0x%08h", $time, packet_word);
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// 等待最后一个字节的停止位结束
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#(BIT_TIME / 2);
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end
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end
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final begin
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if (rx_file_h) begin
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$fclose(rx_file_h);
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$display("[RX] File closed at %t",$time);
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end
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end
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endmodule |