164 lines
5.0 KiB
Verilog
164 lines
5.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: yangshenbo
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//
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// Create Date: 2026/03/31 10:53:24
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// Design Name:
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// Module Name: uart_top_32bit
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//
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//////////////////////////////////////////////////////////////////////////////////
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module uart_top_32bit #(
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parameter BAUD = 9600,
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parameter CLOCK_FREQ = 50_000_000
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)
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(
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input Clk,
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input Reset_n,
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// 32位发送接口
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input Send_Go32, // 32位发送启动脉冲
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input [31:0] Tx_Data32, // 待发送的32位数据
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output Tx_Done32, // 32位发送完成标志
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output uart_tx, // 物理引脚TX
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// 32位接收接口
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input uart_rx, // 物理引脚RX
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output reg Rx_Done32, // 32位接收完成标志
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output reg [31:0] Rx_Data32 // 接收到的32位数据
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);
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// --- 内部连线 ---
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wire byte_tx_go;
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wire [7:0] byte_tx_data;
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wire byte_tx_done;
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wire byte_rx_done;
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wire [7:0] byte_rx_data;
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// ============================================================
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// 1. 发送逻辑控制 (32-bit to 4x8-bit)
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// ============================================================
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reg [3:0] tx_state;
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reg [31:0] tx_data_buffer;
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reg byte_tx_go_reg;
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reg [7:0] byte_tx_data_reg;
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assign byte_tx_go = byte_tx_go_reg;
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assign byte_tx_data = byte_tx_data_reg;
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always @(posedge Clk or negedge Reset_n) begin
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if (!Reset_n) begin
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tx_state <= 0;
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byte_tx_go_reg <= 0;
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tx_data_buffer <= 0;
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end else begin
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case (tx_state)
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0: begin // 等待发送触发
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if (Send_Go32) begin
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tx_data_buffer <= Tx_Data32;
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tx_state <= 1;
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end
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end
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1, 2, 3, 4: begin // 依次发送字节0, 1, 2, 3
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byte_tx_data_reg <= tx_data_buffer[7:0]; // 优先发低位(小端)
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byte_tx_go_reg <= 1;
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tx_state <= tx_state + 4; // 跳转到等待状态 (利用加法偏移)
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end
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// 状态 5, 6, 7, 8 用于等待 byte_tx_done
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5, 6, 7, 8: begin
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byte_tx_go_reg <= 0;
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if (byte_tx_done) begin
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tx_data_buffer <= tx_data_buffer >> 8; // 移位，准备下一字节
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if (tx_state == 8) tx_state <= 0; // 发完4个
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else tx_state <= tx_state - 3; // 回到下一个发送状态
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end
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end
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endcase
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end
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end
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assign Tx_Done32 = (tx_state == 8 && byte_tx_done);
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// ============================================================
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// 2. 接收逻辑控制 (4x8-bit to 32-bit)
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// ============================================================
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reg [1:0] rx_cnt;
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reg [31:0] rx_data_buffer;
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reg rx_done32_reg;
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always @(posedge Clk or negedge Reset_n) begin
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if (!Reset_n) begin
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rx_cnt <= 0;
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rx_data_buffer <= 0;
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rx_done32_reg <= 0;
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end else begin
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rx_done32_reg <= 0;
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if (byte_rx_done) begin
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// 拼接数据 (小端模式)
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case(rx_cnt)
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0: rx_data_buffer[7:0] <= byte_rx_data;
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1: rx_data_buffer[15:8] <= byte_rx_data;
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2: rx_data_buffer[23:16] <= byte_rx_data;
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3: rx_data_buffer[31:24] <= byte_rx_data;
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endcase
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if (rx_cnt == 3) begin
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rx_cnt <= 0;
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rx_done32_reg <= 1;
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end else begin
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rx_cnt <= rx_cnt + 1;
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end
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end
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end
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end
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always @(posedge Clk or Reset_n) begin
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if(!Reset_n) begin
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Rx_Data32 <= 1'b0;
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Rx_Done32 <= 1'b0;
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end
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else if(rx_done32_reg)begin
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Rx_Data32 <= rx_data_buffer;
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Rx_Done32 <= rx_done32_reg;
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end
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else begin
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Rx_Data32 <= Rx_Data32;
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Rx_Done32 <= 0;
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end
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end
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// ============================================================
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// 3. 模块实例化
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// ============================================================
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// 实例化发送字节模块
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uart_byte_tx #(
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.BAUD(BAUD),
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.CLOCK_FREQ(CLOCK_FREQ)
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) u_uart_byte_tx (
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.Clk(Clk),
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.Reset_n(Reset_n),
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.Send_Go(byte_tx_go),
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.Data(byte_tx_data),
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.uart_tx(uart_tx),
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.Tx_Done(byte_tx_done)
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);
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// 实例化接收字节模块
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uart_byte_rx #(
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.BAUD(BAUD),
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.CLOCK_FREQ(CLOCK_FREQ)
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) u_uart_byte_rx (
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.Clk(Clk),
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.Reset_n(Reset_n),
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.uart_rx(uart_rx),
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.Rx_Done(byte_rx_done),
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.Rx_Data(byte_rx_data)
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);
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endmodule
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