64 lines
1.3 KiB
Verilog
64 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/04/03 22:01:15
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// Design Name:
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// Module Name: digital_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module digital_top(
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input clk,
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input rst_n,
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input uart_rx,
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output uart_tx
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);
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wire [31:0] w_wrdata; // DUT -> SRAM 写数据
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wire [24:0] w_addr; // DUT -> SRAM 地址
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wire w_wren; // 写使能
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wire w_rden; // 读使能
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wire [31:0] w_rddata; // SRAM -> DUT 读数据
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// 例化待测模块 (DUT)
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uart_ctrl_sysreg #(
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.BAUD (115200),
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.CLOCK_FREQ (50_000_000)
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) u_uart_ctrl (
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.clk (clk),
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.rst_n (rst_n),
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.uart_rx (uart_rx),
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.uart_tx (uart_tx),
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.o_wrdata (w_wrdata),
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.o_addr (w_addr),
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.o_wren (w_wren),
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.o_rden (w_rden),
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.i_rddata (w_rddata)
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);
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system_regfile u_system_regfile (
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.clk (clk),
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.rst_n (rst_n),
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.wrdata (w_wrdata),
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.wren (w_wren),
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.rwaddr (w_addr),
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.rden (w_rden),
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.rddata (w_rddata)
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);
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endmodule
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