23 lines
969 B
Plaintext
23 lines
969 B
Plaintext
Command: vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k -debug_access+pp -lca -q -timescale=1ns/1ps \
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+nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb \
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-f filelist_vlg.f
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Warning-[LCA_FEATURES_ENABLED] Usage warning
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LCA features enabled by '-lca' argument on the command line. For more
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information regarding list of LCA features please refer to Chapter "LCA
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features" in the VCS/VCS-MX Release Notes
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VCS Coverage Metrics Release O-2018.09-SP2_Full64 Copyright (c) 1991-2018 by Synopsys Inc.
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Note-[VCS_PARAL] Parallel code-gen enabled
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VCS is running with parallel code generation(-j)...
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6 modules and 0 UDP read.
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make[1]: Entering directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \
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ld -shared -Bsymbolic -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o
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rm -f _csrc0.so
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../simv up to date
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make[1]: Leaving directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \
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