90 lines
2.5 KiB
Verilog
90 lines
2.5 KiB
Verilog
`timescale 1ns / 1ps
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module uart_byte_rx_tb();
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reg Clk;
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reg Reset_n;
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reg uart_rx;
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wire Rx_Done;
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wire [7:0]Rx_Data;
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uart_byte_rx uart_byte_rx(
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.Clk(Clk),
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.Reset_n(Reset_n),
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.uart_rx(uart_rx),
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.Rx_Done(Rx_Done),
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.Rx_Data(Rx_Data)
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);
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initial Clk = 1;
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always #10 Clk= ~Clk;
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initial begin
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Reset_n = 0;
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uart_rx = 1;
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#201;
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Reset_n = 1;
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#200;
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//8'b0101_0101
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uart_rx = 0; #(5208*20); //Æðʼλ
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uart_rx = 1; #(5208*20); //bit0
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uart_rx = 0; #(5208*20); //bit1
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uart_rx = 1; #(5208*20); //bit2
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uart_rx = 0; #(5208*20); //bit3
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uart_rx = 1; #(5208*20); //bit4
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uart_rx = 0; #(5208*20); //bit5
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uart_rx = 1; #(5208*20); //bit6
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uart_rx = 0; #(5208*20); //bit7
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uart_rx = 1; #(5208*20); //ֹͣλ
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#(5208*20*10);
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//8'b1010_1010
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uart_rx = 0; #(5208*20); //Æðʼλ
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uart_rx = 0; #(5208*20); //bit0
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uart_rx = 1; #(5208*20); //bit1
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uart_rx = 0; #(5208*20); //bit2
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uart_rx = 1; #(5208*20); //bit3
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uart_rx = 0; #(5208*20); //bit4
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uart_rx = 1; #(5208*20); //bit5
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uart_rx = 0; #(5208*20); //bit6
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uart_rx = 1; #(5208*20); //bit7
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uart_rx = 1; #(5208*20); //ֹͣλ
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#(5208*20*10);
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//8'b1111_0000
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uart_rx = 0; #(5208*20); //Æðʼλ
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uart_rx = 0; #(5208*20); //bit0
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uart_rx = 0; #(5208*20); //bit1
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uart_rx = 0; #(5208*20); //bit2
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uart_rx = 0; #(5208*20); //bit3
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uart_rx = 1; #(5208*20); //bit4
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uart_rx = 1; #(5208*20); //bit5
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uart_rx = 1; #(5208*20); //bit6
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uart_rx = 1; #(5208*20); //bit7
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uart_rx = 1; #(5208*20); //ֹͣλ
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#(5208*20*10);
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//8'b0000_1111
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uart_rx = 0; #(5208*20); //Æðʼλ
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uart_rx = 1; #(5208*20); //bit0
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uart_rx = 1; #(5208*20); //bit1
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uart_rx = 1; #(5208*20); //bit2
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uart_rx = 1; #(5208*20); //bit3
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uart_rx = 0; #(5208*20); //bit4
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uart_rx = 0; #(5208*20); //bit5
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uart_rx = 0; #(5208*20); //bit6
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uart_rx = 0; #(5208*20); //bit7
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uart_rx = 1; #(5208*20); //ֹͣλ
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#(5208*20*10);
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$stop;
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end
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endmodule
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