79 lines
2.1 KiB
Verilog
79 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Yangshenbo
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// version:V1.0
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// Create Date: 2026/03/22
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//////////////////////////////////////////////////////////////////////////////////
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module digital_thermometer(
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input clk,
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input rst_n,
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input vin,
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input mode,
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output reg [19:0]freq_x100hz,
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output reg [15:0]temp_out,
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output reg temp_valid
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);
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wire [19:0] freq;
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wire freq_valid;
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//映射表：
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reg [15:0] temp_lut [0:800];
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integer i;
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initial begin
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for (i = 0; i <= 800; i = i + 1) begin
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// 50.0kHz->-40°C, 130.0kHz->85°C
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// temp = -400 + (1250 * i) / 800
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temp_lut[i] = -400 + (1250 * i + 400) / 800;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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freq_x100hz <= 0;
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temp_out <= 0;
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temp_valid <= 0;
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end
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else begin
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temp_valid <= freq_valid;
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if (freq_valid) begin
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freq_x100hz <= freq;
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if (mode == 0) begin
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// 模式0：线性输出
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// 频率范围：500~1300（50.0kHz~130.0kHz）
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if (freq < 500)
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temp_out <= -400;
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else if (freq > 1300)
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temp_out <= 850;
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else
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temp_out <= -400 + ((freq - 500) * 1250) / 800;
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end else begin
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// 模式1：查表输出
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if (freq < 500)
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temp_out <= temp_lut[0];
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else if (freq > 1300)
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temp_out <= temp_lut[800];
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else
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temp_out <= temp_lut[freq - 500];
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end
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end
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end
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end
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pulse_freq_10ms u_freq_measure (
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.clk (clk),
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.rst_n (rst_n),
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.vin (vin),
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.freq (freq), //1302 ->130.2KHz
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.valid (freq_valid)
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);
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endmodule
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