159 lines
4.7 KiB
Systemverilog
159 lines
4.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module tb_digital_top();
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// 参数定义
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parameter CLK_PERIOD = 20; // 100MHz 系统时钟
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parameter SCLK_PERIOD = 200; // 10MHz SPI时钟 (必须比系统时钟慢)
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// 信号声明
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logic clk;
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logic rst_n;
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logic [4:0] cfgid;
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logic sclk;
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logic csn;
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logic mosi;
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logic miso;
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logic oen;
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logic sig_in;
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// 实例化 DUT
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digital_top u_digital_top (
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.clk (clk ),
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.rst_n (rst_n ),
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.cfgid (cfgid ),
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.sclk (sclk ),
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.csn (csn ),
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.mosi (mosi ),
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.miso (miso ),
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.oen (oen ),
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.sig_in ( sig_in )
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);
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// 系统时钟产生
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initial begin
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clk = 0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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// 初始复位与赋值
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initial begin
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rst_n = 0;
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sclk = 0;
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csn = 1;
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mosi = 0;
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cfgid = 5'h00; // 设定芯片ID为 10
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#(CLK_PERIOD * 10);
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rst_n = 1;
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#(CLK_PERIOD * 10);
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fork
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begin // --- 开始测试 ---
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#2ms;
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spi_read(25'h08, 5'h00);
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#(CLK_PERIOD * 10);
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spi_read(25'h0c, 5'h00);
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#(CLK_PERIOD * 10);
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spi_write(25'h08, 5'h00, 32'h2);
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end
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begin
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gen_pulses(1000,5);
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end
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join
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// spi_read(25'h04, 5'h00);
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//aa
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// spi_read(25'h00, 5'h0A);
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// #(SCLK_PERIOD * 5);
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// spi_read(25'h00, 5'h0A);
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// // 1. 测试写操作: 写入 0x12345678 到 地址 0x100
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// spi_write(25'h00, 5'h0A, 32'h12345678);
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// #(SCLK_PERIOD * 5);
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// // 2. 测试读操作: 从地址 0x100 读取 (验证读使能和地址)
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// spi_read(25'h00, 5'h0A);
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#(SCLK_PERIOD * 20);
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$display("Test Bench Finished.");
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$finish;
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end
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// ---------------------------------------------------------
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// Task: SPI 发送/接收 32位数据
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// ---------------------------------------------------------
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task spi_xfer_32(input [31:0] data_in, output [31:0] data_out);
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for (int i = 31; i >= 0; i--) begin
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mosi = data_in[i]; // MSB First ,psclk前给数据 psclk让人采样. 自己什么时候采？要看别人什么时候给数据
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#(SCLK_PERIOD/2);
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sclk = 1; // 上升沿，DUT采样
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data_out[i] = miso;
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// 采样从机发回的数据
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#(SCLK_PERIOD/2);
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sclk = 0;
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end
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endtask
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// ---------------------------------------------------------
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// Task: 写操作 (wnr=0)
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// ---------------------------------------------------------
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task spi_write(input [24:0] target_addr, input [4:0] id, input [31:0] data);
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logic [31:0] header;
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logic [31:0] dummy;
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header = {1'b0, target_addr, id, 1'b0}; // 构造命令帧
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$display("[WRITE] Addr: %h, Data: %h", target_addr, data);
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csn = 0;
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spi_xfer_32(header, dummy); // 发送命令
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spi_xfer_32(data, dummy); // 发送数据
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csn = 1;
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mosi = 0;
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endtask
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// ---------------------------------------------------------
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// Task: 读操作 (wnr=1)
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// ---------------------------------------------------------
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task spi_read(input [24:0] target_addr, input [4:0] id);
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logic [31:0] header;
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logic [31:0] read_val;
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header = {1'b1, target_addr, id, 1'b0}; // 构造命令帧 (wnr=1)
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$display("[READ] Addr: %h", target_addr);
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csn = 0;
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spi_xfer_32(header, read_val); // 发送命令帧，此时读回的可能是无用数据
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spi_xfer_32(32'h0, read_val); // 发送Dummy，接收真正的读数据
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csn = 1;
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mosi = 0;
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$display("[READ] Result: %h", read_val);
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endtask
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task automatic gen_pulses(input int freq_khz, input int duration_ms);
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int half_period_ns;
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longint end_time_ns;
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begin
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if (freq_khz <= 0) begin
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sig_in = 0;
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#(duration_ms * 1000000);
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end else begin
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half_period_ns = 500000 / freq_khz;
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end_time_ns = $time + (longint'(duration_ms) * 1000000);
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$display("[%0t] Start generating signal: %0d kHz", $time, freq_khz);
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while ($time < end_time_ns) begin
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sig_in = 1;
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#(half_period_ns);
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sig_in = 0;
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#(half_period_ns);
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end
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end
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end
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endtask
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endmodule |