93 lines
1.8 KiB
Verilog
93 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/04/03 22:01:15
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// Design Name:
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// Module Name: digital_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module digital_top(
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input clk,
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input rst_n,
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//spi_slave
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input sclk,
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input [4:0]cfgid,
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input csn,
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input mosi,
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output miso,
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output oen,
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//pulse_counter
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input sig_in
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);
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wire [31:0] wrdata;
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wire [24:0] addr;
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wire wren;
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wire rden;
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wire [31:0]rddata;
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wire [23:0] win_us;
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wire cnt_vld;
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wire [23:0]cnt_out;
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// 实例化 DUT
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spi_sys u_spi_sys (
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.clk (clk ),
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.rst_n (rst_n ),
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.cfgid (cfgid ),
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.sclk (sclk ),
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.csn (csn ),
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.mosi (mosi ),
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.miso (miso ),
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.oen (oen ),
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.wrdata (wrdata ),
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.addr (addr ),
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.wren (wren ),
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.rden (rden ),
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.rddata (rddata )
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);
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system_regfile u_system_regfile (
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.clk (clk),
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.rst_n (rst_n),
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.wrdata (wrdata),
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.wren (wren),
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.rwaddr (addr),
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.rden (rden),
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.rddata (rddata),
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// digital_thermometer
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.win_us(win_us),
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.pulse_cnt_out(cnt_out),
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.pules_cnt_vld(cnt_vld)
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);
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pulse_cnt #(
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.CLK_FREQ(50_000_000)
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) u_pulse_cnt (
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.clk (clk),
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.rst_n (rst_n),
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.sig_in (sig_in),
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.win_us (win_us),
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.cnt_out(cnt_out),
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.vld_out(cnt_vld)
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);
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endmodule
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