45 lines
798 B
Verilog
45 lines
798 B
Verilog
`timescale 1ns / 1ps
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module uart_byte_tx_tb();
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reg Clk;
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reg Reset_n;
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reg [7:0]Data;
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reg Send_Go;
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wire uart_tx;
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wire Tx_Done;
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uart_byte_tx uart_byte_tx(
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.Clk(Clk),
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.Reset_n(Reset_n),
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.Data(Data),
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.uart_tx(uart_tx),
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.Send_Go(Send_Go),
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.Tx_Done(Tx_Done)
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);
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// defparam uart_byte_tx.MCNT_DLY = 50_000_0 - 1;
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initial Clk = 1;
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always #10 Clk = ~Clk;
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initial begin
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Reset_n = 0;
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#200;
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Reset_n = 1;
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Data = 8'b0101_0101;
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Send_Go = 1 ;
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#20;
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Send_Go = 0;
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#20;
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#30000000;
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Data = 8'b1010_1010;
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Send_Go = 1 ;
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#20;
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Send_Go = 0;
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#20;
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#30000000;
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$stop;
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end
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endmodule
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