230 lines
7.6 KiB
Systemverilog
230 lines
7.6 KiB
Systemverilog
`timescale 1ns / 1ps
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module TB();
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// ==========================================
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// Parameters & Signal Definitions
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// ==========================================
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parameter CLK_PERIOD = 20; // 50MHz
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parameter BAUD = 115200;
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localparam BIT_TIME = 1_000_000_000 / BAUD;
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reg clk;
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reg rst_n;
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reg uart_rx; // DUT RX
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wire uart_tx; // DUT TX
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reg sig_in;
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// Clock Generation
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initial clk = 0;
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always #(CLK_PERIOD/2) clk = ~clk;
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// initial begin
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// $fsdbDumpfile("wave.fsdb");
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// $fsdbDumpvars();
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// end
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// ==========================================
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// DUT Instantiation
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// ==========================================
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digital_top u_digital_top(
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.clk (clk),
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.rst_n (rst_n),
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.uart_rx (uart_rx),
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.uart_tx (uart_tx),
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.sig_in (sig_in)
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);
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// // ==========================================
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// // TX Driver: Read from case.txt
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// // ==========================================
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// initial begin
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// int file_h;
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// int status;
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// logic [63:0] val;
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// // Initialize signals
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// rst_n = 0;
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// uart_rx = 1;
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// #(CLK_PERIOD * 10);
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// rst_n = 1;
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// file_h = $fopen("case.txt", "r");
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// if (!file_h) begin
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// $display("[TX ERROR] Cannot open case.txt");
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// $finish;
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// end
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// $display("[TX] Starting transmission...");
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// while (!$feof(file_h)) begin
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// // Read hex data per line
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// status = $fscanf(file_h, "%h\n", val);
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// if (status == 1) begin
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// if (val > 64'hFFFF_FFFF) begin
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// $display("[%t] TX CMD: %h", $time, val);
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// send_data(val, 64);
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// end else begin
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// $display("[%t] TX DATA: %h", $time, val[31:0]);
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// send_data(val[31:0], 32);
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// end
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// #(BIT_TIME * 5); // Frame gap
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// }
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// end
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// $fclose(file_h);
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// $display("[TX] All cases sent.");
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// // Wait for RX return data
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// #(BIT_TIME * 500);
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// $display("[SIM] Simulation finished.");
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// $finish;
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// end
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// ==========================================
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// RX Monitor: Save to rx_data.txt
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// ==========================================
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int rx_file_h;
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initial begin
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logic [7:0] rx_byte;
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rx_file_h = $fopen("rx_data.txt", "w");
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if (!rx_file_h) begin
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$display("[RX ERROR] Cannot create rx_data.txt");
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$finish;
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end
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forever begin
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logic [31:0] packet_word; // 32-bit data packet
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logic [7:0] rx_byte;
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// Collect 4 bytes to form 32-bit data
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for (int byte_idx = 0; byte_idx < 4; byte_idx++) begin
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// 1. Wait for start bit (falling edge)
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@(negedge uart_tx);
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// 2. Skip start bit, sample at center point
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#(BIT_TIME / 2);
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#(BIT_TIME);
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// Read 8 data bits
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for (int i = 0; i < 8; i++) begin
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rx_byte[i] = uart_tx;
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#(BIT_TIME);
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end
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// Combine to 32-bit (little-endian)
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packet_word[24 - 8*byte_idx +: 8] = rx_byte;
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// $display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte);
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// Wait for end of stop bit
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if (byte_idx < 3) begin
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#(BIT_TIME / 2);
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end
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end
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// Write to file (one 32-bit data per line)
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$fdisplay(rx_file_h, "%08h", packet_word);
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$display("[%0t] Packet (32-bit): 0x%08h", $time, packet_word);
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// Wait for end of last stop bit
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#(BIT_TIME / 2);
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end
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end
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final begin
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if (rx_file_h) begin
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$fclose(rx_file_h);
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$display("[RX] File closed at %t",$time);
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end
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end
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// --- Pulse Generation Task ---
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// freq_khz: Target frequency (kHz)
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// duration_ms: Test duration (ms)
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task automatic gen_pulses(input int freq_khz, input int duration_ms);
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int half_period_ns;
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longint end_time_ns;
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begin
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if (freq_khz <= 0) begin
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sig_in = 0;
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#(duration_ms * 1000000);
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end else begin
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half_period_ns = 500000 / freq_khz;
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end_time_ns = $time + (longint'(duration_ms) * 1000000);
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$display("[%0t] Start generating signal: %0d kHz", $time, freq_khz);
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while ($time < end_time_ns) begin
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sig_in = 1;
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#(half_period_ns);
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sig_in = 0;
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#(half_period_ns);
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end
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end
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end
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endtask
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// ==========================================
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// Task: Send one byte (Serial TX)
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// ==========================================
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task automatic send_byte(input [7:0] data);
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begin
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uart_rx = 0; // Start bit
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#(BIT_TIME);
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for (int i = 0; i < 8; i++) begin
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uart_rx = data[i]; // LSB First
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#(BIT_TIME);
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end
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uart_rx = 1; // Stop bit
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#(BIT_TIME);
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end
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endtask
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// Task: Send 32/64 bit data
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task automatic send_data(input [63:0] data, input int len_bits);
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int bytes = len_bits / 8;
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for (int i = bytes - 1; i >= 0; i--) begin // Send from highest byte
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send_byte(data[i*8 +: 8]);
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end
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endtask
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initial begin
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// 1. Initialization
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rst_n = 0; uart_rx = 1; sig_in = 0;
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#(CLK_PERIOD * 20);
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rst_n = 1;
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#(CLK_PERIOD * 100);
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$display("------- Step 1: read Thermometer Regs -------");
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send_data(64'h80000004_00000004,64);
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send_data(64'h80000008_00000004,64); //mode[25:24] + win
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send_data(64'h8000000c_00000004,64); //calibration H / L
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send_data(64'h80000010_00000004,64); //rep[31] +rep_gap[23:0]
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send_data(64'h80000014_00000004,64); //result [23:0]
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$display("------- Step 2: Running Concurrent Tasks -------");
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fork
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// Process A: Generate input pulses (simulate temperature change)
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begin
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gen_pulses(200, 10); // 100kHz for 10ms
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gen_pulses(300, 20);
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gen_pulses(400, 30);
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end
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// Process B: Insert read command during reporting
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begin
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#(6ms); // Wait for first report packet
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send_data(64'h80000014_00000004,64); $display("[%0t] == Sending Read Request ==", $time);
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send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); $display("[%0t] == open report_en==",$time);
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send_data(64'h0000008_00000004,64);send_data(32'h0100_03e8,32); $display("[%0t] == mode = 1 ==",$time);
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#15ms;
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send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);$display("[%0t] == cloese report_en==",$time);
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//send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); $display("[%0t] == open report_en==",$time);
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//send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);$display("[%0t] == cloese report_en==",$time);
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#30000;
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send_data(64'h80000014_00000004,64);
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end
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join
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#(BIT_TIME * 500);
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$display("Test Done.");
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$finish;
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end
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endmodule |