134 lines
5.8 KiB
Verilog
134 lines
5.8 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// 增加一个新寄存器：
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// SECTION A: 添加 localparam ADDR_NEW = 16'hXX;。
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// SECTION B: 声明 wire sel_new, we_new, [31:0] reg_new;。
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// SECTION C: 增加译码逻辑：assign sel_new = (reg_idx == ADDR_NEW >> 2);。
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// SECTION D: 调用底层库，例如 sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);。
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// SECTION F: 在 always 块中加入 else if (sel_new) rddata_reg = reg_new;。
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// SECTION G: 将 reg_new 映射给模块的输出端口。
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//-FHDR--------------------------------------------------------------------------------------------------------
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module system_regfile (
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// [BLOCK 0] 系统与总线接口
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input clk,
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input rst_n,
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input [31:0] wrdata,
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input wren,
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input [24:0] rwaddr,
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input rden,
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output [31:0] rddata,
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output [23:0]win_us,
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output [1:0]out_mode, //0输出对应温度， 1输出对应的频率，2单位窗口输出脉冲的个数
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output [15:0]temp_85_fre_k, //85°对应的频率,默认为600khz
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output [15:0]temp_neg_40_fre_k , //-40对应的频率，默认为160khz,单位khz
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output report_en,
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output [23:0]rep_gap_us, //最小位win_us 小于就不上报了
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input [23:0]therm_out,
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input therm_vld
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);
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// =============================================================================
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// [SECTION A] 地址偏移定义 (Localparams)
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// =============================================================================
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localparam TESTR = 16'h00, DATER = 16'h04;
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localparam WIN_MODE_R = 16'h08; // 配置窗口时间与输出模式
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localparam CALIB_R = 16'h0C; // 标定参数寄存器
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localparam REPORT_R = 16'h10; // 上报使能与间隔
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localparam RESULT_R = 16'h14; // 状态与结果寄存器 (只读)
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// =============================================================================
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// [SECTION B] 内部连线声明 (Wires)
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// =============================================================================
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// 寄存器选择信号 (Enable Wires)
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wire sel_testr, sel_dater;
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wire sel_win_mode, sel_calib, sel_report, sel_result;
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// 写使能信号 (Write Enable Wires)
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wire we_testr, we_dater;
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wire we_win_mode, we_calib, we_report;
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// 寄存器存储连线 (Storage Wires)
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wire [31:0] testr, dater;
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wire [31:0] win_mode_r, calib_r, report_r, result_r;
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// =============================================================================
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// [SECTION C] 译码逻辑 (Decoding)
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// =============================================================================
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assign sel_testr = (rwaddr[15:0] == TESTR );
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assign sel_dater = (rwaddr[15:0] == DATER );
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assign sel_win_mode = (rwaddr[15:0] == WIN_MODE_R );
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assign sel_calib = (rwaddr[15:0] == CALIB_R );
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assign sel_report = (rwaddr[15:0] == REPORT_R );
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assign sel_result = (rwaddr[15:0] == RESULT_R );
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// 写使能分配
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assign we_testr = sel_testr & wren;
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assign we_dater = sel_dater & wren;
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assign we_win_mode = sel_win_mode & wren;
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assign we_calib = sel_calib & wren;
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assign we_report = sel_report & wren;
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// =============================================================================
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// [SECTION D] 寄存器实例化 (Storage Implementation)
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// =============================================================================
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// --- 通用与测试寄存器 ---
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sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n);
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sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n);
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// --- 温度计业务寄存器 ---
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// win_mode_r: [25:24] out_mode, [23:0] win_us (默认窗口 1000us)
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sirv_gnrl_dfflrd #(32) win_mode_dff (32'h0000_03E8, we_win_mode, wrdata, win_mode_r, clk, rst_n);
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// calib_r: [31:16] 85度频率(默认600k), [15:0] -40度频率(默认160k)
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sirv_gnrl_dfflrd #(32) calib_dff (32'h0258_00A0, we_calib, wrdata, calib_r, clk, rst_n);
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// report_r: [31] report_en, [23:0] rep_gap_us (默认间隔 50ms)
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sirv_gnrl_dfflrd #(32) report_dff (32'h0000_C350, we_report, wrdata, report_r, clk, rst_n);
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sirv_gnrl_dffr #(32) result_dff ({8'b0,therm_out},result_r, clk, rst_n);
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// =============================================================================
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// [SECTION E] 特殊业务逻辑 (Business Logic)
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// =============================================================================
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// LVDS 实时状态寄存器
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// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n);
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// =============================================================================
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// [SECTION F] 读回逻辑 (Readback Mux)
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// =============================================================================
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reg [31:0] rddata_reg;
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always @(*) begin
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rddata_reg = 32'b0;
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if (sel_testr) rddata_reg = testr;
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else if (sel_dater) rddata_reg = dater;
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else if (sel_win_mode) rddata_reg = win_mode_r;
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else if (sel_calib) rddata_reg = calib_r;
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else if (sel_report) rddata_reg = report_r;
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else if (sel_result) rddata_reg = result_r;
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end
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sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n);
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// =============================================================================
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// [SECTION G] 输出映射 (Output Assignments)
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// =============================================================================
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assign win_us = win_mode_r[23:0];
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assign out_mode = win_mode_r[25:24];
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assign temp_85_fre_k = calib_r[31:16];
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assign temp_neg_40_fre_k = calib_r[15:0];
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assign report_en = report_r[31];
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assign rep_gap_us = report_r[23:0];
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endmodule |