151 lines
4.6 KiB
Verilog
151 lines
4.6 KiB
Verilog
`timescale 1ns / 1ps
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module uart_ctrl_sysreg #(
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parameter BAUD = 115200,
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parameter CLOCK_FREQ = 50_000_000
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)(
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input clk
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,input rst_n
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// UART Interface
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,input uart_rx
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,output uart_tx
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// Register File Interface
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,output reg [31:0] o_wrdata //write data to register file
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,output reg [24:0] o_addr //register file address
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,output reg o_wren //write enable to register file
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,output reg o_rden //read enable to register file
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,input [31:0] i_rddata //read data from register file
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// Auto-Report Mechanism
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,input [23:0] i_report_data
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,input i_report_vld
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);
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// --- uart_top ---
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wire [31:0] uart_rx_data;
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wire uart_rx_done;
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reg [31:0] uart_tx_data;
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reg uart_tx_go;
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wire uart_tx_done;
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uart_top_32bit #(
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.BAUD(BAUD),
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.CLOCK_FREQ(CLOCK_FREQ)
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) uart_32bit_inst (
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.Clk(clk), .Reset_n(rst_n),
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.Send_Go32(uart_tx_go), .Tx_Data32(uart_tx_data), .Tx_Done32(uart_tx_done),
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.uart_tx(uart_tx), .uart_rx(uart_rx),
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.Rx_Done32(uart_rx_done), .Rx_Data32(uart_rx_data)
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);
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// Protocol parsing registers
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reg [63:0] cmd_reg;
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reg [31:0] wr_data_buff;
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reg [19:0] data_bytes_len;
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// State machine definition
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reg [2:0] state;
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localparam S_IDLE = 3'd0,
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S_RX_CMD_L = 3'd1,
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S_PARSE = 3'd2,
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S_WAIT_RD = 3'd3,
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S_RD_DATA = 3'd4,
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S_WR_DATA = 3'd5,
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S_REPORT = 3'd6; // Auto-report state
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// Latch auto-report data
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reg [23:0] report_data_latch;
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reg report_pending;
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// Capture report pulse: store if busy
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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report_pending <= 1'b0;
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report_data_latch <= 24'd0;
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end else if(i_report_vld) begin
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report_pending <= 1'b1;
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report_data_latch <= i_report_data;
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end else if(state == S_REPORT) begin
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report_pending <= 1'b0; // Clear flag after entering report state
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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state <= 0;
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cmd_reg <= 0;
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o_wrdata <= 0;
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o_wren <= 0;
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o_rden <= 0;
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uart_tx_go <= 1'b0;
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uart_tx_data <= 1'b0;
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end
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else begin
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case(state)
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S_IDLE : begin // IDLE state
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uart_tx_go <= 1'b0;
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if(uart_rx_done) begin
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cmd_reg[63:32] <= uart_rx_data;
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state <= S_RX_CMD_L;
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end
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else if(report_pending) begin
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state <= S_REPORT;
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end
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end
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S_RX_CMD_L : begin // Receive lower command word
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if(uart_rx_done)begin
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cmd_reg[31:0] <= uart_rx_data;
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state <= S_PARSE;
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end
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end
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S_PARSE : begin // Parse command
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o_addr <= cmd_reg[56:32];
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data_bytes_len <= cmd_reg[19:0];
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if(cmd_reg[63] == 1'b1) begin // Read command
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o_rden <= 1'b1;
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state <= S_WAIT_RD;
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end
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else begin // Write command
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state <= S_WR_DATA;
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end
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end
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S_WAIT_RD : begin // Wait for read data ready
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o_rden <= 1'b0;
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state <= S_RD_DATA;
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end
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S_RD_DATA :begin // Transmit read data
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uart_tx_data <= i_rddata;
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uart_tx_go <= 1'b1;
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state <= S_IDLE;
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end
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S_WR_DATA : begin // Receive and write data
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o_wren <= 1'b0;
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if(data_bytes_len != 0)begin
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if(uart_rx_done) begin
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o_wrdata <= uart_rx_data;
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o_wren <= 1'b1;
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data_bytes_len <= data_bytes_len - 20'd4;
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end
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end
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else begin
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state <= S_IDLE;
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end
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end
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S_REPORT : begin // Auto-report data
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// Construct report packet: [8'hAA (header) + 24bit sensor data]
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uart_tx_data <= {8'hAA, report_data_latch};
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uart_tx_go <= 1'b1;
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state <= S_IDLE;
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule |