97 lines
2.4 KiB
Verilog
97 lines
2.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/04/03 22:01:15
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// Design Name:
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// Module Name: digital_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module digital_top(
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input clk,
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input rst_n,
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input uart_rx,
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output uart_tx,
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input sig_in
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);
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wire [31:0] w_wrdata;
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wire [24:0] w_addr;
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wire w_wren;
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wire w_rden;
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wire [31:0] w_rddata;
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wire [23:0] win_us;
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wire [1:0] out_mode;
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wire [15:0] temp_85_fre_k;
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wire [15:0] temp_neg_40_fre_k;
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wire report_en;
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wire [23:0] rep_gap_us;
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wire therm_vld;
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wire [23:0] therm_out;
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uart_ctrl_sysreg #(
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.BAUD (115200),
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.CLOCK_FREQ (50_000_000)
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) u_uart_ctrl (
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.clk (clk),
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.rst_n (rst_n),
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.uart_rx (uart_rx),
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.uart_tx (uart_tx),
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.o_wrdata (w_wrdata),
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.o_addr (w_addr),
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.o_wren (w_wren),
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.o_rden (w_rden),
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.i_rddata (w_rddata),
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.i_report_data (therm_out),
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.i_report_vld (therm_vld)
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);
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system_regfile u_system_regfile (
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.clk (clk),
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.rst_n (rst_n),
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.wrdata (w_wrdata),
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.wren (w_wren),
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.rwaddr (w_addr),
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.rden (w_rden),
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.rddata (w_rddata),
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// digital_thermometer
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.win_us(win_us),
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.out_mode(out_mode),
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.temp_85_fre_k(temp_85_fre_k),
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.temp_neg_40_fre_k(temp_neg_40_fre_k),
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.report_en(report_en),
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.rep_gap_us(rep_gap_us),
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.therm_out(therm_out),
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.therm_vld(therm_vld)
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);
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digital_thermometer u_digital_thermometer (
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.clk (clk),
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.rst_n (rst_n),
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.sig_in (sig_in),
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.win_us (win_us),
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.out_mode (out_mode),
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.temp_85_fre_k (temp_85_fre_k),
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.temp_neg_40_fre_k (temp_neg_40_fre_k),
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.report_en (report_en),
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.rep_gap_us (rep_gap_us),
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.therm_out (therm_out),
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.therm_vld (therm_vld)
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);
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endmodule
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