96 lines
1.8 KiB
Verilog
96 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/03/22 18:54:47
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// Design Name:
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// Module Name: TB
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module tb_digital_thermometer;
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reg clk;
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reg rst_n;
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reg vin;
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reg mode;
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wire [19:0] freq_x100hz;
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wire [15:0] temp_out;
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wire temp_valid;
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// 例化待测模块
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digital_thermometer uut (
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.clk (clk),
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.rst_n (rst_n),
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.vin (vin),
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.mode (mode),
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.freq_x100hz (freq_x100hz),
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.temp_out (temp_out),
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.temp_valid (temp_valid)
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);
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// 时钟：50MHz
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initial clk = 0;
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always #10 clk = ~clk;
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// 测试流程
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initial begin
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// 复位
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rst_n = 0;
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mode = 0;
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#100;
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rst_n = 1;
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gen_pulse(52,20);
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gen_pulse(74,20);
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gen_pulse(104.7,20);
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gen_pulse(130,20);
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mode = 1;
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gen_pulse(52,20);
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gen_pulse(74,20);
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gen_pulse(104.7,20);
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gen_pulse(130,20);
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#10000;
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$finish;
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end
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//
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task gen_pulse;
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input real freq_kHz;
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input [7:0] time_ms;
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integer cycles;
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integer i;
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begin
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//操控reg vin
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cycles = time_ms * freq_kHz;
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vin = 0;
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for (i = 0; i < cycles; i = i + 1) begin
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vin = 1;
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#(500000/freq_kHz);
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vin = 0;
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#(500000/freq_kHz);
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end
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end
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endtask
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endmodule
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