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温度计的数字模块
10 Commits 1 Branch 0 Tags 3.3 MiB
C 54%
Verilog 20.5%
SystemVerilog 9.8%
Batchfile 9.8%
Makefile 3.2%
Other 2.7%
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yangshenbo 00e77e901a 增加doc 2026-04-07 10:03:00 +08:00
doc/设计报告 增加doc 2026-04-07 10:03:00 +08:00
rtl organize the table + translate 2026-04-07 09:50:35 +08:00
sim/therm_chip_top organize the table + translate 2026-04-07 09:50:35 +08:00
tb organize the table + translate 2026-04-07 09:50:35 +08:00