95 lines
2.8 KiB
Verilog
95 lines
2.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Yangshenbo
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// version:V1.0
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// Create Date: 2026/04/05
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//////////////////////////////////////////////////////////////////////////////////
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module digital_thermometer(
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input clk,
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input rst_n,
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input sig_in,
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input [23:0]win_us,
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input [1:0]out_mode, //0: output temperature, 1: output frequency, 2: output pulse count per window
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input [15:0]temp_85_fre_k, //Frequency at 85¡ãC, default 600khz
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input [15:0]temp_neg_40_fre_k , //Frequency at -40¡ãC, default 160khz, unit khz
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input report_en, //Auto report enable
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input [23:0]rep_gap_us, //Minimum report gap (us)
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output reg [23:0]therm_out,
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output reg therm_vld
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);
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wire [23:0] wd_cnt_out;
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wire wd_cnt_vld;
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reg [23:0] gap_cnt; // Report interval counter
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reg [23:0] cur_freq_khz;
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reg signed [23:0] temp_scaled;
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always @(posedge clk or negedge rst_n)begin
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if(!rst_n)begin
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cur_freq_khz <= 0;
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temp_scaled <= 0;
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end
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else begin
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cur_freq_khz <= (wd_cnt_out * 1000) / win_us;
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if (cur_freq_khz <= temp_neg_40_fre_k) begin
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temp_scaled <= -32'sd4000;
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end
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else begin
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temp_scaled <= ((cur_freq_khz - temp_neg_40_fre_k) * 12500) / (temp_85_fre_k - temp_neg_40_fre_k) - 4000;
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end
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end
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end
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// Report logic and output selection
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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gap_cnt <= 0;
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therm_vld <= 0;
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therm_out <= 0;
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end else if (wd_cnt_vld) begin
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if (report_en) begin
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if (gap_cnt >= (rep_gap_us / win_us) - 1) begin
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gap_cnt <= 0;
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therm_vld <= 1'b1;
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end else begin
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gap_cnt <= gap_cnt + 1'b1;
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therm_vld <= 1'b0;
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end
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end
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else begin
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gap_cnt <= 0;
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therm_vld <= 1'b0;
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end
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//Output mode switching
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case (out_mode)
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2'd0: therm_out <= temp_scaled; //Output temperature scaled by 100
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2'd1: therm_out <= cur_freq_khz; //Output frequency (kHz)
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2'd2: therm_out <= wd_cnt_out; //Output raw pulse count
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default: therm_out <= temp_scaled;
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endcase
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end
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else begin
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therm_vld <= 1'b0;
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end
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end
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//Instantiate sub-module
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pulse_cnt #(
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.CLK_FREQ(50_000_000)
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) pulse_cnt_inst (
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.clk (clk),
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.rst_n (rst_n),
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.sig_in (sig_in),
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.win_us (win_us),
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.cnt_out(wd_cnt_out),
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.vld_out(wd_cnt_vld)
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);
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endmodule |