59 lines
1.7 KiB
Verilog
59 lines
1.7 KiB
Verilog
`timescale 1ns / 1ps
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module pulse_cnt #(
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parameter CLK_FREQ = 50_000_000
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) (
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input wire clk,
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input wire rst_n,
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input wire sig_in,
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input wire [31:0] win_time,
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output reg [23:0] cnt_out,
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output reg vld_out
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);
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reg [31:0] window_cnt; // Current clock cycle count
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reg [31:0] target_cnt; // Required clock cycles for current measurement window
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// Pulse counter (width matches output to prevent overflow)
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reg [23:0] pulse_cnt;
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reg sig_sync1, sig_sync2, sig_sync3;
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wire sig_rise = sig_sync2 & ~sig_sync3;
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always @(posedge clk) begin
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sig_sync1 <= sig_in;
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sig_sync2 <= sig_sync1;
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sig_sync3 <= sig_sync2;
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end
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// Main control logic
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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window_cnt <= 0;
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pulse_cnt <= 0;
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cnt_out <= 0;
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vld_out <= 0;
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target_cnt <= 24'd50_000;
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end else begin
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vld_out <= 1'b0;
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target_cnt <= win_time ;
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// Window count end condition: current count reaches target_cnt
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if (window_cnt >= target_cnt) begin
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cnt_out <= pulse_cnt;
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vld_out <= 1'b1;
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// Reset window counter and pulse counter, trigger target value recalculation
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window_cnt <= 0;
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pulse_cnt <= 0;
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end else begin
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window_cnt <= window_cnt + 1;
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if (sig_rise)
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pulse_cnt <= pulse_cnt + 1;
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end
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end
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end
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endmodule |