111 lines
4.3 KiB
Verilog
111 lines
4.3 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Add a new register:
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// SECTION A: Add localparam ADDR_NEW = 16'hXX;.
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// SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;.
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// SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);.
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// SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);.
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// SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block.
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// SECTION G: Map reg_new to the module's output ports.
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//-FHDR--------------------------------------------------------------------------------------------------------
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module system_regfile (
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// [BLOCK 0] System and Bus Interface
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input clk,
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input rst_n,
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input [31:0] wrdata,
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input wren,
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input [24:0] rwaddr,
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input rden,
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output [31:0] rddata,
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output [31:0] win_time,
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input [23:0]pulse_cnt_out,
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input pules_cnt_vld
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);
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// =============================================================================
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// [SECTION A] Address Offset Definition (Localparams)
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// =============================================================================
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localparam TESTR = 16'h00, DATER = 16'h04;
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localparam WIN_TIME_R =16'h08 ;
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localparam RESULT_R =16'h0c ;
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// =============================================================================
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// [SECTION B] Internal Wire Declaration (Wires)
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// =============================================================================
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// Register selection signals (Enable Wires)
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wire sel_testr, sel_dater;
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wire sel_win_time, sel_result;
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// Write enable signals (Write Enable Wires)
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wire we_testr, we_dater;
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wire we_win_time;
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// Register storage wires (Storage Wires)
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wire [31:0] testr, dater , win_time_r;
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wire [23:0] result_r;
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// =============================================================================
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// [SECTION C] Decoding Logic (Decoding)
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// =============================================================================
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assign sel_testr = (rwaddr[15:0] == TESTR );
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assign sel_dater = (rwaddr[15:0] == DATER );
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assign sel_win_time = (rwaddr[15:0] == WIN_TIME_R );
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assign sel_result = (rwaddr[15:0] == RESULT_R );
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// Write enable allocation
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assign we_testr = sel_testr & wren;
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assign we_dater = sel_dater & wren;
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assign we_win_time = sel_win_time & wren;
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// =============================================================================
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// [SECTION D] Register Instantiation (Storage Implementation)
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// =============================================================================
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// --- General and Test Registers ---
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sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n);
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sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n);
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// --- Thermometer Functional Registers ---
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sirv_gnrl_dfflrd #(32) win_time_dff (32'h0000_C350, we_win_time, wrdata, win_time_r, clk, rst_n);
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sirv_gnrl_dfflr #(24) result_dff (pules_cnt_vld,pulse_cnt_out,result_r, clk, rst_n);
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// =============================================================================
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// [SECTION E] Special Business Logic (Business Logic)
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// =============================================================================
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// LVDS Real-time status register
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// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n);
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// =============================================================================
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// [SECTION F] Readback Logic (Readback Mux)
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// =============================================================================
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reg [31:0] rddata_reg;
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always @(*) begin
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rddata_reg = 32'b0;
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if (sel_testr) rddata_reg = testr;
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else if (sel_dater) rddata_reg = dater;
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else if (sel_win_time) rddata_reg = win_time_r;
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else if (sel_result) rddata_reg = {8'b0,result_r};
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end
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sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n);
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// =============================================================================
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// [SECTION G] Output Mapping (Output Assignments)
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// =============================================================================
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assign win_time = win_time_r;
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endmodule |