Command: vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k -debug_access+pp -lca -q -timescale=1ns/1ps \
+nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb \
-f filelist_vlg.f

Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

VCS Coverage Metrics Release O-2018.09-SP2_Full64 Copyright (c) 1991-2018 by Synopsys Inc.

Note-[VCS_PARAL] Parallel code-gen enabled
  VCS is running with parallel code generation(-j)...

6 modules and 0 UDP read.
make[1]: Entering directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \

ld -shared  -Bsymbolic  -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o 
rm -f _csrc0.so
../simv up to date
make[1]: Leaving directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \