//+FHDR--------------------------------------------------------------------------------------------------------
// Add a new register:

// SECTION A: Add localparam ADDR_NEW = 16'hXX;.

// SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;.

// SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);.

// SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);.

// SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block.

// SECTION G: Map reg_new to the module's output ports.
//-FHDR--------------------------------------------------------------------------------------------------------

module system_regfile (
    // [BLOCK 0] System and Bus Interface
    input           clk,             
    input           rst_n,          
    input  [31:0]   wrdata,          
    input           wren,            
    input  [24:0]   rwaddr,          
    input           rden,            
    output [31:0]   rddata,

    output [31:0] win_time,
    input [23:0]pulse_cnt_out,
    input pules_cnt_vld

);

// =============================================================================
// [SECTION A] Address Offset Definition (Localparams)
// =============================================================================
 localparam TESTR      = 16'h00,   DATER     = 16'h04;
 localparam WIN_TIME_R =16'h08 ;
 localparam RESULT_R =16'h0c ;
 

// =============================================================================
// [SECTION B] Internal Wire Declaration (Wires)
// =============================================================================

// Register selection signals (Enable Wires)
 wire sel_testr,   sel_dater;
 wire sel_win_time, sel_result;

// Write enable signals (Write Enable Wires)
 wire we_testr, we_dater;
 wire we_win_time;


// Register storage wires (Storage Wires)
 wire [31:0] testr, dater , win_time_r;
 wire [23:0]   result_r;
// =============================================================================
// [SECTION C] Decoding Logic (Decoding)
// =============================================================================
 assign sel_testr    = (rwaddr[15:0] == TESTR );
 assign sel_dater    = (rwaddr[15:0] == DATER );
 assign sel_win_time = (rwaddr[15:0] == WIN_TIME_R );
 assign sel_result   = (rwaddr[15:0] == RESULT_R );

// Write enable allocation
assign we_testr    = sel_testr    & wren;
assign we_dater    = sel_dater    & wren;
assign we_win_time = sel_win_time & wren;


// =============================================================================
// [SECTION D] Register Instantiation (Storage Implementation)
// =============================================================================

// --- General and Test Registers ---
sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n);
sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n);

// --- Thermometer Functional Registers ---
sirv_gnrl_dfflrd #(32) win_time_dff (32'h0000_C350, we_win_time, wrdata, win_time_r, clk, rst_n);

sirv_gnrl_dfflr #(24) result_dff (pules_cnt_vld,pulse_cnt_out,result_r, clk, rst_n);

// =============================================================================
// [SECTION E] Special Business Logic (Business Logic)
// =============================================================================

// LVDS Real-time status register
// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n);

// =============================================================================
// [SECTION F] Readback Logic (Readback Mux)
// =============================================================================
reg [31:0] rddata_reg;
always @(*) begin 
    rddata_reg = 32'b0;
    if      (sel_testr)       rddata_reg = testr;
    else if (sel_dater)       rddata_reg = dater;
    else if (sel_win_time)    rddata_reg = win_time_r;
    else if (sel_result)      rddata_reg = {8'b0,result_r};
end

 sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n);

// =============================================================================
// [SECTION G] Output Mapping (Output Assignments)
// =============================================================================
    assign win_time            = win_time_r;


endmodule