`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2026/04/03 22:01:15
// Design Name: 
// Module Name: digital_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module digital_top(
    input clk,
    input rst_n,
    //spi_slave
    input sclk,
    input [4:0]cfgid,
    input csn,
    input mosi,
    output miso,
    output oen,
    //pulse_counter
    input sig_in
    );

wire [31:0] wrdata;      
wire [24:0] addr;        
wire        wren;        
wire        rden;        
wire  [31:0]rddata;      

wire  [31:0] win_time;
wire  cnt_vld;
wire  [23:0]cnt_out;


        // 实例化 DUT
    spi_sys u_spi_sys (
        .clk     (clk    ),
        .rst_n   (rst_n  ),
        .cfgid   (cfgid  ),
        .sclk    (sclk   ),
        .csn     (csn    ),
        .mosi    (mosi   ),
        .miso    (miso   ),
        .oen     (oen    ),
        .wrdata  (wrdata ),
        .addr    (addr   ),
        .wren    (wren   ),
        .rden    (rden   ),
        .rddata  (rddata )
    );

    system_regfile u_system_regfile (
        .clk    (clk),
        .rst_n  (rst_n),
        .wrdata (wrdata),
        .wren   (wren),
        .rwaddr (addr),
        .rden   (rden),
        .rddata (rddata),
        // digital_thermometer    
        .win_time(win_time),
        .pulse_cnt_out(cnt_out),
        .pules_cnt_vld(cnt_vld)
    );


    pulse_cnt #(
        .CLK_FREQ(50_000_000)
    ) u_pulse_cnt (
        .clk    (clk),
        .rst_n  (rst_n),
        .sig_in (sig_in),
        .win_time (win_time),
        .cnt_out(cnt_out),
        .vld_out(cnt_vld)
    );


endmodule