`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2026/04/03 22:01:15
// Design Name: 
// Module Name: digital_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module digital_top(
    input clk,
    input rst_n,
    input uart_rx,
    output  uart_tx,
    input sig_in
    );

wire [31:0] w_wrdata;      // DUT -> SRAM 写数据
wire [24:0] w_addr;        // DUT -> SRAM 地址
wire        w_wren;        // 写使能
wire        w_rden;        // 读使能
wire  [31:0] w_rddata;      // SRAM -> DUT 读数据

wire  [23:0] win_us;
wire  [1:0]  out_mode;
wire  [15:0] temp_85_fre_k;
wire  [15:0] temp_neg_40_fre_k;
wire          report_en;
wire  [23:0] rep_gap_us; 
wire        therm_vld;
wire  [23:0] therm_out;

    uart_ctrl_sysreg #(
        .BAUD       (115200),
        .CLOCK_FREQ (50_000_000)
    ) u_uart_ctrl (
        .clk        (clk),
        .rst_n      (rst_n),
        .uart_rx    (uart_rx),
        .uart_tx    (uart_tx),
        .o_wrdata   (w_wrdata),
        .o_addr     (w_addr),
        .o_wren     (w_wren),
        .o_rden     (w_rden),
        .i_rddata   (w_rddata),
        .i_report_data (therm_out),
        .i_report_vld  (therm_vld)
    );

    system_regfile u_system_regfile (
        .clk    (clk),
        .rst_n  (rst_n),
        .wrdata (w_wrdata),
        .wren   (w_wren),
        .rwaddr (w_addr),
        .rden   (w_rden),
        .rddata (w_rddata),
        // digital_thermometer    
        .win_us(win_us),
        .out_mode(out_mode),
        .temp_85_fre_k(temp_85_fre_k),
        .temp_neg_40_fre_k(temp_neg_40_fre_k),
        .report_en(report_en),
        .rep_gap_us(rep_gap_us),
        .therm_out(therm_out),
        .therm_vld(therm_vld)
    );

    digital_thermometer u_digital_thermometer (
        .clk                (clk),
        .rst_n              (rst_n),
        .sig_in             (sig_in),
        .win_us             (win_us),
        .out_mode           (out_mode),
        .temp_85_fre_k      (temp_85_fre_k),
        .temp_neg_40_fre_k  (temp_neg_40_fre_k),
        .report_en          (report_en),
        .rep_gap_us         (rep_gap_us),
        .therm_out          (therm_out),
        .therm_vld          (therm_vld)
    );

endmodule