`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2026/03/22 18:54:47
// Design Name: 
// Module Name: TB
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


`timescale 1ns / 1ps

module tb_digital_thermometer;

    reg         clk;
    reg         rst_n;
    reg         vin;
    reg         mode;
    wire [19:0] freq_x100hz;
    wire [15:0] temp_out;
    wire        temp_valid;

    // 例化待测模块
    digital_thermometer uut (
        .clk         (clk),
        .rst_n       (rst_n),
        .vin         (vin),
        .mode        (mode),
        .freq_x100hz (freq_x100hz),
        .temp_out    (temp_out),
        .temp_valid  (temp_valid)
    );

    // 时钟：50MHz
    initial clk = 0;
    always #10 clk = ~clk;




// 测试流程
    initial begin
        // 复位
        rst_n = 0;
        mode = 0;
        #100;
        rst_n = 1;
    gen_pulse(52,20);
    gen_pulse(74,20);
    gen_pulse(104.7,20);
    gen_pulse(130,20);
    mode = 1;
        gen_pulse(52,20);
    gen_pulse(74,20);
    gen_pulse(104.7,20);
    gen_pulse(130,20);
  
        #10000;
        $finish;
    end

//
task gen_pulse;
    input real freq_kHz;
    input [7:0] time_ms;
    integer cycles;
    integer i;
    begin
    //操控reg vin 
        cycles = time_ms * freq_kHz;
        vin = 0;
        for (i = 0; i < cycles; i = i + 1) begin
            vin = 1;
            #(500000/freq_kHz);
            vin = 0;
            #(500000/freq_kHz);
        end
    end
endtask



endmodule