final_version

final_version/tb/tb_diginal_top.sv

@@ -51,14 +51,20 @@ module tb_digital_top();
             begin            // --- 开始测试 ---
             #2ms;
             spi_read(25'h08, 5'h00);
-            #(CLK_PERIOD * 10);
+            #1ms;
             spi_read(25'h0c, 5'h00);
-            #(CLK_PERIOD * 10);
-            spi_write(25'h08, 5'h00, 32'h61a8);
+            #1ms;
+
+            spi_write(25'h08, 5'h00, 32'h186a0);
+            #1ms;
+            spi_read(25'h08, 5'h00);
+            #3ms;
+            spi_read(25'h0c, 5'h00);
+
             end
 
             begin
-                gen_pulses(400,5);
+                gen_pulses(400,10);
             end
         join
 

final_version/therm_rtl/therm_digital_top.v

@@ -0,0 +1,92 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2026/04/03 22:01:15
+// Design Name: 
+// Module Name: digital_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module therm_digital_top(
+    input clk,
+    input rst_n,
+    //spi_slave
+    input sclk,
+    input [4:0]cfgid,
+    input csn,
+    input mosi,
+    output miso,
+    output oen,
+    //pulse_counter
+    input sig_in
+    );
+
+wire [31:0] wrdata;      
+wire [24:0] addr;        
+wire        wren;        
+wire        rden;        
+wire  [31:0]rddata;      
+
+wire  [31:0] win_time;
+wire  cnt_vld;
+wire  [23:0]cnt_out;
+
+
+        // 实例化 DUT
+    spi_sys u_spi_sys (
+        .clk     (clk    ),
+        .rst_n   (rst_n  ),
+        .cfgid   (cfgid  ),
+        .sclk    (sclk   ),
+        .csn     (csn    ),
+        .mosi    (mosi   ),
+        .miso    (miso   ),
+        .oen     (oen    ),
+        .wrdata  (wrdata ),
+        .addr    (addr   ),
+        .wren    (wren   ),
+        .rden    (rden   ),
+        .rddata  (rddata )
+    );
+
+    system_regfile u_system_regfile (
+        .clk    (clk),
+        .rst_n  (rst_n),
+        .wrdata (wrdata),
+        .wren   (wren),
+        .rwaddr (addr),
+        .rden   (rden),
+        .rddata (rddata),
+        // digital_thermometer    
+        .win_time(win_time),
+        .pulse_cnt_out(cnt_out),
+        .pules_cnt_vld(cnt_vld)
+    );
+
+
+    pulse_cnt #(
+        .CLK_FREQ(50_000_000)
+    ) u_pulse_cnt (
+        .clk    (clk),
+        .rst_n  (rst_n),
+        .sig_in (sig_in),
+        .win_time (win_time),
+        .cnt_out(cnt_out),
+        .vld_out(cnt_vld)
+    );
+
+
+endmodule

version_manage/simple_uart_therm_digital/rtl/digital_top.v

@@ -0,0 +1,87 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2026/04/03 22:01:15
+// Design Name: 
+// Module Name: digital_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module digital_top(
+    input clk,
+    input rst_n,
+    input uart_rx,
+    output uart_tx,
+    //pulse_counter
+    input sig_in
+    );
+
+wire [31:0] wrdata;      
+wire [24:0] addr;        
+wire        wren;        
+wire        rden;        
+wire  [31:0]rddata;      
+
+wire  [31:0] win_time;
+wire  cnt_vld;
+wire  [23:0]cnt_out;
+
+
+        // 实例化 DUT
+    uart_ctrl_sysreg #(
+        .BAUD       (115200),
+        .CLOCK_FREQ (50_000_000)
+    ) u_uart_ctrl (
+        .clk        (clk),
+        .rst_n      (rst_n),
+        .uart_rx    (uart_rx),
+        .uart_tx    (uart_tx),
+        .o_wrdata   (wrdata),
+        .o_addr     (addr),
+        .o_wren     (wren),
+        .o_rden     (rden),
+        .i_rddata   (rddata)
+    );
+
+
+    system_regfile u_system_regfile (
+        .clk    (clk),
+        .rst_n  (rst_n),
+        .wrdata (wrdata),
+        .wren   (wren),
+        .rwaddr (addr),
+        .rden   (rden),
+        .rddata (rddata),
+        // digital_thermometer    
+        .win_time(win_time),
+        .pulse_cnt_out(cnt_out),
+        .pules_cnt_vld(cnt_vld)
+    );
+
+
+    pulse_cnt #(
+        .CLK_FREQ(50_000_000)
+    ) u_pulse_cnt (
+        .clk    (clk),
+        .rst_n  (rst_n),
+        .sig_in (sig_in),
+        .win_time (win_time),
+        .cnt_out(cnt_out),
+        .vld_out(cnt_vld)
+    );
+
+
+endmodule

version_manage/simple_uart_therm_digital/rtl/systemregfile/systemregfile.v

@@ -0,0 +1,111 @@
+//+FHDR--------------------------------------------------------------------------------------------------------
+// Add a new register:
+
+// SECTION A: Add localparam ADDR_NEW = 16'hXX;.
+
+// SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;.
+
+// SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);.
+
+// SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);.
+
+// SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block.
+
+// SECTION G: Map reg_new to the module's output ports.
+//-FHDR--------------------------------------------------------------------------------------------------------
+
+module system_regfile (
+    // [BLOCK 0] System and Bus Interface
+    input           clk,             
+    input           rst_n,          
+    input  [31:0]   wrdata,          
+    input           wren,            
+    input  [24:0]   rwaddr,          
+    input           rden,            
+    output [31:0]   rddata,
+
+    output [31:0] win_time,
+    input [23:0]pulse_cnt_out,
+    input pules_cnt_vld
+
+);
+
+// =============================================================================
+// [SECTION A] Address Offset Definition (Localparams)
+// =============================================================================
+ localparam TESTR      = 16'h00,   DATER     = 16'h04;
+ localparam WIN_TIME_R =16'h08 ;
+ localparam RESULT_R =16'h0c ;
+ 
+
+// =============================================================================
+// [SECTION B] Internal Wire Declaration (Wires)
+// =============================================================================
+
+// Register selection signals (Enable Wires)
+ wire sel_testr,   sel_dater;
+ wire sel_win_time, sel_result;
+
+// Write enable signals (Write Enable Wires)
+ wire we_testr, we_dater;
+ wire we_win_time;
+
+
+// Register storage wires (Storage Wires)
+ wire [31:0] testr, dater , win_time_r;
+ wire [23:0]   result_r;
+// =============================================================================
+// [SECTION C] Decoding Logic (Decoding)
+// =============================================================================
+ assign sel_testr    = (rwaddr[15:0] == TESTR );
+ assign sel_dater    = (rwaddr[15:0] == DATER );
+ assign sel_win_time = (rwaddr[15:0] == WIN_TIME_R );
+ assign sel_result   = (rwaddr[15:0] == RESULT_R );
+
+// Write enable allocation
+assign we_testr    = sel_testr    & wren;
+assign we_dater    = sel_dater    & wren;
+assign we_win_time = sel_win_time & wren;
+
+
+// =============================================================================
+// [SECTION D] Register Instantiation (Storage Implementation)
+// =============================================================================
+
+// --- General and Test Registers ---
+sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n);
+sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n);
+
+// --- Thermometer Functional Registers ---
+sirv_gnrl_dfflrd #(32) win_time_dff (32'h0000_C350, we_win_time, wrdata, win_time_r, clk, rst_n);
+
+sirv_gnrl_dfflr #(24) result_dff (pules_cnt_vld,pulse_cnt_out,result_r, clk, rst_n);
+
+// =============================================================================
+// [SECTION E] Special Business Logic (Business Logic)
+// =============================================================================
+
+// LVDS Real-time status register
+// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n);
+
+// =============================================================================
+// [SECTION F] Readback Logic (Readback Mux)
+// =============================================================================
+reg [31:0] rddata_reg;
+always @(*) begin 
+    rddata_reg = 32'b0;
+    if      (sel_testr)       rddata_reg = testr;
+    else if (sel_dater)       rddata_reg = dater;
+    else if (sel_win_time)    rddata_reg = win_time_r;
+    else if (sel_result)      rddata_reg = {8'b0,result_r};
+end
+
+ sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n);
+
+// =============================================================================
+// [SECTION G] Output Mapping (Output Assignments)
+// =============================================================================
+    assign win_time            = win_time_r;
+
+
+endmodule

version_manage/simple_uart_therm_digital/rtl/therm/pulse_cnt.v

@@ -0,0 +1,59 @@
+`timescale 1ns / 1ps
+
+module pulse_cnt #(
+    parameter CLK_FREQ = 50_000_000          
+) (
+    input  wire        clk,                  
+    input  wire        rst_n,                
+    input  wire        sig_in,               
+    input  wire [31:0] win_time,               
+    output reg  [23:0] cnt_out,             
+    output reg         vld_out               
+);
+
+
+    reg [31:0] window_cnt;      // Current clock cycle count
+    reg [31:0] target_cnt;      // Required clock cycles for current measurement window
+
+    // Pulse counter (width matches output to prevent overflow)
+    reg [23:0] pulse_cnt;
+
+ 
+
+    reg sig_sync1, sig_sync2, sig_sync3;
+    wire sig_rise = sig_sync2 & ~sig_sync3;  
+
+    always @(posedge clk) begin
+        sig_sync1 <= sig_in;
+        sig_sync2 <= sig_sync1;
+        sig_sync3 <= sig_sync2;
+    end
+
+    // Main control logic
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            window_cnt <= 0;
+            pulse_cnt  <= 0;
+            cnt_out    <= 0;
+            vld_out    <= 0;
+            target_cnt <= 24'd50_000;
+
+        end else begin
+            vld_out <= 1'b0;  
+            target_cnt <= win_time ;                 
+            // Window count end condition: current count reaches target_cnt
+            if (window_cnt >= target_cnt) begin
+                cnt_out <= pulse_cnt;
+                vld_out <= 1'b1;
+                // Reset window counter and pulse counter, trigger target value recalculation
+                window_cnt <= 0;
+                pulse_cnt  <= 0;
+            end else begin
+                window_cnt <= window_cnt + 1;
+                if (sig_rise)
+                    pulse_cnt <= pulse_cnt + 1;
+            end
+        end
+    end
+
+endmodule

version_manage/simple_uart_therm_digital/rtl/uart/uart_ctrl_sysreg.v

@@ -0,0 +1,120 @@
+`timescale 1ns / 1ps
+
+module uart_ctrl_sysreg #(
+    parameter BAUD = 115200,
+    parameter CLOCK_FREQ = 50_000_000
+)(
+     input           clk
+    ,input           rst_n
+    // UART Interface
+    ,input           uart_rx
+    ,output          uart_tx
+    // Register File Interface
+    ,output reg [31:0]   o_wrdata        //write data to register file
+    ,output reg [24:0]   o_addr          //register file address
+    ,output reg          o_wren          //write enable to register file
+    ,output reg          o_rden          //read enable to register file
+    ,input  [31:0]   i_rddata        //read data from register file
+);
+
+    // --- uart_top ---
+    wire [31:0] uart_rx_data;
+    wire        uart_rx_done;
+    reg  [31:0] uart_tx_data;
+    reg         uart_tx_go;
+    wire        uart_tx_done;
+    uart_top_32bit #(
+        .BAUD(BAUD),
+        .CLOCK_FREQ(CLOCK_FREQ)
+    ) uart_32bit_inst (
+        .Clk(clk), .Reset_n(rst_n),
+        .Send_Go32(uart_tx_go), .Tx_Data32(uart_tx_data), .Tx_Done32(uart_tx_done),
+        .uart_tx(uart_tx), .uart_rx(uart_rx),
+        .Rx_Done32(uart_rx_done), .Rx_Data32(uart_rx_data)
+    );
+
+
+    // Protocol parsing registers
+    reg [63:0] cmd_reg;
+    reg [31:0] wr_data_buff;
+    reg [19:0] data_bytes_len;    
+
+    // State machine definition
+    reg [2:0] state;
+    localparam S_IDLE      = 3'd0,
+               S_RX_CMD_L  = 3'd1,
+               S_PARSE     = 3'd2,
+               S_WAIT_RD   = 3'd3,
+               S_RD_DATA   = 3'd4,
+               S_WR_DATA   = 3'd5;
+               
+
+    always @(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            state <= 0;
+            cmd_reg <= 0;
+            o_wrdata <= 0;
+            o_wren <= 0;
+            o_rden <= 0;
+            uart_tx_go <= 1'b0;
+            uart_tx_data <= 1'b0;
+        end
+        else begin
+            case(state)
+            S_IDLE : begin  // IDLE state 0
+                uart_tx_go <= 1'b0;
+                if(uart_rx_done) begin
+                    cmd_reg[63:32] <= uart_rx_data;
+                    state <= S_RX_CMD_L;
+                end
+            end
+            S_RX_CMD_L : begin // Receive lower command word 1
+                if(uart_rx_done)begin
+                    cmd_reg[31:0] <= uart_rx_data; 
+                    state <= S_PARSE;
+                end
+            end
+            S_PARSE : begin // Parse command2
+                o_addr <= cmd_reg[56:32];
+                data_bytes_len <= cmd_reg[19:0];
+                if(cmd_reg[63] == 1'b1) begin // Read command
+                    o_rden <= 1'b1;
+                    state <= S_WAIT_RD;
+                end
+                else begin // Write command 
+                    state <= S_WR_DATA;
+                end
+            end
+            S_WAIT_RD : begin // Wait for read data ready 3
+                o_rden <= 1'b0;
+                state <= S_RD_DATA;
+            end
+            S_RD_DATA :begin // Transmit read data 4
+                uart_tx_data <= i_rddata;
+                uart_tx_go <= 1'b1;
+                state <= S_IDLE;
+            end
+            S_WR_DATA : begin // Receive and write data 5
+                o_wren <= 1'b0;
+                if(data_bytes_len != 0)begin
+                    if(uart_rx_done) begin
+                    o_wrdata <= uart_rx_data;
+                    o_wren <= 1'b1;
+                    data_bytes_len <= data_bytes_len - 20'd4;
+                    end
+                end
+                else begin
+                    state <= S_IDLE;
+                end
+            end
+
+            default: state <= S_IDLE;
+            endcase
+        end
+
+    end
+ 
+
+ 
+
+endmodule