sim correct
This commit is contained in:
parent
00e77e901a
commit
9f29575d70
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@ -112,7 +112,7 @@ module TB();
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end
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// Combine to 32-bit (little-endian)
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packet_word[24 - 8*byte_idx +: 8] = rx_byte;
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$display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte);
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// $display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte);
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// Wait for end of stop bit
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if (byte_idx < 3) begin
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#(BIT_TIME / 2);
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@ -121,7 +121,7 @@ module TB();
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// Write to file (one 32-bit data per line)
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$fdisplay(rx_file_h, "%08h", packet_word);
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$display("[%t] Packet (32-bit): 0x%08h", $time, packet_word);
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$display("[%0t] Packet (32-bit): 0x%08h", $time, packet_word);
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// Wait for end of last stop bit
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#(BIT_TIME / 2);
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end
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@ -189,28 +189,34 @@ module TB();
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#(CLK_PERIOD * 20);
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rst_n = 1;
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#(CLK_PERIOD * 100);
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$display("------- Step 1: Configure Thermometer Regs -------");
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$display("------- Step 1: read Thermometer Regs -------");
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send_data(64'h80000004_00000004,64);
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send_data(64'h80000008_00000004,64);
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send_data(64'h8000000c_00000004,64);
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send_data(64'h80000010_00000004,64);
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send_data(64'h80000014_00000004,64);
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send_data(64'h80000008_00000004,64); //mode[25:24] + win
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send_data(64'h8000000c_00000004,64); //calibration H / L
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send_data(64'h80000010_00000004,64); //rep[31] +rep_gap[23:0]
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send_data(64'h80000014_00000004,64); //result [23:0]
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$display("------- Step 2: Running Concurrent Tasks -------");
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fork
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// Process A: Generate input pulses (simulate temperature change)
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begin
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gen_pulses(400, 10); // 100kHz for 10ms
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gen_pulses(200, 10); // 100kHz for 10ms
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gen_pulses(300, 20);
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gen_pulses(400, 30);
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end
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// Process B: Insert read command during reporting
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begin
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#(2_000000); // Wait for first report packet
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$display("[%t] TX: Sending Read Request during active reporting...", $time);
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send_data(64'h80000014_00000004,64);
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send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32);
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send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);
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#(6ms); // Wait for first report packet
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send_data(64'h80000014_00000004,64); $display("[%0t] == Sending Read Request ==", $time);
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send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); $display("[%0t] == open report_en==",$time);
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send_data(64'h0000008_00000004,64);send_data(32'h0100_03e8,32); $display("[%0t] == mode = 1 ==",$time);
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#15ms;
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send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);$display("[%0t] == cloese report_en==",$time);
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//send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); $display("[%0t] == open report_en==",$time);
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//send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);$display("[%0t] == cloese report_en==",$time);
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#30000;
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send_data(64'h80000014_00000004,64);
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end
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@ -15,6 +15,8 @@ Note-[VCS_PARAL] Parallel code-gen enabled
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6 modules and 0 UDP read.
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make[1]: Entering directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \
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ld -shared -Bsymbolic -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o
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rm -f _csrc0.so
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../simv up to date
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make[1]: Leaving directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \
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@ -1,6 +1,6 @@
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// Synopsys, Inc.
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// User: shbyang
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// Date: Tue Apr 7 09:38:18 2026
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// Date: Tue Apr 7 11:12:31 2026
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// ==================================================================================================
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// This config file prototype is produced from the last run using the complete list of extracted fsms.
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.//../simv.daidir//_14790_archive_1.so
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.//../simv.daidir//_14816_archive_1.so
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.//../simv.daidir//_26119_archive_1.so
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.//../simv.daidir//_30584_archive_1.so
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.//../simv.daidir//_39120_archive_1.so
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.//../simv.daidir//_40348_archive_1.so
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.//../simv.daidir//_41494_archive_1.so
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.//../simv.daidir//_43406_archive_1.so
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.//../simv.daidir//_43443_archive_1.so
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.//../simv.daidir//_45855_archive_1.so
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.//../simv.daidir//_50099_archive_1.so
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.//../simv.daidir//_50120_archive_1.so
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.//../simv.daidir//_57264_archive_1.so
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.//../simv.daidir//_csrc0.so
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.//../simv.daidir//_prev_archive_1.so
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@ -0,0 +1,462 @@
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{
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"cpu_cycles_pass2_start": 4041504101117290,
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"Misc": {
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"vcs_version": "O-2018.09-SP2_Full64",
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"master_pid": 56094,
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"csrc": "csrc",
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"vcs_build_date": "Build Date = Feb 28 2019 22:34:30",
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"VCS_HOME": "/opt/synopsys/vcs-mx/O-2018.09-SP2",
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"hostname": "cryo1",
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"archive_dir": "archive.16",
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"csrc_abs": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc",
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"cwd": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top",
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"daidir": "simv.daidir",
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"default_output_dir": "csrc",
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"daidir_abs": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir"
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},
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"cycles_program_begin": 4041503055448976,
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||||
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||||
|
|
@ -177,15 +249,15 @@
|
|||
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||||
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|
|
@ -195,15 +267,15 @@
|
|||
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|
@ -211,30 +283,30 @@
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|
|
@ -242,15 +314,15 @@
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|||
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|
@ -260,15 +332,15 @@
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"nMops": 192
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||||
}
|
||||
},
|
||||
"ObjArchives": [
|
||||
{
|
||||
"archive": "archive.17/_57246_archive_1.a",
|
||||
"objects": [
|
||||
[
|
||||
"amcQwB.o",
|
||||
129528
|
||||
]
|
||||
],
|
||||
"size": 129528
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||||
}
|
||||
],
|
||||
"stat": {
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||||
"ru_self_end": {
|
||||
"ru_utime_sec": 0.16919500000000001,
|
||||
"ru_stime_sec": 0.085615999999999998,
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||||
"ru_maxrss_kb": 84144,
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||||
"ru_nvcsw": 56,
|
||||
"ru_minflt": 30439,
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||||
"ru_nivcsw": 8,
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||||
"ru_majflt": 0
|
||||
},
|
||||
"ru_childs_end": {
|
||||
"ru_utime_sec": 0.13755500000000001,
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||||
"ru_stime_sec": 0.092283000000000004,
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||||
"ru_maxrss_kb": 43496,
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||||
"ru_nvcsw": 62,
|
||||
"ru_minflt": 21284,
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||||
"ru_nivcsw": 26,
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||||
"ru_majflt": 0
|
||||
},
|
||||
"cpu_cycles_end": 4041682813998046,
|
||||
"peak_mem_kb": 296992
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
{
|
||||
"reusePaths": {},
|
||||
"CompUnits": {
|
||||
"sH4Fc_d": {
|
||||
"mod": "TB",
|
||||
"text": 63094,
|
||||
"out": "sH4Fc_d.o",
|
||||
"checksum": 0,
|
||||
"bytes": 134118,
|
||||
"mode": 4,
|
||||
"archive": "archive.17/_57264_archive_1.a"
|
||||
}
|
||||
},
|
||||
"Modules": {
|
||||
"TB": {
|
||||
"start_perf": [
|
||||
0.387908935546875,
|
||||
0.0,
|
||||
0.00077800000000000005,
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285092,
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285092,
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1775531551.860244,
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4041682496390018
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],
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"child_modules": {
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"sirv_gnrl_dfflrd": 5
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},
|
||||
"nQuads": 8636,
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"significant_routs": [
|
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[
|
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133,
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"R_VCSgd_sH4Fc_85",
|
||||
6325624,
|
||||
4651,
|
||||
1078
|
||||
]
|
||||
],
|
||||
"Compiled": "Yes",
|
||||
"Compiled Times": 18,
|
||||
"end_perf": [
|
||||
0.48143482208251953,
|
||||
0.087273000000000003,
|
||||
0.0070219999999999996,
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||||
292828,
|
||||
294880,
|
||||
4041682739157474,
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||||
77309411329,
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||||
0
|
||||
],
|
||||
"nMops": 20350,
|
||||
"nRouts": 472
|
||||
}
|
||||
},
|
||||
"ObjArchives": [
|
||||
{
|
||||
"archive": "archive.17/_57264_archive_1.a",
|
||||
"objects": [
|
||||
[
|
||||
"sH4Fc_d.o",
|
||||
134118
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||||
]
|
||||
],
|
||||
"size": 134118
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||||
}
|
||||
],
|
||||
"stat": {
|
||||
"ru_self_end": {
|
||||
"ru_utime_sec": 0.087467000000000003,
|
||||
"ru_stime_sec": 0.0070369999999999999,
|
||||
"ru_maxrss_kb": 39924,
|
||||
"ru_nvcsw": 1,
|
||||
"ru_minflt": 4639,
|
||||
"ru_nivcsw": 0,
|
||||
"ru_majflt": 0
|
||||
},
|
||||
"ru_childs_end": {
|
||||
"ru_utime_sec": 0.0,
|
||||
"ru_stime_sec": 0.0,
|
||||
"ru_maxrss_kb": 0,
|
||||
"ru_nvcsw": 0,
|
||||
"ru_minflt": 0,
|
||||
"ru_nivcsw": 0,
|
||||
"ru_majflt": 0
|
||||
},
|
||||
"cpu_cycles_end": 4041682739634416,
|
||||
"peak_mem_kb": 294880
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
{
|
||||
"reusePaths": {
|
||||
"reYIK_d": {
|
||||
"icPath": "csrc"
|
||||
}
|
||||
},
|
||||
"CompUnits": {},
|
||||
"Modules": {
|
||||
"std": {
|
||||
"start_perf": [
|
||||
0.38861989974975586,
|
||||
0.000638,
|
||||
0.0,
|
||||
285092,
|
||||
285092,
|
||||
1775531551.860955,
|
||||
4041682498268042
|
||||
],
|
||||
"child_modules": {},
|
||||
"nQuads": 224,
|
||||
"nRouts": 36,
|
||||
"svclass": [
|
||||
"$vcs_nba_dyn_obj",
|
||||
0,
|
||||
37,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"sigprop$$",
|
||||
0,
|
||||
37,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"process",
|
||||
0,
|
||||
184,
|
||||
8,
|
||||
8,
|
||||
0,
|
||||
"event",
|
||||
0,
|
||||
36,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"mailbox",
|
||||
0,
|
||||
107,
|
||||
9,
|
||||
9,
|
||||
0,
|
||||
"semaphore",
|
||||
0,
|
||||
71,
|
||||
5,
|
||||
5,
|
||||
0
|
||||
],
|
||||
"Compiled": "Yes",
|
||||
"Compiled Times": 18,
|
||||
"end_perf": [
|
||||
0.39862990379333496,
|
||||
0.003192,
|
||||
0.0074479999999999998,
|
||||
285112,
|
||||
285112,
|
||||
4041682523850886,
|
||||
8589934594,
|
||||
0
|
||||
],
|
||||
"nMops": 477
|
||||
}
|
||||
},
|
||||
"ObjArchives": [],
|
||||
"stat": {
|
||||
"ru_self_end": {
|
||||
"ru_utime_sec": 0.0032360000000000002,
|
||||
"ru_stime_sec": 0.0075510000000000004,
|
||||
"ru_maxrss_kb": 31568,
|
||||
"ru_nvcsw": 1,
|
||||
"ru_minflt": 1875,
|
||||
"ru_nivcsw": 0,
|
||||
"ru_majflt": 0
|
||||
},
|
||||
"ru_childs_end": {
|
||||
"ru_utime_sec": 0.0,
|
||||
"ru_stime_sec": 0.0,
|
||||
"ru_maxrss_kb": 0,
|
||||
"ru_nvcsw": 0,
|
||||
"ru_minflt": 0,
|
||||
"ru_nivcsw": 0,
|
||||
"ru_majflt": 0
|
||||
},
|
||||
"cpu_cycles_end": 4041682524207970,
|
||||
"peak_mem_kb": 285116
|
||||
}
|
||||
}
|
||||
|
|
@ -1,31 +1,34 @@
|
|||
PIC_LD=ld
|
||||
|
||||
ARCHIVE_OBJS=
|
||||
ARCHIVE_OBJS += _131020_archive_1.so
|
||||
_131020_archive_1.so : archive.0/_131020_archive_1.a
|
||||
ARCHIVE_OBJS += _57246_archive_1.so
|
||||
_57246_archive_1.so : archive.17/_57246_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131020_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_57246_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_131020_archive_1.so $@
|
||||
@ln -sf .//../simv.daidir//_57246_archive_1.so $@
|
||||
|
||||
|
||||
ARCHIVE_OBJS += _131039_archive_1.so
|
||||
_131039_archive_1.so : archive.0/_131039_archive_1.a
|
||||
ARCHIVE_OBJS += _57264_archive_1.so
|
||||
_57264_archive_1.so : archive.17/_57264_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131039_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_57264_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_131039_archive_1.so $@
|
||||
@ln -sf .//../simv.daidir//_57264_archive_1.so $@
|
||||
|
||||
|
||||
ARCHIVE_OBJS += _131040_archive_1.so
|
||||
_131040_archive_1.so : archive.0/_131040_archive_1.a
|
||||
ARCHIVE_OBJS += _prev_archive_1.so
|
||||
_prev_archive_1.so : archive.17/_prev_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131040_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_131040_archive_1.so $@
|
||||
@ln -sf .//../simv.daidir//_prev_archive_1.so $@
|
||||
|
||||
|
||||
|
||||
VCS_ARC0 =_csrc0.so
|
||||
|
||||
VCS_OBJS0 =objs/amcQw_d.o
|
||||
|
||||
|
||||
O0_OBJS =
|
||||
|
|
@ -36,6 +39,12 @@ $(O0_OBJS) : %.o: %.c
|
|||
|
||||
%.o: %.c
|
||||
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
|
||||
|
||||
$(VCS_ARC0) : $(VCS_OBJS0)
|
||||
$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0)
|
||||
rm -f $(VCS_ARC0)
|
||||
@ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0)
|
||||
|
||||
CU_UDP_OBJS = \
|
||||
|
||||
|
||||
|
|
@ -43,7 +52,7 @@ CU_LVL_OBJS = \
|
|||
SIM_l.o
|
||||
|
||||
MAIN_OBJS = \
|
||||
objs/amcQw_d.o
|
||||
|
||||
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
|
||||
|
||||
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
|
||||
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
File diff suppressed because one or more lines are too long
|
|
@ -113,6 +113,7 @@ Branch = 1
|
|||
IfShowModule = {TRUE, FALSE}
|
||||
[DisabledMessages]
|
||||
version = Verdi_O-2018.09-SP2
|
||||
184615126 = disabled
|
||||
[Editor]
|
||||
editorName = TurboEditor
|
||||
[Emacs]
|
||||
|
|
@ -370,8 +371,9 @@ saveWaveformStat = TRUE
|
|||
savePropStat = FALSE
|
||||
savePropDtl = TRUE
|
||||
[QtDialog]
|
||||
QwWarnMsgDlg = 650,407,600,250
|
||||
QwUserAskDlg = 809,434,324,134
|
||||
QwWarnMsgDlg = 650,444,600,250
|
||||
QwUserAskDlg = 798,524,324,134
|
||||
SetWindowTimeUnitDialog = 742,466,433,86
|
||||
[Relationship]
|
||||
hideRecursiceNode = FALSE
|
||||
[Session Cache]
|
||||
|
|
@ -558,7 +560,7 @@ pdmlMacro = ID_BLACK
|
|||
font = COURIER12
|
||||
annotFont = Helvetica_M_R_10
|
||||
[Text.1]
|
||||
viewport = 453 103 1017 706 45
|
||||
viewport = 239 111 1440 723 45
|
||||
[TextPrinter]
|
||||
Orientation = Landscape
|
||||
Indicator = FALSE
|
||||
|
|
@ -648,9 +650,9 @@ DefaultLogTimeUnit = "1.000000ns"
|
|||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0]
|
||||
parRuleSets = ""
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0]
|
||||
name = Severity
|
||||
name = Time
|
||||
width = 60
|
||||
visualIndex = 1
|
||||
visualIndex = 0
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1]
|
||||
|
|
@ -672,9 +674,9 @@ visualIndex = 3
|
|||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4]
|
||||
name = Time
|
||||
name = Severity
|
||||
width = 60
|
||||
visualIndex = 0
|
||||
visualIndex = 1
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[Vi]
|
||||
|
|
@ -696,7 +698,7 @@ scope_to_save_with_macro
|
|||
open_file_dir
|
||||
open_rc_file_dir
|
||||
getSignalForm = 0 0 800 479 100 30 100 30
|
||||
viewPort = 0 27 1017 282 100 65
|
||||
viewPort = 0 27 1440 265 143 65
|
||||
signalSpacing = 5
|
||||
digitalSignalHeight = 15
|
||||
analogSignalHeight = 98
|
||||
|
|
@ -1293,7 +1295,7 @@ AddImportArgument = FALSE
|
|||
LineBreakWithScope = TRUE
|
||||
StopAfterCompileOption = -s
|
||||
[wave.0]
|
||||
viewPort = 0 27 1017 282 100 65
|
||||
viewPort = 0 27 1440 265 143 65
|
||||
[wave.1]
|
||||
viewPort = 127 219 960 332 100 65
|
||||
[wave.2]
|
||||
|
|
|
|||
|
|
@ -187,7 +187,7 @@ XDG_MENU_PREFIX=gnome-
|
|||
VTE_VERSION=5204
|
||||
SHELL=/bin/csh
|
||||
MAKEFLAGS=
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/33c4f0fe_b1af_4925_918d_f401e6285844
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/c54e5016_f7fb_4a73_ae57_77787103df43
|
||||
SPECTRE_HOME=/opt/cadence/SPECTRE181
|
||||
VIVADO_HOME=/opt/xilinx/Vivado/2019.2/
|
||||
CDS_LOAD_ENV=CWD
|
||||
|
|
@ -290,8 +290,8 @@ argv[0]=./simv
|
|||
argv[1]=sync:busywait
|
||||
argv[2]=-l
|
||||
291 profile - 100
|
||||
CPU/Mem usage: 0.050 sys, 0.220 user, 282.41M mem
|
||||
292 Tue Apr 7 09:38:20 2026
|
||||
CPU/Mem usage: 0.050 sys, 0.210 user, 284.52M mem
|
||||
292 Tue Apr 7 11:12:33 2026
|
||||
293 pliAppInit
|
||||
294 FSDB_GATE is set.
|
||||
295 FSDB_RTL is set.
|
||||
|
|
@ -303,45 +303,46 @@ argv[2]=-l
|
|||
301 (C) 1996 - 2019 by Synopsys, Inc.
|
||||
302 sps_call_fsdbDumpfile_main at 0 : ./TB.sv(22)
|
||||
303 argv[0]: (wave.fsdb)
|
||||
304 *Verdi* : Create FSDB file 'wave.fsdb'
|
||||
305 compile option from '/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/vcs_rebuild'.
|
||||
306 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1"
|
||||
307 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
308 sps_call_fsdbDumpvars_vd_main at 0 : ./TB.sv(23)
|
||||
309 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
310 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
311 *Verdi* : Begin traversing the scopes, layer (0).
|
||||
312 *Verdi* : End of traversing.
|
||||
313 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.080 sys, 0.230 user, 378.79M mem
|
||||
incr: 0.000 sys, 0.010 user, 8.98M mem
|
||||
accu: 0.000 sys, 0.010 user, 8.98M mem
|
||||
accu incr: 0.000 sys, 0.010 user, 8.98M mem
|
||||
304 *Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
|
||||
305 *Verdi* : Create FSDB file 'wave.fsdb'
|
||||
306 compile option from '/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/vcs_rebuild'.
|
||||
307 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1"
|
||||
308 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
309 sps_call_fsdbDumpvars_vd_main at 0 : ./TB.sv(23)
|
||||
310 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
311 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
312 *Verdi* : Begin traversing the scopes, layer (0).
|
||||
313 *Verdi* : End of traversing.
|
||||
314 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.090 sys, 0.220 user, 380.92M mem
|
||||
incr: 0.010 sys, 0.000 user, 8.86M mem
|
||||
accu: 0.010 sys, 0.000 user, 8.86M mem
|
||||
accu incr: 0.010 sys, 0.000 user, 8.86M mem
|
||||
|
||||
Count usage: 224 var, 123 idcode, 86 callback
|
||||
incr: 224 var, 123 idcode, 86 callback
|
||||
accu: 224 var, 123 idcode, 86 callback
|
||||
accu incr: 224 var, 123 idcode, 86 callback
|
||||
314 Tue Apr 7 09:38:20 2026
|
||||
315 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.080 sys, 0.230 user, 379.84M mem
|
||||
Count usage: 223 var, 122 idcode, 85 callback
|
||||
incr: 223 var, 122 idcode, 85 callback
|
||||
accu: 223 var, 122 idcode, 85 callback
|
||||
accu incr: 223 var, 122 idcode, 85 callback
|
||||
315 Tue Apr 7 11:12:33 2026
|
||||
316 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.090 sys, 0.220 user, 381.97M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu: 0.000 sys, 0.010 user, 10.04M mem
|
||||
accu: 0.010 sys, 0.000 user, 9.92M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
|
||||
Count usage: 224 var, 123 idcode, 86 callback
|
||||
Count usage: 223 var, 122 idcode, 85 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 224 var, 123 idcode, 86 callback
|
||||
accu: 223 var, 122 idcode, 85 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
316 Tue Apr 7 09:38:20 2026
|
||||
317 End of simulation at 17814400000
|
||||
318 Tue Apr 7 09:38:21 2026
|
||||
319 Begin FSDB profile info:
|
||||
320 FSDB Writer : bc1(1815118) bcn(1365370) mtf/stf(0/1)
|
||||
FSDB Writer elapsed time : flush(0.171826) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
317 Tue Apr 7 11:12:33 2026
|
||||
318 End of simulation at 67816396000
|
||||
319 Tue Apr 7 11:12:36 2026
|
||||
320 Begin FSDB profile info:
|
||||
321 FSDB Writer : bc1(6944429) bcn(4210234) mtf/stf(0/2)
|
||||
FSDB Writer elapsed time : flush(0.508682) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
FSDB Writer cpu time : MT Compression : 0
|
||||
321 End FSDB profile info
|
||||
322 Parallel profile - Flush:3 Expand:0 ProduceWait:0 ConsumerWait:27 BlockUsed:34
|
||||
323 ProduceTime:1.172810727 ConsumerTime:0.465192911 Buffer:64MB
|
||||
324 SimExit
|
||||
325 Sim process exit
|
||||
322 End FSDB profile info
|
||||
323 Parallel profile - Flush:3 Expand:0 ProduceWait:0 ConsumerWait:116 BlockUsed:122
|
||||
324 ProduceTime:2.819906888 ConsumerTime:1.842929702 Buffer:64MB
|
||||
325 SimExit
|
||||
326 Sim process exit
|
||||
|
|
|
|||
|
|
@ -3,6 +3,22 @@
|
|||
025800a0
|
||||
0000c350
|
||||
00fff060
|
||||
00000b02
|
||||
aa000b02
|
||||
00000b02
|
||||
00fff4d0
|
||||
aafff4d0
|
||||
aa0000c8
|
||||
aa0000fc
|
||||
aa00012d
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012d
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012c
|
||||
aa00012c
|
||||
0000012c
|
||||
|
|
|
|||
|
|
@ -1,61 +1,51 @@
|
|||
Chronologic VCS simulator copyright 1991-2018
|
||||
Contains Synopsys proprietary information.
|
||||
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Apr 7 09:38 2026
|
||||
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Apr 7 11:12 2026
|
||||
*Verdi* Loading libsscore_vcs201809.so
|
||||
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
(C) 1996 - 2019 by Synopsys, Inc.
|
||||
*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
|
||||
*Verdi* : Create FSDB file 'wave.fsdb'
|
||||
*Verdi* : Begin traversing the scopes, layer (0).
|
||||
*Verdi* : End of traversing.
|
||||
------- Step 1: Configure Thermometer Regs -------
|
||||
[ 775170000] Byte 0: 0x20
|
||||
[ 862030000] Byte 1: 0x26
|
||||
[ 948890000] Byte 2: 0x04
|
||||
[ 1035750000] Byte 3: 0x06
|
||||
------- Step 1: read Thermometer Regs -------
|
||||
[1035750000] Packet (32-bit): 0x20260406
|
||||
[ 1469570000] Byte 0: 0x00
|
||||
[ 1556430000] Byte 1: 0x00
|
||||
[ 1643290000] Byte 2: 0x03
|
||||
[ 1730150000] Byte 3: 0xe8
|
||||
[1730150000] Packet (32-bit): 0x000003e8
|
||||
[ 2163970000] Byte 0: 0x02
|
||||
[ 2250830000] Byte 1: 0x58
|
||||
[ 2337690000] Byte 2: 0x00
|
||||
[ 2424550000] Byte 3: 0xa0
|
||||
[2424550000] Packet (32-bit): 0x025800a0
|
||||
[ 2858370000] Byte 0: 0x00
|
||||
[ 2945230000] Byte 1: 0x00
|
||||
[ 3032090000] Byte 2: 0xc3
|
||||
[ 3118950000] Byte 3: 0x50
|
||||
[3118950000] Packet (32-bit): 0x0000c350
|
||||
------- Step 2: Running Concurrent Tasks -------
|
||||
[3474400000] Start generating signal: 400 kHz
|
||||
[ 3552770000] Byte 0: 0x00
|
||||
[ 3639630000] Byte 1: 0xff
|
||||
[ 3726490000] Byte 2: 0xf0
|
||||
[ 3813350000] Byte 3: 0x60
|
||||
[3474400000] Start generating signal: 200 kHz
|
||||
[3813350000] Packet (32-bit): 0x00fff060
|
||||
[ 5474400000] TX: Sending Read Request during active reporting...
|
||||
[ 6247170000] Byte 0: 0x00
|
||||
[ 6334030000] Byte 1: 0x00
|
||||
[ 6420890000] Byte 2: 0x0b
|
||||
[ 6507750000] Byte 3: 0x02
|
||||
[ 6507750000] Packet (32-bit): 0x00000b02
|
||||
[ 8330370000] Byte 0: 0xaa
|
||||
[ 8417230000] Byte 1: 0x00
|
||||
[ 8504090000] Byte 2: 0x0b
|
||||
[ 8590950000] Byte 3: 0x02
|
||||
[ 8590950000] Packet (32-bit): 0xaa000b02
|
||||
[ 9054770000] Byte 0: 0x00
|
||||
[ 9141630000] Byte 1: 0x00
|
||||
[ 9228490000] Byte 2: 0x0b
|
||||
[ 9315350000] Byte 3: 0x02
|
||||
[ 9315350000] Packet (32-bit): 0x00000b02
|
||||
[10168800000] == Sending Read Request ==
|
||||
[10507750000] Packet (32-bit): 0x00fff4d0
|
||||
[11210400000] == open report_en==
|
||||
[12252000000] == mode = 1 ==
|
||||
[12590950000] Packet (32-bit): 0xaafff4d0
|
||||
[13343850000] Packet (32-bit): 0xaa0000c8
|
||||
[13474400000] Start generating signal: 300 kHz
|
||||
[14343870000] Packet (32-bit): 0xaa0000fc
|
||||
[15343890000] Packet (32-bit): 0xaa00012d
|
||||
[16343910000] Packet (32-bit): 0xaa00012c
|
||||
[17343930000] Packet (32-bit): 0xaa00012c
|
||||
[18343950000] Packet (32-bit): 0xaa00012c
|
||||
[19343970000] Packet (32-bit): 0xaa00012c
|
||||
[20343990000] Packet (32-bit): 0xaa00012c
|
||||
[21344010000] Packet (32-bit): 0xaa00012c
|
||||
[22344030000] Packet (32-bit): 0xaa00012c
|
||||
[23344050000] Packet (32-bit): 0xaa00012d
|
||||
[24344070000] Packet (32-bit): 0xaa00012c
|
||||
[25344090000] Packet (32-bit): 0xaa00012c
|
||||
[26344110000] Packet (32-bit): 0xaa00012c
|
||||
[27344130000] Packet (32-bit): 0xaa00012c
|
||||
[28293600000] == cloese report_en==
|
||||
[28632550000] Packet (32-bit): 0xaa00012c
|
||||
[29356950000] Packet (32-bit): 0x0000012c
|
||||
[33476396000] Start generating signal: 400 kHz
|
||||
Test Done.
|
||||
$finish called from file "./TB.sv", line 221.
|
||||
[RX] File closed at 17814400000
|
||||
$finish at simulation time 17814400000
|
||||
$finish called from file "./TB.sv", line 227.
|
||||
[RX] File closed at 67816396000
|
||||
$finish at simulation time 67816396000
|
||||
V C S S i m u l a t i o n R e p o r t
|
||||
Time: 17814400000 ps
|
||||
CPU Time: 1.630 seconds; Data structure size: 0.0Mb
|
||||
Tue Apr 7 09:38:21 2026
|
||||
Time: 67816396000 ps
|
||||
CPU Time: 4.650 seconds; Data structure size: 0.0Mb
|
||||
Tue Apr 7 11:12:36 2026
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -118,7 +118,7 @@ HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2
|
|||
HOSTTYPE=x86_64-linux
|
||||
GROUP=cryo
|
||||
GNOME_TERMINAL_SERVICE=:1.2258
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/33c4f0fe_b1af_4925_918d_f401e6285844
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/c54e5016_f7fb_4a73_ae57_77787103df43
|
||||
GNOME_SHELL_SESSION_MODE=classic
|
||||
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
|
||||
GENUS_HOME=/opt/cadence/GENUS152
|
||||
|
|
@ -149,12 +149,12 @@ CADENCE_DIR=/opt/cadence/IC618
|
|||
AMS_ENABLE_NOISE=YES
|
||||
0
|
||||
14
|
||||
1775464866 ./TB.sv
|
||||
1775377742 ../../rtl/therm/pulse_cnt.v
|
||||
1775454778 ../../rtl/therm/digital_thermometer.v
|
||||
1775531547 ./TB.sv
|
||||
1775526351 ../../rtl/therm/pulse_cnt.v
|
||||
1775526160 ../../rtl/therm/digital_thermometer.v
|
||||
1774925224 ../../rtl/uart/uart_byte_tx.v
|
||||
1775370228 ../../rtl/uart/uart_top_32bit.v
|
||||
1775459928 ../../rtl/uart/uart_ctrl_sysreg.v
|
||||
1775526524 ../../rtl/uart/uart_top_32bit.v
|
||||
1775526452 ../../rtl/uart/uart_ctrl_sysreg.v
|
||||
1774924538 ../../rtl/uart/uart_byte_rx.v
|
||||
1775525487 ../../rtl/digital_top.v
|
||||
1774930574 ../../rtl/systemregfile/sirv_gnrl_dffs.v
|
||||
|
|
@ -168,5 +168,5 @@ AMS_ENABLE_NOISE=YES
|
|||
1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so
|
||||
1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so
|
||||
1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so
|
||||
1775525900 simv.daidir
|
||||
1775531552 simv.daidir
|
||||
-1 partitionlib
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -5,11 +5,11 @@
|
|||
"module",
|
||||
7
|
||||
],
|
||||
"sirv_gnrl_dffl": [
|
||||
"sirv_gnrl_dffl",
|
||||
"BM4bj",
|
||||
"sirv_gnrl_dfflrs": [
|
||||
"sirv_gnrl_dfflrs",
|
||||
"ZJgwY",
|
||||
"module",
|
||||
4
|
||||
2
|
||||
],
|
||||
"std": [
|
||||
"std",
|
||||
|
|
@ -17,17 +17,11 @@
|
|||
"module",
|
||||
1
|
||||
],
|
||||
"sirv_gnrl_dffrs": [
|
||||
"sirv_gnrl_dffrs",
|
||||
"QHiet",
|
||||
"sirv_gnrl_ltch": [
|
||||
"sirv_gnrl_ltch",
|
||||
"UTi0b",
|
||||
"module",
|
||||
5
|
||||
],
|
||||
"sirv_gnrl_dfflrs": [
|
||||
"sirv_gnrl_dfflrs",
|
||||
"ZJgwY",
|
||||
"module",
|
||||
2
|
||||
6
|
||||
],
|
||||
"sirv_gnrl_dfflrd": [
|
||||
"sirv_gnrl_dfflrd",
|
||||
|
|
@ -35,16 +29,22 @@
|
|||
"module",
|
||||
3
|
||||
],
|
||||
"sirv_gnrl_ltch": [
|
||||
"sirv_gnrl_ltch",
|
||||
"UTi0b",
|
||||
"module",
|
||||
6
|
||||
],
|
||||
"...MASTER...": [
|
||||
"SIM",
|
||||
"amcQw",
|
||||
"module",
|
||||
8
|
||||
],
|
||||
"sirv_gnrl_dffl": [
|
||||
"sirv_gnrl_dffl",
|
||||
"BM4bj",
|
||||
"module",
|
||||
4
|
||||
],
|
||||
"sirv_gnrl_dffrs": [
|
||||
"sirv_gnrl_dffrs",
|
||||
"QHiet",
|
||||
"module",
|
||||
5
|
||||
]
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -5,5 +5,5 @@ PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27
|
|||
export PYTHONPATH
|
||||
LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27
|
||||
export LD_LIBRARY_PATH
|
||||
/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_ik1qVk.xml.gz" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_DBCEI2.xml.gz" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
\mv "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db"
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1 +1 @@
|
|||
<06>l<EFBFBD><13>c<EFBFBD><08>}
|
||||
<06>k<EFBFBD><12>b<EFBFBD><08>|
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
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Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue