yangshenbo
/
thermometer_digital
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sim correct

This commit is contained in:
yangshenbo 2026-04-07 11:15:51 +08:00
parent 00e77e901a
commit 9f29575d70
178 changed files with 2146 additions and 1026 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
sim/therm_chip_top/TB.sv
View File

@ -112,7 +112,7 @@ module TB();
end end
// Combine to 32-bit (little-endian) // Combine to 32-bit (little-endian)
packet_word[24 - 8*byte_idx +: 8] = rx_byte; packet_word[24 - 8*byte_idx +: 8] = rx_byte;
$display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte); // $display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte);
// Wait for end of stop bit // Wait for end of stop bit
if (byte_idx < 3) begin if (byte_idx < 3) begin
#(BIT_TIME / 2); #(BIT_TIME / 2);
@ -121,7 +121,7 @@ module TB();
// Write to file (one 32-bit data per line) // Write to file (one 32-bit data per line)
$fdisplay(rx_file_h, "%08h", packet_word); $fdisplay(rx_file_h, "%08h", packet_word);
$display("[%t] Packet (32-bit): 0x%08h", $time, packet_word); $display("[%0t] Packet (32-bit): 0x%08h", $time, packet_word);
// Wait for end of last stop bit // Wait for end of last stop bit
#(BIT_TIME / 2); #(BIT_TIME / 2);
end end
@ -189,28 +189,34 @@ module TB();
#(CLK_PERIOD * 20); #(CLK_PERIOD * 20);
rst_n = 1; rst_n = 1;
#(CLK_PERIOD * 100); #(CLK_PERIOD * 100);
$display("------- Step 1: Configure Thermometer Regs -------"); $display("------- Step 1: read Thermometer Regs -------");
send_data(64'h80000004_00000004,64); send_data(64'h80000004_00000004,64);
send_data(64'h80000008_00000004,64); send_data(64'h80000008_00000004,64); //mode[25:24] + win
send_data(64'h8000000c_00000004,64); send_data(64'h8000000c_00000004,64); //calibration H / L
send_data(64'h80000010_00000004,64); send_data(64'h80000010_00000004,64); //rep[31] +rep_gap[23:0]
send_data(64'h80000014_00000004,64); send_data(64'h80000014_00000004,64); //result [23:0]
$display("------- Step 2: Running Concurrent Tasks -------"); $display("------- Step 2: Running Concurrent Tasks -------");
fork fork
// Process A: Generate input pulses (simulate temperature change) // Process A: Generate input pulses (simulate temperature change)
begin begin
gen_pulses(400, 10); // 100kHz for 10ms gen_pulses(200, 10); // 100kHz for 10ms
gen_pulses(300, 20);
gen_pulses(400, 30);
end end
// Process B: Insert read command during reporting // Process B: Insert read command during reporting
begin begin
#(2_000000); // Wait for first report packet #(6ms); // Wait for first report packet
$display("[%t] TX: Sending Read Request during active reporting...", $time); send_data(64'h80000014_00000004,64); $display("[%0t] == Sending Read Request ==", $time);
send_data(64'h80000014_00000004,64); send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); $display("[%0t] == open report_en==",$time);
send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); send_data(64'h0000008_00000004,64);send_data(32'h0100_03e8,32); $display("[%0t] == mode = 1 ==",$time);
send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32); #15ms;
send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);$display("[%0t] == cloese report_en==",$time);
//send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); $display("[%0t] == open report_en==",$time);
//send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);$display("[%0t] == cloese report_en==",$time);
#30000; #30000;
send_data(64'h80000014_00000004,64); send_data(64'h80000014_00000004,64);
end end

2
sim/therm_chip_top/compile.log
View File

@ -15,6 +15,8 @@ Note-[VCS_PARAL] Parallel code-gen enabled
6 modules and 0 UDP read. 6 modules and 0 UDP read.
make[1]: Entering directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \ make[1]: Entering directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \
ld -shared -Bsymbolic -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o
rm -f _csrc0.so
../simv up to date ../simv up to date
make[1]: Leaving directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \ make[1]: Leaving directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \

BIN
sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml
View File

Binary file not shown.

BIN
sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml
View File

Binary file not shown.

BIN
sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml
View File

Binary file not shown.

2
sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt
View File

@ -1,6 +1,6 @@
// Synopsys, Inc. // Synopsys, Inc.
// User: shbyang // User: shbyang
// Date: Tue Apr 7 09:38:18 2026 // Date: Tue Apr 7 11:12:31 2026
// ================================================================================================== // ==================================================================================================
// This config file prototype is produced from the last run using the complete list of extracted fsms. // This config file prototype is produced from the last run using the complete list of extracted fsms.

BIN
sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml
View File

Binary file not shown.

BIN
sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml
View File

Binary file not shown.

1
sim/therm_chip_top/csrc/_14790_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_14790_archive_1.so

1
sim/therm_chip_top/csrc/_14816_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_14816_archive_1.so

1
sim/therm_chip_top/csrc/_26119_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_26119_archive_1.so

1
sim/therm_chip_top/csrc/_30584_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_30584_archive_1.so

1
sim/therm_chip_top/csrc/_30603_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_30603_archive_1.so

1
sim/therm_chip_top/csrc/_34047_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_34047_archive_1.so

1
sim/therm_chip_top/csrc/_34065_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_34065_archive_1.so

1
sim/therm_chip_top/csrc/_37423_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_37423_archive_1.so

1
sim/therm_chip_top/csrc/_37441_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_37441_archive_1.so

1
sim/therm_chip_top/csrc/_39101_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_39101_archive_1.so

1
sim/therm_chip_top/csrc/_39120_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_39120_archive_1.so

1
sim/therm_chip_top/csrc/_40330_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_40330_archive_1.so

1
sim/therm_chip_top/csrc/_40348_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_40348_archive_1.so

1
sim/therm_chip_top/csrc/_41475_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_41475_archive_1.so

1
sim/therm_chip_top/csrc/_41494_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_41494_archive_1.so

1
sim/therm_chip_top/csrc/_42301_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_42301_archive_1.so

1
sim/therm_chip_top/csrc/_42320_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_42320_archive_1.so

1
sim/therm_chip_top/csrc/_43406_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_43406_archive_1.so

1
sim/therm_chip_top/csrc/_43443_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_43443_archive_1.so

1
sim/therm_chip_top/csrc/_45855_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_45855_archive_1.so

1
sim/therm_chip_top/csrc/_45891_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_45891_archive_1.so

1
sim/therm_chip_top/csrc/_50099_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_50099_archive_1.so

1
sim/therm_chip_top/csrc/_50120_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_50120_archive_1.so

1
sim/therm_chip_top/csrc/_52045_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_52045_archive_1.so

1
sim/therm_chip_top/csrc/_52081_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_52081_archive_1.so

1
sim/therm_chip_top/csrc/_53444_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_53444_archive_1.so

1
sim/therm_chip_top/csrc/_53462_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_53462_archive_1.so

1
sim/therm_chip_top/csrc/_54606_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_54606_archive_1.so

1
sim/therm_chip_top/csrc/_54624_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_54624_archive_1.so

1
sim/therm_chip_top/csrc/_56094_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_56094_archive_1.so

1
sim/therm_chip_top/csrc/_56112_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_56112_archive_1.so

1
sim/therm_chip_top/csrc/_57246_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_57246_archive_1.so

1
sim/therm_chip_top/csrc/_57264_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_57264_archive_1.so

1
sim/therm_chip_top/csrc/_csrc0.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_csrc0.so

1
sim/therm_chip_top/csrc/_prev_archive_1.so Symbolic link
View File

@ -0,0 +1 @@
.//../simv.daidir//_prev_archive_1.so

462
sim/therm_chip_top/csrc/_prev_cginfo.json Normal file
View File

@ -0,0 +1,462 @@
{
"cpu_cycles_pass2_start": 4041504101117290,
"Misc": {
"vcs_version": "O-2018.09-SP2_Full64",
"master_pid": 56094,
"csrc": "csrc",
"vcs_build_date": "Build Date = Feb 28 2019 22:34:30",
"VCS_HOME": "/opt/synopsys/vcs-mx/O-2018.09-SP2",
"hostname": "cryo1",
"archive_dir": "archive.16",
"csrc_abs": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc",
"cwd": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top",
"daidir": "simv.daidir",
"default_output_dir": "csrc",
"daidir_abs": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir"
},
"cycles_program_begin": 4041503055448976,
"CompileStrategy": "fullobj",
"perf": [
{
"stat": [
"main",
"entry",
0.025707006454467773,
0.050798000000000003,
0.040638000000000001,
219324,
219324,
0.0,
0.0,
1775531482.845031,
4041503055807372
],
"sub": [
{
"stat": [
"doParsingAndDesignResolution",
"entry",
0.15805292129516602,
0.059728999999999997,
0.051630000000000002,
279468,
280268,
0.0,
0.0,
1775531482.9773769,
4041503399842812
],
"sub": []
},
{
"stat": [
"doParsingAndDesignResolution",
"exit",
0.17752289772033691,
0.075049000000000005,
0.055780000000000003,
280732,
281380,
0.0,
0.0,
1775531482.9968469,
4041503450421354
],
"sub": []
},
{
"stat": [
"doPostDesignResolutionToVir2Vcs",
"entry",
0.18805098533630371,
0.075049000000000005,
0.057679000000000001,
280732,
281380,
0.0037090000000000001,
0.0049459999999999999,
1775531483.007375,
4041503477997862
],
"sub": [
{
"stat": [
"doUptoVir2VcsNoSepCleanup",
"entry",
0.20422601699829102,
0.088502999999999998,
0.060401000000000003,
281844,
281848,
0.0037090000000000001,
0.0049459999999999999,
1775531483.02355,
4041503519841320
],
"sub": []
},
{
"stat": [
"doUptoVir2VcsNoSepCleanup",
"exit",
0.35647892951965332,
0.17352999999999999,
0.080711000000000005,
283736,
296992,
0.014555,
0.039600000000000003,
1775531483.1758029,
4041503915720814
],
"sub": []
},
{
"stat": [
"doRadify_vir2vcsAll",
"entry",
0.35656595230102539,
0.17358999999999999,
0.080739000000000005,
283736,
296992,
0.014555,
0.039600000000000003,
1775531483.17589,
4041503915875626
],
"sub": []
},
{
"stat": [
"doRadify_vir2vcsAll",
"exit",
0.36506390571594238,
0.182087,
0.080739000000000005,
285224,
296992,
0.014555,
0.039600000000000003,
1775531483.1843879,
4041503938032246
],
"sub": []
}
]
},
{
"stat": [
"doPostDesignResolutionToVir2Vcs",
"exit",
0.36511087417602539,
0.18213499999999999,
0.080739000000000005,
285224,
296992,
0.014555,
0.039600000000000003,
1775531483.1844349,
4041503938083582
],
"sub": []
},
{
"stat": [
"doGAToPass2",
"entry",
0.36512899398803711,
0.18215300000000001,
0.080739000000000005,
285224,
296992,
0.014555,
0.039600000000000003,
1775531483.184453,
4041503938124922
],
"sub": [
{
"stat": [
"DoPass2",
"entry",
0.42776107788085938,
0.18302499999999999,
0.084940000000000002,
283668,
296992,
0.040840000000000001,
0.072571999999999998,
1775531483.2470851,
4041504101098614
],
"sub": []
},
{
"stat": [
"DoPass2",
"exit",
0.59294986724853516,
0.20028499999999999,
0.107767,
286200,
296992,
0.142126,
0.12512899999999999,
1775531483.4122739,
4041504530526600
],
"sub": []
}
]
},
{
"stat": [
"doGAToPass2",
"exit",
0.59738898277282715,
0.20255200000000001,
0.109927,
288136,
296992,
0.142126,
0.12512899999999999,
1775531483.416713,
4041504542066856
],
"sub": []
}
]
},
{
"stat": [
"main",
"exit",
0.59781694412231445,
0.20294899999999999,
0.109959,
288128,
296992,
0.142126,
0.12512899999999999,
1775531483.417141,
4041504543136380
],
"sub": []
}
],
"MlibObjs": {},
"CompileProcesses": [
"cgproc.56094.json",
"cgproc.56112.json",
"cgproc.56113.json"
],
"PrevCompiledModules": {
"sirv_gnrl_dfflrs": {
"ZJgwY_d": {
"mod": "sirv_gnrl_dfflrs",
"bytes": 11754,
"mode": 4,
"archive": "archive.16/_prev_archive_1.a",
"checksum": 0,
"out": "ZJgwY_d.o"
}
},
"sirv_gnrl_dffrs": {
"QHiet_d": {
"mod": "sirv_gnrl_dffrs",
"bytes": 10828,
"mode": 4,
"archive": "archive.16/_prev_archive_1.a",
"checksum": 0,
"out": "QHiet_d.o"
}
},
"std": {
"reYIK_d": {
"mod": "std",
"bytes": 35776,
"mode": 4,
"archive": "archive.16/_prev_archive_1.a",
"checksum": 0,
"out": "reYIK_d.o"
}
},
"sirv_gnrl_dfflrd": {
"Uye5v_d": {
"mod": "sirv_gnrl_dfflrd",
"bytes": 11006,
"mode": 4,
"archive": "archive.16/_prev_archive_1.a",
"checksum": 0,
"out": "Uye5v_d.o"
}
},
"sirv_gnrl_dffl": {
"BM4bj_d": {
"mod": "sirv_gnrl_dffl",
"bytes": 10090,
"mode": 4,
"archive": "archive.16/_prev_archive_1.a",
"checksum": 0,
"out": "BM4bj_d.o"
}
},
"sirv_gnrl_ltch": {
"UTi0b_d": {
"mod": "sirv_gnrl_ltch",
"bytes": 9576,
"mode": 4,
"archive": "archive.16/_prev_archive_1.a",
"checksum": 0,
"out": "UTi0b_d.o"
}
},
"TB": {
"sH4Fc_d": {
"mod": "TB",
"bytes": 132880,
"out": "sH4Fc_d.o",
"mode": 4,
"archive": "archive.16/_56112_archive_1.a",
"checksum": 0
}
},
"...MASTER...": {
"amcQw_d": {
"mod": "...MASTER...",
"bytes": 9036,
"mode": 4,
"checksum": 0,
"out": "objs/amcQw_d.o"
}
}
},
"NameTable": {
"std": [
"std",
"reYIK",
"module",
1
],
"sirv_gnrl_dfflrs": [
"sirv_gnrl_dfflrs",
"ZJgwY",
"module",
2
],
"TB": [
"TB",
"sH4Fc",
"module",
7
],
"sirv_gnrl_dfflrd": [
"sirv_gnrl_dfflrd",
"Uye5v",
"module",
3
],
"sirv_gnrl_dffl": [
"sirv_gnrl_dffl",
"BM4bj",
"module",
4
],
"sirv_gnrl_ltch": [
"sirv_gnrl_ltch",
"UTi0b",
"module",
6
],
"sirv_gnrl_dffrs": [
"sirv_gnrl_dffrs",
"QHiet",
"module",
5
],
"...MASTER...": [
"SIM",
"amcQw",
"module",
8
]
},
"stat": {
"cpu_cycles_end": 4041504543244116,
"ru_self_cgstart": {
"ru_utime_sec": 0.18302499999999999,
"ru_stime_sec": 0.085038000000000002,
"ru_nvcsw": 43,
"ru_maxrss_kb": 78600,
"ru_nivcsw": 3,
"ru_minflt": 27664,
"ru_majflt": 0
},
"ru_childs_cgstart": {
"ru_utime_sec": 0.040840000000000001,
"ru_stime_sec": 0.072571999999999998,
"ru_nvcsw": 26,
"ru_maxrss_kb": 23868,
"ru_nivcsw": 24,
"ru_minflt": 11291,
"ru_majflt": 0
},
"outputSizePerQuad": 250.05405405405406,
"nMops": 967,
"cpu_cycles_cgstart": 4041504101208464,
"nQuads": 518,
"totalObjSize": 129528,
"ru_childs_end": {
"ru_utime_sec": 0.142126,
"ru_stime_sec": 0.12512899999999999,
"ru_nvcsw": 62,
"ru_maxrss_kb": 43420,
"ru_nivcsw": 26,
"ru_minflt": 21252,
"ru_majflt": 0
},
"ru_self_end": {
"ru_utime_sec": 0.20300599999999999,
"ru_stime_sec": 0.109959,
"ru_nvcsw": 57,
"ru_maxrss_kb": 84140,
"ru_nivcsw": 5,
"ru_minflt": 30550,
"ru_majflt": 0
},
"cpu_cycles_total": 1487795140,
"mopSpeed": 7974.1397082470903,
"quadSpeed": 4271.5660484715536,
"mop/quad": 1.8667953667953667,
"Frontend(%)": 64.863588424139166,
"CodeGen(%)": 35.136411575860834,
"peak_mem_kb": 296992,
"realTime": 0.59789800643920898
},
"CurCompileUdps": {},
"LVLData": [
"SIM"
],
"SIMBData": {
"out": "amcQwB.o",
"bytes": 129528,
"text": 0,
"archive": "archive.16/_56094_archive_1.a"
},
"incremental": "on",
"CurCompileModules": [
"...MASTER...",
"sirv_gnrl_dfflrs",
"sirv_gnrl_dfflrd",
"sirv_gnrl_dffrs",
"sirv_gnrl_dffl",
"sirv_gnrl_ltch"
],
"PEModules": [],
"rlimit": {
"data": -1,
"stack": -1
},
"CompileStatus": "Successful"
}

BIN
sim/therm_chip_top/csrc/archive.0/_131039_archive_1.a
View File

Binary file not shown.

BIN
sim/therm_chip_top/csrc/archive.0/_131040_archive_1.a
View File

Binary file not shown.

1
sim/therm_chip_top/csrc/archive.0/_131040_archive_1.a.info
View File

@ -1 +0,0 @@
reYIK_d.o

BIN
sim/therm_chip_top/csrc/archive.0/_131020_archive_1.a → sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a
View File

Binary file not shown.

1
sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a.info Normal file
View File

@ -0,0 +1 @@
amcQwB.o

BIN
sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a Normal file
View File

Binary file not shown.

0
sim/therm_chip_top/csrc/archive.0/_131039_archive_1.a.info → sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a.info
View File

BIN
sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a Normal file
View File

Binary file not shown.

6
sim/therm_chip_top/csrc/archive.0/_131020_archive_1.a.info → sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a.info
View File

@ -1,6 +1,6 @@
reYIK_d.o
ZJgwY_d.o ZJgwY_d.o
Uye5v_d.o
QHiet_d.o QHiet_d.o
BM4bj_d.o Uye5v_d.o
UTi0b_d.o UTi0b_d.o
amcQwB.o BM4bj_d.o

BIN
sim/therm_chip_top/csrc/cgincr.sdb
View File

Binary file not shown.

488
sim/therm_chip_top/csrc/cginfo.json
View File

@ -1,17 +1,89 @@
{ {
"rlimit": { "CompileStrategy": "fullobj",
"data": -1, "CurCompileUdps": {},
"stack": -1 "CompileStatus": "Successful",
"PrevCompiledModules": {
"TB": {
"sH4Fc_d": {
"checksum": 0,
"bytes": 133914,
"mod": "TB",
"out": "sH4Fc_d.o",
"mode": 4,
"archive": "archive.17/_57264_archive_1.a"
}
},
"std": {
"reYIK_d": {
"checksum": 0,
"bytes": 35776,
"mod": "std",
"mode": 4,
"archive": "archive.17/_prev_archive_1.a",
"out": "reYIK_d.o"
}
},
"sirv_gnrl_dfflrs": {
"ZJgwY_d": {
"checksum": 0,
"bytes": 11754,
"mod": "sirv_gnrl_dfflrs",
"mode": 4,
"archive": "archive.17/_prev_archive_1.a",
"out": "ZJgwY_d.o"
}
},
"sirv_gnrl_dffrs": {
"QHiet_d": {
"checksum": 0,
"bytes": 10828,
"mod": "sirv_gnrl_dffrs",
"mode": 4,
"archive": "archive.17/_prev_archive_1.a",
"out": "QHiet_d.o"
}
},
"sirv_gnrl_dfflrd": {
"Uye5v_d": {
"checksum": 0,
"bytes": 11006,
"mod": "sirv_gnrl_dfflrd",
"mode": 4,
"archive": "archive.17/_prev_archive_1.a",
"out": "Uye5v_d.o"
}
},
"sirv_gnrl_ltch": {
"UTi0b_d": {
"checksum": 0,
"bytes": 9576,
"mod": "sirv_gnrl_ltch",
"mode": 4,
"archive": "archive.17/_prev_archive_1.a",
"out": "UTi0b_d.o"
}
},
"...MASTER...": {
"amcQw_d": {
"checksum": 0,
"bytes": 9036,
"mod": "...MASTER...",
"mode": 4,
"out": "objs/amcQw_d.o"
}
},
"sirv_gnrl_dffl": {
"BM4bj_d": {
"checksum": 0,
"bytes": 10090,
"mod": "sirv_gnrl_dffl",
"mode": 4,
"archive": "archive.17/_prev_archive_1.a",
"out": "BM4bj_d.o"
}
}
}, },
"CompileProcesses": [ "cycles_program_begin": 4041681552700912,
"cgproc.131020.json",
"cgproc.131039.json",
"cgproc.131040.json"
],
"cycles_program_begin": 4026983680315700,
"cpu_cycles_pass2_start": 4026984736454666,
"PrevCompiledModules": {},
"incremental": "on",
"NameTable": { "NameTable": {
"std": [ "std": [
"std", "std",
@ -19,47 +91,47 @@
"module", "module",
1 1
], ],
"sirv_gnrl_dffl": [
"sirv_gnrl_dffl",
"BM4bj",
"module",
4
],
"TB": [ "TB": [
"TB", "TB",
"sH4Fc", "sH4Fc",
"module", "module",
7 7
], ],
"sirv_gnrl_dffrs": [
"sirv_gnrl_dffrs",
"QHiet",
"module",
5
],
"sirv_gnrl_dfflrs": [ "sirv_gnrl_dfflrs": [
"sirv_gnrl_dfflrs", "sirv_gnrl_dfflrs",
"ZJgwY", "ZJgwY",
"module", "module",
2 2
], ],
"sirv_gnrl_dfflrd": [
"sirv_gnrl_dfflrd",
"Uye5v",
"module",
3
],
"sirv_gnrl_ltch": [ "sirv_gnrl_ltch": [
"sirv_gnrl_ltch", "sirv_gnrl_ltch",
"UTi0b", "UTi0b",
"module", "module",
6 6
], ],
"sirv_gnrl_dfflrd": [
"sirv_gnrl_dfflrd",
"Uye5v",
"module",
3
],
"sirv_gnrl_dffl": [
"sirv_gnrl_dffl",
"BM4bj",
"module",
4
],
"...MASTER...": [ "...MASTER...": [
"SIM", "SIM",
"amcQw", "amcQw",
"module", "module",
8 8
],
"sirv_gnrl_dffrs": [
"sirv_gnrl_dffrs",
"QHiet",
"module",
5
] ]
}, },
"perf": [ "perf": [
@ -67,30 +139,30 @@
"stat": [ "stat": [
"main", "main",
"entry", "entry",
0.025353193283081055, 0.025187969207763672,
0.051507999999999998, 0.047795999999999998,
0.032318, 0.035846999999999997,
219324, 219324,
219324, 219324,
0.0, 0.0,
0.0, 0.0,
1775525898.4924941, 1775531551.4975231,
4026983680601896 4041681552987980
], ],
"sub": [ "sub": [
{ {
"stat": [ "stat": [
"doParsingAndDesignResolution", "doParsingAndDesignResolution",
"entry", "entry",
0.15924215316772461, 0.15317082405090332,
0.059558, 0.055349000000000002,
0.044912000000000001, 0.045949999999999998,
279468, 279468,
280268, 280268,
0.0, 0.0,
0.0, 0.0,
1775525898.6263831, 1775531551.6255059,
4026984028726890 4041681885663436
], ],
"sub": [] "sub": []
}, },
@ -98,15 +170,15 @@
"stat": [ "stat": [
"doParsingAndDesignResolution", "doParsingAndDesignResolution",
"exit", "exit",
0.17695212364196777, 0.16832685470581055,
0.069958000000000006, 0.067585000000000006,
0.052221999999999998, 0.048869000000000003,
280732, 280732,
281380, 281380,
0.0, 0.0,
0.0, 0.0,
1775525898.644093, 1775531551.640662,
4026984074783690 4041681925078996
], ],
"sub": [] "sub": []
}, },
@ -114,30 +186,30 @@
"stat": [ "stat": [
"doPostDesignResolutionToVir2Vcs", "doPostDesignResolutionToVir2Vcs",
"entry", "entry",
0.18804812431335449, 0.17739486694335938,
0.070393999999999998, 0.068685999999999997,
0.053773000000000001, 0.048912999999999998,
280732, 280732,
281380, 281380,
0.001305, 0.0039620000000000002,
0.0078320000000000004, 0.0039620000000000002,
1775525898.655189, 1775531551.64973,
4026984103612948 4041681948669414
], ],
"sub": [ "sub": [
{ {
"stat": [ "stat": [
"doUptoVir2VcsNoSepCleanup", "doUptoVir2VcsNoSepCleanup",
"entry", "entry",
0.19855499267578125, 0.18636298179626465,
0.078539999999999999, 0.076559000000000002,
0.056134000000000003, 0.050008999999999998,
281872, 281844,
281876, 281848,
0.001305, 0.0039620000000000002,
0.0078320000000000004, 0.0039620000000000002,
1775525898.6656959, 1775531551.6586981,
4026984130863100 4041681971959420
], ],
"sub": [] "sub": []
}, },
@ -145,15 +217,15 @@
"stat": [ "stat": [
"doUptoVir2VcsNoSepCleanup", "doUptoVir2VcsNoSepCleanup",
"exit", "exit",
0.35943198204040527, 0.31557178497314453,
0.156747, 0.147367,
0.083333000000000004, 0.064473000000000003,
283660, 283736,
296884, 296992,
0.017238, 0.016215,
0.046074999999999998, 0.035156,
1775525898.8265729, 1775531551.7879069,
4026984549325418 4041682307928962
], ],
"sub": [] "sub": []
}, },
@ -161,15 +233,15 @@
"stat": [ "stat": [
"doRadify_vir2vcsAll", "doRadify_vir2vcsAll",
"entry", "entry",
0.35964107513427734, 0.31564092636108398,
0.15688299999999999, 0.14741499999999999,
0.083405999999999994, 0.064493999999999996,
283660, 283736,
296884, 296992,
0.017238, 0.016215,
0.046074999999999998, 0.035156,
1775525898.826782, 1775531551.787976,
4026984549745642 4041682308054458
], ],
"sub": [] "sub": []
}, },
@ -177,15 +249,15 @@
"stat": [ "stat": [
"doRadify_vir2vcsAll", "doRadify_vir2vcsAll",
"exit", "exit",
0.36980605125427246, 0.32315182685852051,
0.162995, 0.15307100000000001,
0.087459999999999996, 0.066331000000000001,
284992, 285224,
296884, 296992,
0.017238, 0.016215,
0.046074999999999998, 0.035156,
1775525898.836947, 1775531551.7954869,
4026984576149880 4041682327624920
], ],
"sub": [] "sub": []
} }
@ -195,15 +267,15 @@
"stat": [ "stat": [
"doPostDesignResolutionToVir2Vcs", "doPostDesignResolutionToVir2Vcs",
"exit", "exit",
0.3698570728302002, 0.32318878173828125,
0.16303000000000001, 0.15309800000000001,
0.087479000000000001, 0.066341999999999998,
284992, 285224,
296884, 296992,
0.017238, 0.016215,
0.046074999999999998, 0.035156,
1775525898.836998, 1775531551.7955239,
4026984576202038 4041682327674366
], ],
"sub": [] "sub": []
}, },
@ -211,30 +283,30 @@
"stat": [ "stat": [
"doGAToPass2", "doGAToPass2",
"entry", "entry",
0.36987519264221191, 0.32320594787597656,
0.16304099999999999, 0.15311,
0.087484999999999993, 0.066347000000000003,
284992, 285224,
296884, 296992,
0.017238, 0.016215,
0.046074999999999998, 0.035156,
1775525898.8370161, 1775531551.795541,
4026984576243042 4041682327712278
], ],
"sub": [ "sub": [
{ {
"stat": [ "stat": [
"DoPass2", "DoPass2",
"entry", "entry",
0.43139505386352539, 0.37333297729492188,
0.16487399999999999, 0.15396199999999999,
0.092369000000000007, 0.070352999999999999,
283436, 283668,
296884, 296992,
0.040210999999999997, 0.035781,
0.079510999999999998, 0.062357999999999997,
1775525898.898536, 1775531551.8456681,
4026984736423114 4041682458256714
], ],
"sub": [] "sub": []
}, },
@ -242,15 +314,15 @@
"stat": [ "stat": [
"DoPass2", "DoPass2",
"exit", "exit",
0.58017301559448242, 0.50662589073181152,
0.19891900000000001, 0.16746,
0.114953, 0.083729999999999999,
287216, 286200,
296884, 296992,
0.14067499999999999, 0.13755500000000001,
0.12798200000000001, 0.092283000000000004,
1775525899.0473139, 1775531551.978961,
4026985123075080 4041682804644498
], ],
"sub": [] "sub": []
} }
@ -260,15 +332,15 @@
"stat": [ "stat": [
"doGAToPass2", "doGAToPass2",
"exit", "exit",
0.58391714096069336, 0.51018190383911133,
0.20239299999999999, 0.169152,
0.11522300000000001, 0.085595000000000004,
287216, 288136,
296884, 296992,
0.14067499999999999, 0.13755500000000001,
0.12798200000000001, 0.092283000000000004,
1775525899.0510581, 1775531551.982517,
4026985132810504 4041682813892048
], ],
"sub": [] "sub": []
} }
@ -278,111 +350,113 @@
"stat": [ "stat": [
"main", "main",
"exit", "exit",
0.58433914184570312, 0.51050591468811035,
0.20239299999999999, 0.16936699999999999,
0.115645, 0.085704000000000002,
287208, 288128,
296884, 296992,
0.14067499999999999, 0.13755500000000001,
0.12798200000000001, 0.092283000000000004,
1775525899.0514801, 1775531551.982841,
4026985133861756 4041682814707124
], ],
"sub": [] "sub": []
} }
], ],
"cpu_cycles_pass2_start": 4041682458287570,
"MlibObjs": {}, "MlibObjs": {},
"CurCompileUdps": {}, "PEModules": [],
"Misc": { "incremental": "on",
"vcs_version": "O-2018.09-SP2_Full64",
"vcs_build_date": "Build Date = Feb 28 2019 22:34:30",
"master_pid": 131020,
"VCS_HOME": "/opt/synopsys/vcs-mx/O-2018.09-SP2",
"daidir_abs": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir",
"hostname": "cryo1",
"cwd": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top",
"csrc": "csrc",
"csrc_abs": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc",
"daidir": "simv.daidir",
"default_output_dir": "csrc",
"archive_dir": "archive.0"
},
"stat": { "stat": {
"cpu_cycles_cgstart": 4026984736643766,
"ru_self_cgstart": { "ru_self_cgstart": {
"ru_utime_sec": 0.16498199999999999, "ru_utime_sec": 0.15407000000000001,
"ru_maxrss_kb": 78468, "ru_stime_sec": 0.070402000000000006,
"ru_stime_sec": 0.092428999999999997, "ru_maxrss_kb": 78600,
"ru_minflt": 28217, "ru_nvcsw": 42,
"ru_nivcsw": 3, "ru_minflt": 27557,
"ru_majflt": 0, "ru_nivcsw": 7,
"ru_nvcsw": 43 "ru_majflt": 0
}, },
"mopSpeed": 7013.5992747053488, "cpu_cycles_end": 4041682814798148,
"totalObjSize": 129528,
"ru_childs_cgstart": { "ru_childs_cgstart": {
"ru_utime_sec": 0.040210999999999997, "ru_utime_sec": 0.035781,
"ru_maxrss_kb": 23856, "ru_stime_sec": 0.062357999999999997,
"ru_stime_sec": 0.079510999999999998, "ru_maxrss_kb": 23868,
"ru_minflt": 11857, "ru_nvcsw": 26,
"ru_nivcsw": 26, "ru_minflt": 11291,
"ru_majflt": 0, "ru_nivcsw": 24,
"ru_nvcsw": 27 "ru_majflt": 0
}, },
"nMops": 967, "nMops": 967,
"totalObjSize": 192218, "cpu_cycles_cgstart": 4041682458460846,
"nQuads": 518, "nQuads": 518,
"ru_self_end": { "ru_self_end": {
"ru_utime_sec": 0.20239299999999999, "ru_utime_sec": 0.16939899999999999,
"ru_maxrss_kb": 86096, "ru_stime_sec": 0.085720000000000005,
"ru_stime_sec": 0.115699, "ru_maxrss_kb": 84144,
"ru_minflt": 31602, "ru_nvcsw": 56,
"ru_nivcsw": 5, "ru_minflt": 30443,
"ru_majflt": 0, "ru_nivcsw": 8,
"ru_nvcsw": 66 "ru_majflt": 0
}, },
"ru_childs_end": { "ru_childs_end": {
"ru_utime_sec": 0.14067499999999999, "ru_utime_sec": 0.13755500000000001,
"ru_maxrss_kb": 43708, "ru_stime_sec": 0.092283000000000004,
"ru_stime_sec": 0.12798200000000001, "ru_maxrss_kb": 43496,
"ru_minflt": 21834, "ru_nvcsw": 62,
"ru_minflt": 21284,
"ru_nivcsw": 26, "ru_nivcsw": 26,
"ru_majflt": 0, "ru_majflt": 0
"ru_nvcsw": 70
}, },
"cpu_cycles_end": 4026985133966878, "quadSpeed": 4423.4562735369727,
"cpu_cycles_total": 1453651178, "cpu_cycles_total": 1262097236,
"quadSpeed": 3757.0262919310971, "CodeGen(%)": 38.150015963303943,
"mopSpeed": 8257.6876766607184,
"mop/quad": 1.8667953667953667, "mop/quad": 1.8667953667953667,
"outputSizePerQuad": 371.07722007722009, "outputSizePerQuad": 250.05405405405406,
"CodeGen(%)": 40.188825538960209, "Frontend(%)": 61.849984036696057,
"Frontend(%)": 59.811174461039791, "peak_mem_kb": 296992,
"peak_mem_kb": 296884, "realTime": 0.51057696342468262
"realTime": 0.58441615104675293
}, },
"CompileStrategy": "fullobj",
"SIMBData": { "SIMBData": {
"out": "amcQwB.o",
"bytes": 129928,
"text": 0, "text": 0,
"archive": "archive.0/_131020_archive_1.a" "out": "amcQwB.o",
"bytes": 129528,
"archive": "archive.17/_57246_archive_1.a"
}, },
"CurCompileModules": [ "CurCompileModules": [
"...MASTER...", "...MASTER...",
"...MASTER...",
"sirv_gnrl_dfflrs",
"sirv_gnrl_dfflrs", "sirv_gnrl_dfflrs",
"sirv_gnrl_dfflrd", "sirv_gnrl_dfflrd",
"sirv_gnrl_dfflrd",
"sirv_gnrl_dffrs",
"sirv_gnrl_dffrs", "sirv_gnrl_dffrs",
"sirv_gnrl_dffl", "sirv_gnrl_dffl",
"sirv_gnrl_dffl",
"sirv_gnrl_ltch",
"sirv_gnrl_ltch" "sirv_gnrl_ltch"
], ],
"LVLData": [ "LVLData": [
"SIM" "SIM"
], ],
"PEModules": [], "CompileProcesses": [
"CompileStatus": "Successful" "cgproc.57246.json",
"cgproc.57264.json",
"cgproc.57265.json"
],
"Misc": {
"vcs_version": "O-2018.09-SP2_Full64",
"master_pid": 57246,
"hostname": "cryo1",
"VCS_HOME": "/opt/synopsys/vcs-mx/O-2018.09-SP2",
"default_output_dir": "csrc",
"vcs_build_date": "Build Date = Feb 28 2019 22:34:30",
"cwd": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top",
"csrc": "csrc",
"csrc_abs": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc",
"daidir": "simv.daidir",
"daidir_abs": "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir",
"archive_dir": "archive.17"
},
"rlimit": {
"data": -1,
"stack": -1
}
} }

281
sim/therm_chip_top/csrc/cgproc.131020.json
View File

@ -1,281 +0,0 @@
{
"reusePaths": {},
"Modules": {
"...MASTER...": {
"nRouts": 11,
"start_perf": [
0.43294119834899902,
0.16522700000000001,
0.093562000000000006,
283436,
296884,
1775525898.9000821,
4026984740432502
],
"nQuads": 7,
"child_modules": {
"sirv_gnrl_dffrs": 1,
"sirv_gnrl_dfflrs": 1,
"sirv_gnrl_dffl": 1,
"TB": 1,
"std": 1,
"sirv_gnrl_ltch": 1
},
"end_perf": [
0.43971705436706543,
0.169076,
0.096473000000000003,
285852,
296884,
4026984757885970,
0,
0
],
"nMops": 13
},
"sirv_gnrl_dffrs": {
"nRouts": 27,
"start_perf": [
0.46023201942443848,
0.179672,
0.10630100000000001,
290200,
296884,
1775525898.9273729,
4026984811179316
],
"nQuads": 106,
"child_modules": {},
"end_perf": [
0.46452999114990234,
0.18390300000000001,
0.106366,
290200,
296884,
4026984822423498,
34359738369,
0
],
"Compiled": "Yes",
"Compiled Times": 1,
"nMops": 192
},
"sirv_gnrl_dfflrs": {
"nRouts": 29,
"start_perf": [
0.44277620315551758,
0.169124,
0.099484000000000003,
285836,
296884,
1775525898.9099171,
4026984765861954
],
"nQuads": 130,
"child_modules": {},
"end_perf": [
0.45535016059875488,
0.174812,
0.106277,
290200,
296884,
4026984798552590,
17179869185,
0
],
"Compiled": "Yes",
"Compiled Times": 1,
"nMops": 237
},
"sirv_gnrl_dfflrd": {
"nRouts": 27,
"start_perf": [
0.45541119575500488,
0.17485000000000001,
0.10630100000000001,
290200,
296884,
1775525898.9225521,
4026984798649168
],
"nQuads": 127,
"child_modules": {},
"end_perf": [
0.46017813682556152,
0.179617,
0.10630100000000001,
290200,
296884,
4026984811106202,
25769803777,
0
],
"Compiled": "Yes",
"Compiled Times": 1,
"nMops": 250
},
"sirv_gnrl_dffl": {
"nRouts": 23,
"start_perf": [
0.4645850658416748,
0.18393899999999999,
0.10638599999999999,
290200,
296884,
1775525898.931726,
4026984822492872
],
"nQuads": 86,
"child_modules": {},
"end_perf": [
0.46852517127990723,
0.18787799999999999,
0.10638599999999999,
290200,
296884,
4026984832808074,
30064771073,
0
],
"Compiled": "Yes",
"Compiled Times": 1,
"nMops": 151
},
"sirv_gnrl_ltch": {
"nRouts": 15,
"start_perf": [
0.46857905387878418,
0.18792700000000001,
0.106392,
290200,
296884,
1775525898.93572,
4026984832880982
],
"nQuads": 62,
"child_modules": {},
"end_perf": [
0.47210907936096191,
0.19145699999999999,
0.106392,
290200,
296884,
4026984842119740,
42949672961,
0
],
"Compiled": "Yes",
"Compiled Times": 1,
"nMops": 124
}
},
"CompUnits": {
"QHiet_d": {
"mod": "sirv_gnrl_dffrs",
"checksum": 0,
"out": "QHiet_d.o",
"bytes": 10828,
"mode": 4,
"text": 1659,
"archive": "archive.0/_131020_archive_1.a"
},
"amcQw_d": {
"mod": "...MASTER...",
"checksum": 0,
"out": "objs/amcQw_d.o",
"bytes": 9036,
"mode": 4,
"text": 671
},
"ZJgwY_d": {
"mod": "sirv_gnrl_dfflrs",
"checksum": 0,
"out": "ZJgwY_d.o",
"bytes": 11754,
"mode": 4,
"text": 1862,
"archive": "archive.0/_131020_archive_1.a"
},
"UTi0b_d": {
"mod": "sirv_gnrl_ltch",
"checksum": 0,
"out": "UTi0b_d.o",
"bytes": 9576,
"mode": 4,
"text": 1047,
"archive": "archive.0/_131020_archive_1.a"
},
"BM4bj_d": {
"mod": "sirv_gnrl_dffl",
"checksum": 0,
"out": "BM4bj_d.o",
"bytes": 10090,
"mode": 4,
"text": 1247,
"archive": "archive.0/_131020_archive_1.a"
},
"Uye5v_d": {
"mod": "sirv_gnrl_dfflrd",
"checksum": 0,
"out": "Uye5v_d.o",
"bytes": 11006,
"mode": 4,
"text": 1863,
"archive": "archive.0/_131020_archive_1.a"
}
},
"ObjArchives": [
{
"archive": "archive.0/_131020_archive_1.a",
"objects": [
[
"ZJgwY_d.o",
11754
],
[
"Uye5v_d.o",
11006
],
[
"QHiet_d.o",
10828
],
[
"BM4bj_d.o",
10090
],
[
"UTi0b_d.o",
9576
],
[
"amcQwB.o",
129928
]
],
"size": 183182
}
],
"stat": {
"ru_self_end": {
"ru_utime_sec": 0.20239299999999999,
"ru_maxrss_kb": 86096,
"ru_stime_sec": 0.115329,
"ru_minflt": 31598,
"ru_nivcsw": 5,
"ru_majflt": 0,
"ru_nvcsw": 66
},
"ru_childs_end": {
"ru_utime_sec": 0.14067499999999999,
"ru_maxrss_kb": 43708,
"ru_stime_sec": 0.12798200000000001,
"ru_minflt": 21834,
"ru_nivcsw": 26,
"ru_majflt": 0,
"ru_nvcsw": 70
},
"cpu_cycles_end": 4026985133010656,
"peak_mem_kb": 296884
}
}

88
sim/therm_chip_top/csrc/cgproc.131039.json
View File

@ -1,88 +0,0 @@
{
"reusePaths": {},
"Modules": {
"TB": {
"start_perf": [
0.44163417816162109,
0.0,
0.00099500000000000001,
285836,
285836,
1775525898.9087751,
4026984763255954
],
"nQuads": 4843,
"child_modules": {
"sirv_gnrl_dfflrd": 5
},
"Compiled": "Yes",
"end_perf": [
0.53441810607910156,
0.074830999999999995,
0.018957000000000002,
294576,
294576,
4026985004138688,
77309411329,
0
],
"Compiled Times": 1,
"significant_routs": [
[
130,
"R_VCSgd_sH4Fc_82",
7397226,
4385,
1013
]
],
"nMops": 11228,
"nRouts": 460
}
},
"CompUnits": {
"sH4Fc_d": {
"mod": "TB",
"checksum": 0,
"out": "sH4Fc_d.o",
"bytes": 131190,
"mode": 4,
"text": 61914,
"archive": "archive.0/_131039_archive_1.a"
}
},
"ObjArchives": [
{
"archive": "archive.0/_131039_archive_1.a",
"objects": [
[
"sH4Fc_d.o",
131190
]
],
"size": 131190
}
],
"stat": {
"ru_self_end": {
"ru_utime_sec": 0.075082999999999997,
"ru_maxrss_kb": 39980,
"ru_stime_sec": 0.019021,
"ru_minflt": 4597,
"ru_nivcsw": 0,
"ru_majflt": 0,
"ru_nvcsw": 0
},
"ru_childs_end": {
"ru_utime_sec": 0.0,
"ru_maxrss_kb": 0,
"ru_stime_sec": 0.0,
"ru_minflt": 0,
"ru_nivcsw": 0,
"ru_majflt": 0,
"ru_nvcsw": 0
},
"cpu_cycles_end": 4026985004857588,
"peak_mem_kb": 294580
}
}

116
sim/therm_chip_top/csrc/cgproc.131040.json
View File

@ -1,116 +0,0 @@
{
"reusePaths": {},
"Modules": {
"std": {
"start_perf": [
0.44302701950073242,
0.001,
0.0,
285836,
285836,
1775525898.9101679,
4026984766925290
],
"nQuads": 224,
"child_modules": {},
"Compiled": "Yes",
"end_perf": [
0.45973801612854004,
0.0093670000000000003,
0.0083260000000000001,
289492,
289492,
4026984809951740,
8589934594,
0
],
"Compiled Times": 1,
"svclass": [
"$vcs_nba_dyn_obj",
385,
37,
2,
2,
0,
"sigprop$$",
385,
37,
2,
2,
0,
"process",
1645,
184,
8,
8,
0,
"event",
462,
36,
2,
2,
0,
"mailbox",
912,
107,
9,
9,
0,
"semaphore",
672,
71,
5,
5,
0
],
"nMops": 477,
"nRouts": 36
}
},
"CompUnits": {
"reYIK_d": {
"mod": "std",
"checksum": 0,
"out": "reYIK_d.o",
"bytes": 35776,
"mode": 4,
"text": 4811,
"cls": 4461,
"archive": "archive.0/_131040_archive_1.a"
}
},
"ObjArchives": [
{
"archive": "archive.0/_131040_archive_1.a",
"objects": [
[
"reYIK_d.o",
35776
]
],
"size": 35776
}
],
"stat": {
"ru_self_end": {
"ru_utime_sec": 0.0093670000000000003,
"ru_maxrss_kb": 33524,
"ru_stime_sec": 0.0086359999999999996,
"ru_minflt": 2444,
"ru_nivcsw": 0,
"ru_majflt": 0,
"ru_nvcsw": 1
},
"ru_childs_end": {
"ru_utime_sec": 0.0,
"ru_maxrss_kb": 0,
"ru_stime_sec": 0.0,
"ru_minflt": 0,
"ru_nivcsw": 0,
"ru_majflt": 0,
"ru_nvcsw": 0
},
"cpu_cycles_end": 4026984810673476,
"peak_mem_kb": 289496
}
}

226
sim/therm_chip_top/csrc/cgproc.57246.json Normal file
View File

@ -0,0 +1,226 @@
{
"reusePaths": {
"amcQw_d": {
"icPath": "csrc"
},
"ZJgwY_d": {
"icPath": "csrc"
},
"Uye5v_d": {
"icPath": "csrc"
},
"QHiet_d": {
"icPath": "csrc"
},
"BM4bj_d": {
"icPath": "csrc"
},
"UTi0b_d": {
"icPath": "csrc"
}
},
"CompUnits": {},
"Modules": {
"sirv_gnrl_dffl": {
"start_perf": [
0.3974149227142334,
0.16103600000000001,
0.079497999999999999,
285436,
296992,
1775531551.86975,
4041682520664734
],
"nRouts": 23,
"nQuads": 86,
"child_modules": {},
"Compiled Times": 18,
"Compiled": "Yes",
"end_perf": [
0.39875888824462891,
0.162272,
0.079604999999999995,
285436,
296992,
4041682524212716,
30064771073,
0
],
"nMops": 151
},
"...MASTER...": {
"start_perf": [
0.37381982803344727,
0.15440100000000001,
0.070402000000000006,
283668,
296992,
1775531551.8461549,
4041682459435874
],
"nRouts": 11,
"nQuads": 7,
"child_modules": {
"TB": 1,
"std": 1,
"sirv_gnrl_dfflrs": 1,
"sirv_gnrl_dffrs": 1,
"sirv_gnrl_ltch": 1,
"sirv_gnrl_dffl": 1
},
"end_perf": [
0.38642978668212891,
0.15610399999999999,
0.073459999999999998,
285100,
296992,
4041682492134808,
0,
0
],
"nMops": 13
},
"sirv_gnrl_dfflrs": {
"start_perf": [
0.38842678070068359,
0.15610399999999999,
0.075456999999999996,
285092,
296992,
1775531551.8607619,
4041682497325266
],
"nRouts": 29,
"nQuads": 130,
"child_modules": {},
"Compiled Times": 18,
"Compiled": "Yes",
"end_perf": [
0.39398884773254395,
0.15875,
0.078356999999999996,
285436,
296992,
4041682511786936,
17179869185,
0
],
"nMops": 237
},
"sirv_gnrl_ltch": {
"start_perf": [
0.3988029956817627,
0.16231599999999999,
0.079604999999999995,
285436,
296992,
1775531551.8711381,
4041682524269766
],
"nRouts": 15,
"nQuads": 62,
"child_modules": {},
"Compiled Times": 18,
"Compiled": "Yes",
"end_perf": [
0.40000200271606445,
0.16351599999999999,
0.079604999999999995,
285436,
296992,
4041682527410878,
42949672961,
0
],
"nMops": 124
},
"sirv_gnrl_dfflrd": {
"start_perf": [
0.39402890205383301,
0.158778,
0.078370999999999996,
285436,
296992,
1775531551.866364,
4041682511859682
],
"nRouts": 27,
"nQuads": 127,
"child_modules": {},
"Compiled Times": 18,
"Compiled": "Yes",
"end_perf": [
0.39577698707580566,
0.16028500000000001,
0.078611,
285436,
296992,
4041682516462532,
25769803777,
0
],
"nMops": 250
},
"sirv_gnrl_dffrs": {
"start_perf": [
0.39582300186157227,
0.16028500000000001,
0.078657000000000005,
285436,
296992,
1775531551.8681581,
4041682516522194
],
"nRouts": 27,
"nQuads": 106,
"child_modules": {},
"Compiled Times": 18,
"Compiled": "Yes",
"end_perf": [
0.39738178253173828,
0.16101299999999999,
0.079487000000000002,
285436,
296992,
4041682520607334,
34359738369,
0
],
"nMops": 192
}
},
"ObjArchives": [
{
"archive": "archive.17/_57246_archive_1.a",
"objects": [
[
"amcQwB.o",
129528
]
],
"size": 129528
}
],
"stat": {
"ru_self_end": {
"ru_utime_sec": 0.16919500000000001,
"ru_stime_sec": 0.085615999999999998,
"ru_maxrss_kb": 84144,
"ru_nvcsw": 56,
"ru_minflt": 30439,
"ru_nivcsw": 8,
"ru_majflt": 0
},
"ru_childs_end": {
"ru_utime_sec": 0.13755500000000001,
"ru_stime_sec": 0.092283000000000004,
"ru_maxrss_kb": 43496,
"ru_nvcsw": 62,
"ru_minflt": 21284,
"ru_nivcsw": 26,
"ru_majflt": 0
},
"cpu_cycles_end": 4041682813998046,
"peak_mem_kb": 296992
}
}

88
sim/therm_chip_top/csrc/cgproc.57264.json Normal file
View File

@ -0,0 +1,88 @@
{
"reusePaths": {},
"CompUnits": {
"sH4Fc_d": {
"mod": "TB",
"text": 63094,
"out": "sH4Fc_d.o",
"checksum": 0,
"bytes": 134118,
"mode": 4,
"archive": "archive.17/_57264_archive_1.a"
}
},
"Modules": {
"TB": {
"start_perf": [
0.387908935546875,
0.0,
0.00077800000000000005,
285092,
285092,
1775531551.860244,
4041682496390018
],
"child_modules": {
"sirv_gnrl_dfflrd": 5
},
"nQuads": 8636,
"significant_routs": [
[
133,
"R_VCSgd_sH4Fc_85",
6325624,
4651,
1078
]
],
"Compiled": "Yes",
"Compiled Times": 18,
"end_perf": [
0.48143482208251953,
0.087273000000000003,
0.0070219999999999996,
292828,
294880,
4041682739157474,
77309411329,
0
],
"nMops": 20350,
"nRouts": 472
}
},
"ObjArchives": [
{
"archive": "archive.17/_57264_archive_1.a",
"objects": [
[
"sH4Fc_d.o",
134118
]
],
"size": 134118
}
],
"stat": {
"ru_self_end": {
"ru_utime_sec": 0.087467000000000003,
"ru_stime_sec": 0.0070369999999999999,
"ru_maxrss_kb": 39924,
"ru_nvcsw": 1,
"ru_minflt": 4639,
"ru_nivcsw": 0,
"ru_majflt": 0
},
"ru_childs_end": {
"ru_utime_sec": 0.0,
"ru_stime_sec": 0.0,
"ru_maxrss_kb": 0,
"ru_nvcsw": 0,
"ru_minflt": 0,
"ru_nivcsw": 0,
"ru_majflt": 0
},
"cpu_cycles_end": 4041682739634416,
"peak_mem_kb": 294880
}
}

98
sim/therm_chip_top/csrc/cgproc.57265.json Normal file
View File

@ -0,0 +1,98 @@
{
"reusePaths": {
"reYIK_d": {
"icPath": "csrc"
}
},
"CompUnits": {},
"Modules": {
"std": {
"start_perf": [
0.38861989974975586,
0.000638,
0.0,
285092,
285092,
1775531551.860955,
4041682498268042
],
"child_modules": {},
"nQuads": 224,
"nRouts": 36,
"svclass": [
"$vcs_nba_dyn_obj",
0,
37,
2,
2,
0,
"sigprop$$",
0,
37,
2,
2,
0,
"process",
0,
184,
8,
8,
0,
"event",
0,
36,
2,
2,
0,
"mailbox",
0,
107,
9,
9,
0,
"semaphore",
0,
71,
5,
5,
0
],
"Compiled": "Yes",
"Compiled Times": 18,
"end_perf": [
0.39862990379333496,
0.003192,
0.0074479999999999998,
285112,
285112,
4041682523850886,
8589934594,
0
],
"nMops": 477
}
},
"ObjArchives": [],
"stat": {
"ru_self_end": {
"ru_utime_sec": 0.0032360000000000002,
"ru_stime_sec": 0.0075510000000000004,
"ru_maxrss_kb": 31568,
"ru_nvcsw": 1,
"ru_minflt": 1875,
"ru_nivcsw": 0,
"ru_majflt": 0
},
"ru_childs_end": {
"ru_utime_sec": 0.0,
"ru_stime_sec": 0.0,
"ru_maxrss_kb": 0,
"ru_nvcsw": 0,
"ru_minflt": 0,
"ru_nivcsw": 0,
"ru_majflt": 0
},
"cpu_cycles_end": 4041682524207970,
"peak_mem_kb": 285116
}
}

37
sim/therm_chip_top/csrc/filelist.cu
View File

@ -1,31 +1,34 @@
PIC_LD=ld PIC_LD=ld
ARCHIVE_OBJS= ARCHIVE_OBJS=
ARCHIVE_OBJS += _131020_archive_1.so ARCHIVE_OBJS += _57246_archive_1.so
_131020_archive_1.so : archive.0/_131020_archive_1.a _57246_archive_1.so : archive.17/_57246_archive_1.a
@$(AR) -s $< @$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131020_archive_1.so --whole-archive $< --no-whole-archive @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_57246_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@ @rm -f $@
@ln -sf .//../simv.daidir//_131020_archive_1.so $@ @ln -sf .//../simv.daidir//_57246_archive_1.so $@
ARCHIVE_OBJS += _131039_archive_1.so ARCHIVE_OBJS += _57264_archive_1.so
_131039_archive_1.so : archive.0/_131039_archive_1.a _57264_archive_1.so : archive.17/_57264_archive_1.a
@$(AR) -s $< @$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131039_archive_1.so --whole-archive $< --no-whole-archive @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_57264_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@ @rm -f $@
@ln -sf .//../simv.daidir//_131039_archive_1.so $@ @ln -sf .//../simv.daidir//_57264_archive_1.so $@
ARCHIVE_OBJS += _131040_archive_1.so ARCHIVE_OBJS += _prev_archive_1.so
_131040_archive_1.so : archive.0/_131040_archive_1.a _prev_archive_1.so : archive.17/_prev_archive_1.a
@$(AR) -s $< @$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131040_archive_1.so --whole-archive $< --no-whole-archive @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@ @rm -f $@
@ln -sf .//../simv.daidir//_131040_archive_1.so $@ @ln -sf .//../simv.daidir//_prev_archive_1.so $@
VCS_ARC0 =_csrc0.so
VCS_OBJS0 =objs/amcQw_d.o
O0_OBJS = O0_OBJS =
@ -36,6 +39,12 @@ $(O0_OBJS) : %.o: %.c
%.o: %.c %.o: %.c
$(CC_CG) $(CFLAGS_CG) -c -o $@ $< $(CC_CG) $(CFLAGS_CG) -c -o $@ $<
$(VCS_ARC0) : $(VCS_OBJS0)
$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0)
rm -f $(VCS_ARC0)
@ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0)
CU_UDP_OBJS = \ CU_UDP_OBJS = \
@ -43,7 +52,7 @@ CU_LVL_OBJS = \
SIM_l.o SIM_l.o
MAIN_OBJS = \ MAIN_OBJS = \
objs/amcQw_d.o
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS)

BIN
sim/therm_chip_top/csrc/hsim/hsim.sdb
View File

Binary file not shown.

BIN
sim/therm_chip_top/csrc/pre.cgincr.sdb Normal file
View File

Binary file not shown.

223
sim/therm_chip_top/novas.conf
View File

File diff suppressed because one or more lines are too long

20
sim/therm_chip_top/novas.rc
View File

@ -113,6 +113,7 @@ Branch = 1
IfShowModule = {TRUE, FALSE} IfShowModule = {TRUE, FALSE}
[DisabledMessages] [DisabledMessages]
version = Verdi_O-2018.09-SP2 version = Verdi_O-2018.09-SP2
184615126 = disabled
[Editor] [Editor]
editorName = TurboEditor editorName = TurboEditor
[Emacs] [Emacs]
@ -370,8 +371,9 @@ saveWaveformStat = TRUE
savePropStat = FALSE savePropStat = FALSE
savePropDtl = TRUE savePropDtl = TRUE
[QtDialog] [QtDialog]
QwWarnMsgDlg = 650,407,600,250 QwWarnMsgDlg = 650,444,600,250
QwUserAskDlg = 809,434,324,134 QwUserAskDlg = 798,524,324,134
SetWindowTimeUnitDialog = 742,466,433,86
[Relationship] [Relationship]
hideRecursiceNode = FALSE hideRecursiceNode = FALSE
[Session Cache] [Session Cache]
@ -558,7 +560,7 @@ pdmlMacro = ID_BLACK
font = COURIER12 font = COURIER12
annotFont = Helvetica_M_R_10 annotFont = Helvetica_M_R_10
[Text.1] [Text.1]
viewport = 453 103 1017 706 45 viewport = 239 111 1440 723 45
[TextPrinter] [TextPrinter]
Orientation = Landscape Orientation = Landscape
Indicator = FALSE Indicator = FALSE
@ -648,9 +650,9 @@ DefaultLogTimeUnit = "1.000000ns"
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] [VIA.oneSearch.preference.vgifColumnSettingRC.setting0]
parRuleSets = "" parRuleSets = ""
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] [VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0]
name = Severity name = Time
width = 60 width = 60
visualIndex = 1 visualIndex = 0
isHidden = TRUE isHidden = TRUE
isUserChangeColumnVisible = FALSE isUserChangeColumnVisible = FALSE
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] [VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1]
@ -672,9 +674,9 @@ visualIndex = 3
isHidden = TRUE isHidden = TRUE
isUserChangeColumnVisible = FALSE isUserChangeColumnVisible = FALSE
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] [VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4]
name = Time name = Severity
width = 60 width = 60
visualIndex = 0 visualIndex = 1
isHidden = TRUE isHidden = TRUE
isUserChangeColumnVisible = FALSE isUserChangeColumnVisible = FALSE
[Vi] [Vi]
@ -696,7 +698,7 @@ scope_to_save_with_macro
open_file_dir open_file_dir
open_rc_file_dir open_rc_file_dir
getSignalForm = 0 0 800 479 100 30 100 30 getSignalForm = 0 0 800 479 100 30 100 30
viewPort = 0 27 1017 282 100 65 viewPort = 0 27 1440 265 143 65
signalSpacing = 5 signalSpacing = 5
digitalSignalHeight = 15 digitalSignalHeight = 15
analogSignalHeight = 98 analogSignalHeight = 98
@ -1293,7 +1295,7 @@ AddImportArgument = FALSE
LineBreakWithScope = TRUE LineBreakWithScope = TRUE
StopAfterCompileOption = -s StopAfterCompileOption = -s
[wave.0] [wave.0]
viewPort = 0 27 1017 282 100 65 viewPort = 0 27 1440 265 143 65
[wave.1] [wave.1]
viewPort = 127 219 960 332 100 65 viewPort = 127 219 960 332 100 65
[wave.2] [wave.2]

77
sim/therm_chip_top/novas_dump.log
View File

@ -187,7 +187,7 @@ XDG_MENU_PREFIX=gnome-
VTE_VERSION=5204 VTE_VERSION=5204
SHELL=/bin/csh SHELL=/bin/csh
MAKEFLAGS= MAKEFLAGS=
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/33c4f0fe_b1af_4925_918d_f401e6285844 GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/c54e5016_f7fb_4a73_ae57_77787103df43
SPECTRE_HOME=/opt/cadence/SPECTRE181 SPECTRE_HOME=/opt/cadence/SPECTRE181
VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ VIVADO_HOME=/opt/xilinx/Vivado/2019.2/
CDS_LOAD_ENV=CWD CDS_LOAD_ENV=CWD
@ -290,8 +290,8 @@ argv[0]=./simv
argv[1]=sync:busywait argv[1]=sync:busywait
argv[2]=-l argv[2]=-l
291 profile - 100 291 profile - 100
CPU/Mem usage: 0.050 sys, 0.220 user, 282.41M mem CPU/Mem usage: 0.050 sys, 0.210 user, 284.52M mem
292 Tue Apr 7 09:38:20 2026 292 Tue Apr 7 11:12:33 2026
293 pliAppInit 293 pliAppInit
294 FSDB_GATE is set. 294 FSDB_GATE is set.
295 FSDB_RTL is set. 295 FSDB_RTL is set.
@ -303,45 +303,46 @@ argv[2]=-l
301 (C) 1996 - 2019 by Synopsys, Inc. 301 (C) 1996 - 2019 by Synopsys, Inc.
302 sps_call_fsdbDumpfile_main at 0 : ./TB.sv(22) 302 sps_call_fsdbDumpfile_main at 0 : ./TB.sv(22)
303 argv[0]: (wave.fsdb) 303 argv[0]: (wave.fsdb)
304 *Verdi* : Create FSDB file 'wave.fsdb' 304 *Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
305 compile option from '/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/vcs_rebuild'. 305 *Verdi* : Create FSDB file 'wave.fsdb'
306 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1" 306 compile option from '/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/vcs_rebuild'.
307 FSDB_VCS_ENABLE_FAST_VC is enable 307 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1"
308 sps_call_fsdbDumpvars_vd_main at 0 : ./TB.sv(23) 308 FSDB_VCS_ENABLE_FAST_VC is enable
309 [spi_vcs_vd_ppi_create_root]: no upf option 309 sps_call_fsdbDumpvars_vd_main at 0 : ./TB.sv(23)
310 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. 310 [spi_vcs_vd_ppi_create_root]: no upf option
311 *Verdi* : Begin traversing the scopes, layer (0). 311 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
312 *Verdi* : End of traversing. 312 *Verdi* : Begin traversing the scopes, layer (0).
313 pliAppHDL_DumpVarComplete traverse var: profile - 313 *Verdi* : End of traversing.
CPU/Mem usage: 0.080 sys, 0.230 user, 378.79M mem 314 pliAppHDL_DumpVarComplete traverse var: profile -
incr: 0.000 sys, 0.010 user, 8.98M mem CPU/Mem usage: 0.090 sys, 0.220 user, 380.92M mem
accu: 0.000 sys, 0.010 user, 8.98M mem incr: 0.010 sys, 0.000 user, 8.86M mem
accu incr: 0.000 sys, 0.010 user, 8.98M mem accu: 0.010 sys, 0.000 user, 8.86M mem
accu incr: 0.010 sys, 0.000 user, 8.86M mem
Count usage: 224 var, 123 idcode, 86 callback Count usage: 223 var, 122 idcode, 85 callback
incr: 224 var, 123 idcode, 86 callback incr: 223 var, 122 idcode, 85 callback
accu: 224 var, 123 idcode, 86 callback accu: 223 var, 122 idcode, 85 callback
accu incr: 224 var, 123 idcode, 86 callback accu incr: 223 var, 122 idcode, 85 callback
314 Tue Apr 7 09:38:20 2026 315 Tue Apr 7 11:12:33 2026
315 pliAppHDL_DumpVarComplete: profile - 316 pliAppHDL_DumpVarComplete: profile -
CPU/Mem usage: 0.080 sys, 0.230 user, 379.84M mem CPU/Mem usage: 0.090 sys, 0.220 user, 381.97M mem
incr: 0.000 sys, 0.000 user, 1.05M mem incr: 0.000 sys, 0.000 user, 1.05M mem
accu: 0.000 sys, 0.010 user, 10.04M mem accu: 0.010 sys, 0.000 user, 9.92M mem
accu incr: 0.000 sys, 0.000 user, 1.05M mem accu incr: 0.000 sys, 0.000 user, 1.05M mem
Count usage: 224 var, 123 idcode, 86 callback Count usage: 223 var, 122 idcode, 85 callback
incr: 0 var, 0 idcode, 0 callback incr: 0 var, 0 idcode, 0 callback
accu: 224 var, 123 idcode, 86 callback accu: 223 var, 122 idcode, 85 callback
accu incr: 0 var, 0 idcode, 0 callback accu incr: 0 var, 0 idcode, 0 callback
316 Tue Apr 7 09:38:20 2026 317 Tue Apr 7 11:12:33 2026
317 End of simulation at 17814400000 318 End of simulation at 67816396000
318 Tue Apr 7 09:38:21 2026 319 Tue Apr 7 11:12:36 2026
319 Begin FSDB profile info: 320 Begin FSDB profile info:
320 FSDB Writer : bc1(1815118) bcn(1365370) mtf/stf(0/1) 321 FSDB Writer : bc1(6944429) bcn(4210234) mtf/stf(0/2)
FSDB Writer elapsed time : flush(0.171826) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) FSDB Writer elapsed time : flush(0.508682) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
FSDB Writer cpu time : MT Compression : 0 FSDB Writer cpu time : MT Compression : 0
321 End FSDB profile info 322 End FSDB profile info
322 Parallel profile - Flush:3 Expand:0 ProduceWait:0 ConsumerWait:27 BlockUsed:34 323 Parallel profile - Flush:3 Expand:0 ProduceWait:0 ConsumerWait:116 BlockUsed:122
323 ProduceTime:1.172810727 ConsumerTime:0.465192911 Buffer:64MB 324 ProduceTime:2.819906888 ConsumerTime:1.842929702 Buffer:64MB
324 SimExit 325 SimExit
325 Sim process exit 326 Sim process exit

22
sim/therm_chip_top/rx_data.txt
View File

@ -3,6 +3,22 @@
025800a0 025800a0
0000c350 0000c350
00fff060 00fff060
00000b02 00fff4d0
aa000b02 aafff4d0
00000b02 aa0000c8
aa0000fc
aa00012d
aa00012c
aa00012c
aa00012c
aa00012c
aa00012c
aa00012c
aa00012c
aa00012d
aa00012c
aa00012c
aa00012c
aa00012c
aa00012c
0000012c

90
sim/therm_chip_top/sim.log
View File

@ -1,61 +1,51 @@
Chronologic VCS simulator copyright 1991-2018 Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information. Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Apr 7 09:38 2026 Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Apr 7 11:12 2026
*Verdi* Loading libsscore_vcs201809.so *Verdi* Loading libsscore_vcs201809.so
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc. (C) 1996 - 2019 by Synopsys, Inc.
*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi* : Create FSDB file 'wave.fsdb' *Verdi* : Create FSDB file 'wave.fsdb'
*Verdi* : Begin traversing the scopes, layer (0). *Verdi* : Begin traversing the scopes, layer (0).
*Verdi* : End of traversing. *Verdi* : End of traversing.
------- Step 1: Configure Thermometer Regs ------- ------- Step 1: read Thermometer Regs -------
[ 775170000] Byte 0: 0x20 [1035750000] Packet (32-bit): 0x20260406
[ 862030000] Byte 1: 0x26 [1730150000] Packet (32-bit): 0x000003e8
[ 948890000] Byte 2: 0x04 [2424550000] Packet (32-bit): 0x025800a0
[ 1035750000] Byte 3: 0x06 [3118950000] Packet (32-bit): 0x0000c350
[ 1035750000] Packet (32-bit): 0x20260406
[ 1469570000] Byte 0: 0x00
[ 1556430000] Byte 1: 0x00
[ 1643290000] Byte 2: 0x03
[ 1730150000] Byte 3: 0xe8
[ 1730150000] Packet (32-bit): 0x000003e8
[ 2163970000] Byte 0: 0x02
[ 2250830000] Byte 1: 0x58
[ 2337690000] Byte 2: 0x00
[ 2424550000] Byte 3: 0xa0
[ 2424550000] Packet (32-bit): 0x025800a0
[ 2858370000] Byte 0: 0x00
[ 2945230000] Byte 1: 0x00
[ 3032090000] Byte 2: 0xc3
[ 3118950000] Byte 3: 0x50
[ 3118950000] Packet (32-bit): 0x0000c350
------- Step 2: Running Concurrent Tasks ------- ------- Step 2: Running Concurrent Tasks -------
[3474400000] Start generating signal: 400 kHz [3474400000] Start generating signal: 200 kHz
[ 3552770000] Byte 0: 0x00 [3813350000] Packet (32-bit): 0x00fff060
[ 3639630000] Byte 1: 0xff [10168800000] == Sending Read Request ==
[ 3726490000] Byte 2: 0xf0 [10507750000] Packet (32-bit): 0x00fff4d0
[ 3813350000] Byte 3: 0x60 [11210400000] == open report_en==
[ 3813350000] Packet (32-bit): 0x00fff060 [12252000000] == mode = 1 ==
[ 5474400000] TX: Sending Read Request during active reporting... [12590950000] Packet (32-bit): 0xaafff4d0
[ 6247170000] Byte 0: 0x00 [13343850000] Packet (32-bit): 0xaa0000c8
[ 6334030000] Byte 1: 0x00 [13474400000] Start generating signal: 300 kHz
[ 6420890000] Byte 2: 0x0b [14343870000] Packet (32-bit): 0xaa0000fc
[ 6507750000] Byte 3: 0x02 [15343890000] Packet (32-bit): 0xaa00012d
[ 6507750000] Packet (32-bit): 0x00000b02 [16343910000] Packet (32-bit): 0xaa00012c
[ 8330370000] Byte 0: 0xaa [17343930000] Packet (32-bit): 0xaa00012c
[ 8417230000] Byte 1: 0x00 [18343950000] Packet (32-bit): 0xaa00012c
[ 8504090000] Byte 2: 0x0b [19343970000] Packet (32-bit): 0xaa00012c
[ 8590950000] Byte 3: 0x02 [20343990000] Packet (32-bit): 0xaa00012c
[ 8590950000] Packet (32-bit): 0xaa000b02 [21344010000] Packet (32-bit): 0xaa00012c
[ 9054770000] Byte 0: 0x00 [22344030000] Packet (32-bit): 0xaa00012c
[ 9141630000] Byte 1: 0x00 [23344050000] Packet (32-bit): 0xaa00012d
[ 9228490000] Byte 2: 0x0b [24344070000] Packet (32-bit): 0xaa00012c
[ 9315350000] Byte 3: 0x02 [25344090000] Packet (32-bit): 0xaa00012c
[ 9315350000] Packet (32-bit): 0x00000b02 [26344110000] Packet (32-bit): 0xaa00012c
[27344130000] Packet (32-bit): 0xaa00012c
[28293600000] == cloese report_en==
[28632550000] Packet (32-bit): 0xaa00012c
[29356950000] Packet (32-bit): 0x0000012c
[33476396000] Start generating signal: 400 kHz
Test Done. Test Done.
$finish called from file "./TB.sv", line 221. $finish called from file "./TB.sv", line 227.
[RX] File closed at 17814400000 [RX] File closed at 67816396000
$finish at simulation time 17814400000 $finish at simulation time 67816396000
V C S S i m u l a t i o n R e p o r t V C S S i m u l a t i o n R e p o r t
Time: 17814400000 ps Time: 67816396000 ps
CPU Time: 1.630 seconds; Data structure size: 0.0Mb CPU Time: 4.650 seconds; Data structure size: 0.0Mb
Tue Apr 7 09:38:21 2026 Tue Apr 7 11:12:36 2026

BIN
sim/therm_chip_top/simv
View File

Binary file not shown.

14
sim/therm_chip_top/simv.daidir/.vcs.timestamp
View File

@ -118,7 +118,7 @@ HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2
HOSTTYPE=x86_64-linux HOSTTYPE=x86_64-linux
GROUP=cryo GROUP=cryo
GNOME_TERMINAL_SERVICE=:1.2258 GNOME_TERMINAL_SERVICE=:1.2258
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/33c4f0fe_b1af_4925_918d_f401e6285844 GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/c54e5016_f7fb_4a73_ae57_77787103df43
GNOME_SHELL_SESSION_MODE=classic GNOME_SHELL_SESSION_MODE=classic
GNOME_DESKTOP_SESSION_ID=this-is-deprecated GNOME_DESKTOP_SESSION_ID=this-is-deprecated
GENUS_HOME=/opt/cadence/GENUS152 GENUS_HOME=/opt/cadence/GENUS152
@ -149,12 +149,12 @@ CADENCE_DIR=/opt/cadence/IC618
AMS_ENABLE_NOISE=YES AMS_ENABLE_NOISE=YES
0 0
14 14
1775464866 ./TB.sv 1775531547 ./TB.sv
1775377742 ../../rtl/therm/pulse_cnt.v 1775526351 ../../rtl/therm/pulse_cnt.v
1775454778 ../../rtl/therm/digital_thermometer.v 1775526160 ../../rtl/therm/digital_thermometer.v
1774925224 ../../rtl/uart/uart_byte_tx.v 1774925224 ../../rtl/uart/uart_byte_tx.v
1775370228 ../../rtl/uart/uart_top_32bit.v 1775526524 ../../rtl/uart/uart_top_32bit.v
1775459928 ../../rtl/uart/uart_ctrl_sysreg.v 1775526452 ../../rtl/uart/uart_ctrl_sysreg.v
1774924538 ../../rtl/uart/uart_byte_rx.v 1774924538 ../../rtl/uart/uart_byte_rx.v
1775525487 ../../rtl/digital_top.v 1775525487 ../../rtl/digital_top.v
1774930574 ../../rtl/systemregfile/sirv_gnrl_dffs.v 1774930574 ../../rtl/systemregfile/sirv_gnrl_dffs.v
@ -168,5 +168,5 @@ AMS_ENABLE_NOISE=YES
1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so 1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so
1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so 1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so
1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so 1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so
1775525900 simv.daidir 1775531552 simv.daidir
-1 partitionlib -1 partitionlib

BIN
sim/therm_chip_top/simv.daidir/_131020_archive_1.so
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/_131039_archive_1.so
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/_131040_archive_1.so
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/_57246_archive_1.so Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/_57264_archive_1.so Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/_csrc0.so Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/_prev_archive_1.so Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/binmap.sdb
View File

Binary file not shown.

40
sim/therm_chip_top/simv.daidir/cgname.json
View File

@ -5,11 +5,11 @@
"module", "module",
7 7
], ],
"sirv_gnrl_dffl": [ "sirv_gnrl_dfflrs": [
"sirv_gnrl_dffl", "sirv_gnrl_dfflrs",
"BM4bj", "ZJgwY",
"module", "module",
4 2
], ],
"std": [ "std": [
"std", "std",
@ -17,17 +17,11 @@
"module", "module",
1 1
], ],
"sirv_gnrl_dffrs": [ "sirv_gnrl_ltch": [
"sirv_gnrl_dffrs", "sirv_gnrl_ltch",
"QHiet", "UTi0b",
"module", "module",
5 6
],
"sirv_gnrl_dfflrs": [
"sirv_gnrl_dfflrs",
"ZJgwY",
"module",
2
], ],
"sirv_gnrl_dfflrd": [ "sirv_gnrl_dfflrd": [
"sirv_gnrl_dfflrd", "sirv_gnrl_dfflrd",
@ -35,16 +29,22 @@
"module", "module",
3 3
], ],
"sirv_gnrl_ltch": [
"sirv_gnrl_ltch",
"UTi0b",
"module",
6
],
"...MASTER...": [ "...MASTER...": [
"SIM", "SIM",
"amcQw", "amcQw",
"module", "module",
8 8
],
"sirv_gnrl_dffl": [
"sirv_gnrl_dffl",
"BM4bj",
"module",
4
],
"sirv_gnrl_dffrs": [
"sirv_gnrl_dffrs",
"QHiet",
"module",
5
] ]
} }

BIN
sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz
View File

Binary file not shown.

2
sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db
View File

@ -5,5 +5,5 @@ PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27
export PYTHONPATH export PYTHONPATH
LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27
export LD_LIBRARY_PATH export LD_LIBRARY_PATH
/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_ik1qVk.xml.gz" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_DBCEI2.xml.gz" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
\mv "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" \mv "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db"

BIN
sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_DBCEI2.xml.gz Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_ik1qVk.xml.gz
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz
View File

Binary file not shown.

2
sim/therm_chip_top/simv.daidir/debug_dump/topmodules
View File

@ -1 +1 @@
<06>l<EFBFBD><13>c<EFBFBD><08>} <06>k<EFBFBD><12>b<EFBFBD><08>|

BIN
sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/elabmoddb.sdb
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/hslevel_level.sdb
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/indcall_14816.sdb Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/indcall_30603.sdb Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/indcall_34065.sdb Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/indcall_37441.sdb Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/indcall_39120.sdb Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/indcall_40348.sdb Normal file
View File

Binary file not shown.

BIN
sim/therm_chip_top/simv.daidir/indcall_41494.sdb Normal file
View File

Binary file not shown.

Some files were not shown because too many files have changed in this diff Show More