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ea448c3..0000000 --- a/sim/therm_chip_top/csrc/_csrc0.so +++ /dev/null @@ -1 +0,0 @@ -.//../simv.daidir//_csrc0.so \ No newline at end of file diff --git a/sim/therm_chip_top/csrc/_prev_archive_1.so b/sim/therm_chip_top/csrc/_prev_archive_1.so deleted file mode 120000 index 718cfb3..0000000 --- a/sim/therm_chip_top/csrc/_prev_archive_1.so +++ /dev/null @@ -1 +0,0 @@ -.//../simv.daidir//_prev_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/rtl/digital_top.v b/spi_thermometer_digital/rtl/digital_top.v new file mode 100644 index 0000000..f027161 --- /dev/null +++ b/spi_thermometer_digital/rtl/digital_top.v @@ -0,0 +1,92 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2026/04/03 22:01:15 +// Design Name: +// Module Name: digital_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module digital_top( + input clk, + input rst_n, + //spi_slave + input sclk, + input [4:0]cfgid, + input csn, + input mosi, + output miso, + output oen, + //pulse_counter + input sig_in + ); + +wire [31:0] wrdata; +wire [24:0] addr; +wire wren; +wire rden; +wire [31:0]rddata; + +wire [23:0] win_us; +wire cnt_vld; +wire [23:0]cnt_out; + + + // 实例化 DUT + spi_sys u_spi_sys ( + .clk (clk ), + .rst_n (rst_n ), + .cfgid (cfgid ), + .sclk (sclk ), + .csn (csn ), + .mosi (mosi ), + .miso (miso ), + .oen (oen ), + .wrdata (wrdata ), + .addr (addr ), + .wren (wren ), + .rden (rden ), + .rddata (rddata ) + ); + + system_regfile u_system_regfile ( + .clk (clk), + .rst_n (rst_n), + .wrdata (wrdata), + .wren (wren), + .rwaddr (addr), + .rden (rden), + .rddata (rddata), + // digital_thermometer + .win_us(win_us), + .pulse_cnt_out(cnt_out), + .pules_cnt_vld(cnt_vld) + ); + + + pulse_cnt #( + .CLK_FREQ(50_000_000) + ) u_pulse_cnt ( + .clk (clk), + .rst_n (rst_n), + .sig_in (sig_in), + .win_us (win_us), + .cnt_out(cnt_out), + .vld_out(cnt_vld) + ); + + +endmodule diff --git a/spi_thermometer_digital/rtl/spi/spi_sys.v b/spi_thermometer_digital/rtl/spi/spi_sys.v new file mode 100644 index 0000000..2769cdb --- /dev/null +++ b/spi_thermometer_digital/rtl/spi/spi_sys.v @@ -0,0 +1,292 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : spi_sys.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-04-13 PWY SPI BUS for System +// 0.2 2024-06-24 PWY {spi_dout[31:0],1'b0} -> {spi_dout[30:0],1'b0} +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +//-----------------------------Spi Frame------------------------------------------------------------------------------------- +////MSB------------->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>..............................................>>>>>>>>------->LSB +///|<-----------MSB 32 bits------------------->||<---------Second 32-bit---->||<-------x 32-bit---->||<-------n 32-bit---->| +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// | 31 || 30:6 || 5:1 || 0 || 31:0 || ...... || 31:0 | +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// | wnr || addr[24:0] || CHIPID ||resv || data[31:0] || ...... || data[31:0] | +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +//-----------------------------Spi Frame------------------------------------------------------------------------------------- + + +module spi_sys ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //cfg ID + ,input [4 :0] cfgid //ID number for the entire chip + //spi port + ,input sclk // Spi Clock + ,input csn // Spi Chip Select active low + ,input mosi // Spi Mosi + ,output miso // Spi Miso + ,output oen // Spi Miso output enable + + ,output [31:0] wrdata //write data to sram + ,output [24:0] addr //sram address + ,output wren //write enable sram + ,output rden //rden enable sram + ,input [31:0] rddata //read data from sram + +); + +localparam IDLE = 2'b00, + RECVCMD = 2'b01, + WRITE = 2'b10, + READ = 2'b11; +//----------------------------------------------------------------------- +//SPI module reset processing +//----------------------------------------------------------------------- +//spi_rstn +//wire spi_rstn; +//assign spi_rstn = rst_n & (~csn); + +////////////////////////////////////////////////////////////////////////// +//capture the sck +////////////////////////////////////////////////////////////////////////// +wire [2:0] sclk_reg; +//sync sclk to the main clock using a 3-bits shift register +sirv_gnrl_dffrs #(3) sclk_reg_dffrs ({sclk_reg[1:0],sclk}, sclk_reg, clk, rst_n); + +//sclk's rising edges +wire sclk_p = (sclk_reg[2:1] == 2'b01); + +//sclk's falling edges +//assign sclk_n = (sclk_reg[2:1] == 2'b10); + +////////////////////////////////////////////////////////////////////////// +//capture the csn +////////////////////////////////////////////////////////////////////////// +wire [2:0] csn_reg; +//sync csn to the main clock using a 2-bits shift register + +sirv_gnrl_dffrs #(3) csn_reg_dffrs ({csn_reg[1:0],csn}, csn_reg, clk, rst_n); +// csn is active low +wire csn_active = ~csn_reg[1]; + +//csn's rising edges +wire csn_p = (csn_reg[2:1] == 2'b01); + +//csn's falling edges +wire csn_n = (csn_reg[2:1] == 2'b10); + +////////////////////////////////////////////////////////////////////////// +//capture the mosi +////////////////////////////////////////////////////////////////////////// +wire [1:0] mosi_reg; +//sync mosi to the main clock using a 2-bits shift register + +sirv_gnrl_dffr #(2) mosi_reg_dffr ({mosi_reg[0],mosi}, mosi_reg, clk, rst_n); +//mosi_data +wire mosi_data = mosi_reg[1]; + +////////////////////////////////////////////////////////////////////////// +//cnt +////////////////////////////////////////////////////////////////////////// +wire [4:0] cnt_c; +//add_cnt +wire add_cnt = sclk_p && csn_active; +//end_cnt +wire end_cnt = (add_cnt && (cnt_c == 5'd31)) | csn_p; + +wire [4:0] cnt_n = end_cnt ? 5'h0 : + add_cnt ? cnt_c + 5'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(5) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////// +//SPI data sample +/////////////////////////////////////////////////////////////////////// + +generate + genvar i; + wire [31:0] recv_vld ; + wire [31:0] spi_din ; + for(i=0;i<32;i=i+1) begin: spi_sys_recv + assign recv_vld[i] = add_cnt & (cnt_c == i ); + sirv_gnrl_dfflr #(1) spi_din_dfflr (recv_vld[i], mosi_data, spi_din[31-i], clk, rst_n); + end +endgenerate + + +wire [1:0] state_c; +wire [1:0] state_n; + + +/////////////////////////////////////////////////////////////////////// +//init_addr capture +/////////////////////////////////////////////////////////////////////// +wire [24:0] initaddr; +wire initaddr_vld = (state_c == RECVCMD ) & add_cnt && (cnt_c == 5'd26); +wire [1:0] initaddr_vld_r; +sirv_gnrl_dffr #(2) initaddr_vld_r_dffr ({initaddr_vld_r[0],initaddr_vld}, initaddr_vld_r, clk, rst_n); + +sirv_gnrl_dfflr #(25) initaddr_dfflr (initaddr_vld_r[0], spi_din[30:6], initaddr, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//CMD capture +/////////////////////////////////////////////////////////////////////// +wire cmd ; +sirv_gnrl_dfflr #(1) cmd_dfflr ( initaddr_vld_r[0], spi_din[31], cmd, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//CHIPID capture +/////////////////////////////////////////////////////////////////////// +wire [4:0] chipid; +wire [1:0] chipid_vld_r; +wire chipid_vld = (state_c == RECVCMD ) & add_cnt & (cnt_c == 5'd30); +//register cmd_vld to align it with cmd +sirv_gnrl_dffr #(2) chipid_vld_r_dffr ({chipid_vld_r[0],chipid_vld}, chipid_vld_r, clk, rst_n); + +sirv_gnrl_dfflr #(5) chipid_dfflr (chipid_vld_r[0], spi_din[5:1], chipid, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//ID matching determination +/////////////////////////////////////////////////////////////////////// +wire chipid_match = (chipid == cfgid); +wire chipid_dismatch = (chipid != cfgid); + + + +/////////////////////////////////////////////////////////////////////// +//SPI Module State Machine +/////////////////////////////////////////////////////////////////////// + +//Generating jump conditions for state machines +wire ilde2recvcmd = (state_c == IDLE ) && csn_active && csn_n ; +wire recvcmd2ilde = (state_c == RECVCMD ) && chipid_dismatch & end_cnt; +wire recvcmd2write = (state_c == RECVCMD ) && chipid_match && ~cmd & end_cnt; +wire recvcmd2read = (state_c == RECVCMD ) && chipid_match && cmd & end_cnt; +wire write2idle = (state_c == WRITE ) && csn_p; +wire read2idle = (state_c == READ ) && csn_p; + +//The first section of the state machine +//state_c +sirv_gnrl_dffr #(2) state_c_dffr (state_n, state_c, clk, rst_n); + +//state_n +assign state_n = ((state_c == IDLE ) && ilde2recvcmd ) ? RECVCMD : + ((state_c == RECVCMD ) && recvcmd2ilde ) ? IDLE : + ((state_c == RECVCMD ) && recvcmd2write ) ? WRITE : + ((state_c == RECVCMD ) && recvcmd2read ) ? READ : + ((state_c == WRITE ) && write2idle ) ? IDLE : + ((state_c == READ ) && read2idle ) ? IDLE : + state_c ; + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//Address generation for read and write operations +//The address to be used for updating in the next +//27 clock cycles in the read-write state +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire second_falling; +wire second_falling_w = (state_c == WRITE); +sirv_gnrl_dfflr #(1) second_falling_dfflr (end_cnt ,second_falling_w, second_falling, clk, rst_n); + +wire addr_update = ((state_c == READ) | ((state_c == WRITE) & second_falling)) & add_cnt & (cnt_c == 5'd27); +wire [24:0] addr_c; + +wire [24:0] addr_n = ilde2recvcmd ? 25'd0 : + initaddr_vld_r[1] ? initaddr : + addr_update ? addr_c + 25'd4 : + addr_c ; + +sirv_gnrl_dffr #(25) addr_c_dffr (addr_n, addr_c, clk, rst_n); + +assign addr = addr_c; + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//Write data and write signals generation +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire wren_r; + +wire wren_w = (state_c == WRITE) & add_cnt & (cnt_c == 5'd31); +//wdata +sirv_gnrl_dfflr #(32) wrdata_dfflr (wren_r, spi_din[31:0], wrdata, clk, rst_n); +//wren_r + +sirv_gnrl_dffr #(1) wren_r_dffr (wren_w, wren_r, clk, rst_n); + +//wren +sirv_gnrl_dffr #(1) wren_dffr (wren_r, wren, clk, rst_n); + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//read signals generation +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +wire rden_w = chipid_match & cmd & add_cnt & (cnt_c == 5'd28); +sirv_gnrl_dffr #(1) rden_dffr (rden_w, rden, clk, rst_n); + +//Read data register +wire rddata_vld = cmd & add_cnt & (cnt_c == 5'd30); +wire [31:0] rddata_reg; +sirv_gnrl_dfflr #(32) rddata_reg_dfflr (rddata_vld, rddata[31:0], rddata_reg, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI send data update +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [31:0] spi_dout ; +wire update_flag = cmd & add_cnt & (cnt_c == 5'd31); + +wire [31:0] rddata_sr = update_flag ? rddata_reg[31:0] : + ((state_c == READ) & add_cnt) ? {spi_dout[30:0],1'b0} : //M 2024-06-24 + spi_dout ; + +sirv_gnrl_dffr #(32) spi_dout_dffr (rddata_sr, spi_dout, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI send data +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +assign miso = spi_dout[31]; + + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI output enable +/////////////////////////////////////////////////////////////////////////////////////////////////////// +sirv_gnrl_dffrs #(1) oen_dffr (~(state_c == READ), oen, clk, rst_n); + +endmodule + + diff --git a/rtl/systemregfile/sirv_gnrl_dffs.v b/spi_thermometer_digital/rtl/systemregfile/sirv_gnrl_dffs.v similarity index 95% rename from rtl/systemregfile/sirv_gnrl_dffs.v rename to spi_thermometer_digital/rtl/systemregfile/sirv_gnrl_dffs.v index 2448ae7..6526cd4 100644 --- a/rtl/systemregfile/sirv_gnrl_dffs.v +++ b/spi_thermometer_digital/rtl/systemregfile/sirv_gnrl_dffs.v @@ -1,342 +1,342 @@ - /* - Copyright 2018-2020 Nuclei System Technology, Inc. - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - */ - - - -//===================================================================== -// -// Designer : Bob Hu -// -// Description: -// All of the general DFF and Latch modules -// -// ==================================================================== - -// - - -// -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is 1 -// -// =========================================================================== -`define DISABLE_SV_ASSERTION -`define dly #0.2 -module sirv_gnrl_dfflrs # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLRS_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b1}}; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is 0 -// -// =========================================================================== - -module sirv_gnrl_dfflr # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLR_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b0}}; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule - -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is input -// -// =========================================================================== - -module sirv_gnrl_dfflrd # ( - parameter DW = 32 -) ( - input [DW-1:0] init, - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLR_PROC - if (rst_n == 1'b0) - qout_r <= init; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule - -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable, no reset -// -// =========================================================================== - -module sirv_gnrl_dffl # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk -); - -reg [DW-1:0] qout_r; - -always @(posedge clk) -begin : DFFL_PROC - if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Reset, no load-enable -// Default reset value is 1 -// -// =========================================================================== - -module sirv_gnrl_dffrs # ( - parameter DW = 32 -) ( - - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFRS_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b1}}; - else - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Reset, no load-enable -// Default reset value is 0 -// -// =========================================================================== - -module sirv_gnrl_dffr # ( - parameter DW = 32 -) ( - - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFR_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b0}}; - else - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -endmodule -// =========================================================================== -// -// Description: -// Verilog module for general latch -// -// =========================================================================== - -module sirv_gnrl_ltch # ( - parameter DW = 32 -) ( - - //input test_mode, - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout -); - -reg [DW-1:0] qout_r; - -always @ * -begin : LTCH_PROC - if (lden == 1'b1) - qout_r <= dnxt; -end - -//assign qout = test_mode ? dnxt : qout_r; -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -always_comb -begin - CHECK_THE_X_VALUE: - assert (lden !== 1'bx) - else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); -end - -//synopsys translate_on -`endif//} -`endif//} - - -endmodule - -// module sirv_gnrl_edffr #(parameter type T = logic) ( -// input T dnxt, -// output T qout, -// input clk, rst_n -// ); - -// T qout_r; - -// always_ff @(posedge clk or negedge rst_n) begin -// if (!rst_n) qout_r <= T'('0); -// else qout_r <= `dly dnxt; -// end -// assign qout = qout_r; -// endmodule - + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// All of the general DFF and Latch modules +// +// ==================================================================== + +// + + +// +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 1 +// +// =========================================================================== +`define DISABLE_SV_ASSERTION +`define dly #0.2 +module sirv_gnrl_dfflrs # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dfflr # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is input +// +// =========================================================================== + +module sirv_gnrl_dfflrd # ( + parameter DW = 32 +) ( + input [DW-1:0] init, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= init; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable, no reset +// +// =========================================================================== + +module sirv_gnrl_dffl # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk +); + +reg [DW-1:0] qout_r; + +always @(posedge clk) +begin : DFFL_PROC + if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 1 +// +// =========================================================================== + +module sirv_gnrl_dffrs # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dffr # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module for general latch +// +// =========================================================================== + +module sirv_gnrl_ltch # ( + parameter DW = 32 +) ( + + //input test_mode, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout +); + +reg [DW-1:0] qout_r; + +always @ * +begin : LTCH_PROC + if (lden == 1'b1) + qout_r <= dnxt; +end + +//assign qout = test_mode ? dnxt : qout_r; +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +always_comb +begin + CHECK_THE_X_VALUE: + assert (lden !== 1'bx) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); +end + +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// module sirv_gnrl_edffr #(parameter type T = logic) ( +// input T dnxt, +// output T qout, +// input clk, rst_n +// ); + +// T qout_r; + +// always_ff @(posedge clk or negedge rst_n) begin +// if (!rst_n) qout_r <= T'('0); +// else qout_r <= `dly dnxt; +// end +// assign qout = qout_r; +// endmodule + diff --git a/spi_thermometer_digital/rtl/systemregfile/systemregfile.v b/spi_thermometer_digital/rtl/systemregfile/systemregfile.v new file mode 100644 index 0000000..3cb78ed --- /dev/null +++ b/spi_thermometer_digital/rtl/systemregfile/systemregfile.v @@ -0,0 +1,111 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Add a new register: + +// SECTION A: Add localparam ADDR_NEW = 16'hXX;. + +// SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;. + +// SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);. + +// SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);. + +// SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block. + +// SECTION G: Map reg_new to the module's output ports. +//-FHDR-------------------------------------------------------------------------------------------------------- + +module system_regfile ( + // [BLOCK 0] System and Bus Interface + input clk, + input rst_n, + input [31:0] wrdata, + input wren, + input [24:0] rwaddr, + input rden, + output [31:0] rddata, + + output [23:0]win_us, + input [23:0]pulse_cnt_out, + input pules_cnt_vld + +); + +// ============================================================================= +// [SECTION A] Address Offset Definition (Localparams) +// ============================================================================= + localparam TESTR = 16'h00, DATER = 16'h04; + localparam WIN_TIME_R =16'h08 ; + localparam RESULT_R =16'h0c ; + + +// ============================================================================= +// [SECTION B] Internal Wire Declaration (Wires) +// ============================================================================= + +// Register selection signals (Enable Wires) + wire sel_testr, sel_dater; + wire sel_win_time, sel_result; + +// Write enable signals (Write Enable Wires) + wire we_testr, we_dater; + wire we_win_time; + + +// Register storage wires (Storage Wires) + wire [31:0] testr, dater; + wire [23:0] win_time_r, result_r; +// ============================================================================= +// [SECTION C] Decoding Logic (Decoding) +// ============================================================================= + assign sel_testr = (rwaddr[15:0] == TESTR ); + assign sel_dater = (rwaddr[15:0] == DATER ); + assign sel_win_time = (rwaddr[15:0] == WIN_TIME_R ); + assign sel_result = (rwaddr[15:0] == RESULT_R ); + +// Write enable allocation +assign we_testr = sel_testr & wren; +assign we_dater = sel_dater & wren; +assign we_win_time = sel_win_time & wren; + + +// ============================================================================= +// [SECTION D] Register Instantiation (Storage Implementation) +// ============================================================================= + +// --- General and Test Registers --- +sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n); +sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n); + +// --- Thermometer Functional Registers --- +sirv_gnrl_dfflrd #(24) win_time_dff (32'h00_03E8, we_win_time, wrdata, win_time_r, clk, rst_n); + +sirv_gnrl_dfflr #(24) result_dff (pules_cnt_vld,pulse_cnt_out,result_r, clk, rst_n); + +// ============================================================================= +// [SECTION E] Special Business Logic (Business Logic) +// ============================================================================= + +// LVDS Real-time status register +// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n); + +// ============================================================================= +// [SECTION F] Readback Logic (Readback Mux) +// ============================================================================= +reg [31:0] rddata_reg; +always @(*) begin + rddata_reg = 32'b0; + if (sel_testr) rddata_reg = testr; + else if (sel_dater) rddata_reg = dater; + else if (sel_win_time) rddata_reg = {8'b0,win_time_r}; + else if (sel_result) rddata_reg = {8'b0,result_r}; +end + + sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n); + +// ============================================================================= +// [SECTION G] Output Mapping (Output Assignments) +// ============================================================================= + assign win_us = win_time_r; + + +endmodule \ No newline at end of file diff --git a/rtl/therm/pulse_cnt.v b/spi_thermometer_digital/rtl/therm/pulse_cnt.v similarity index 100% rename from rtl/therm/pulse_cnt.v rename to spi_thermometer_digital/rtl/therm/pulse_cnt.v diff --git a/sim/therm_chip_top/Makefile b/spi_thermometer_digital/sim/therm_chip_top/Makefile similarity index 100% rename from sim/therm_chip_top/Makefile rename to spi_thermometer_digital/sim/therm_chip_top/Makefile diff --git a/sim/therm_chip_top/TB.sv b/spi_thermometer_digital/sim/therm_chip_top/TB.sv similarity index 98% rename from sim/therm_chip_top/TB.sv rename to spi_thermometer_digital/sim/therm_chip_top/TB.sv index 376c288..6dc8678 100644 --- a/sim/therm_chip_top/TB.sv +++ b/spi_thermometer_digital/sim/therm_chip_top/TB.sv @@ -18,10 +18,10 @@ module TB(); // Clock Generation initial clk = 0; always #(CLK_PERIOD/2) clk = ~clk; - initial begin - $fsdbDumpfile("wave.fsdb"); - $fsdbDumpvars(); - end + // initial begin + // $fsdbDumpfile("wave.fsdb"); + // $fsdbDumpvars(); + // end // ========================================== // DUT Instantiation // ========================================== diff --git a/sim/therm_chip_top/compile.log b/spi_thermometer_digital/sim/therm_chip_top/compile.log similarity index 100% rename from sim/therm_chip_top/compile.log rename to spi_thermometer_digital/sim/therm_chip_top/compile.log diff --git a/sim/therm_chip_top/coverage/simv.vdb/.cmoptions b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.cmoptions similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/.cmoptions rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.cmoptions diff --git a/sim/therm_chip_top/coverage/simv.vdb/.mode64 b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.mode64 similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/.mode64 rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.mode64 diff --git a/sim/therm_chip_top/coverage/simv.vdb/.vdb_version b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.vdb_version similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/.vdb_version rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.vdb_version diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.exclude.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.exclude.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.exclude.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.exclude.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml b/spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml similarity index 100% rename from sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml rename to spi_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml diff --git a/sim/therm_chip_top/csrc/Makefile b/spi_thermometer_digital/sim/therm_chip_top/csrc/Makefile similarity index 100% rename from sim/therm_chip_top/csrc/Makefile rename to spi_thermometer_digital/sim/therm_chip_top/csrc/Makefile diff --git a/sim/therm_chip_top/csrc/Makefile.hsopt b/spi_thermometer_digital/sim/therm_chip_top/csrc/Makefile.hsopt similarity index 100% rename from sim/therm_chip_top/csrc/Makefile.hsopt rename to spi_thermometer_digital/sim/therm_chip_top/csrc/Makefile.hsopt diff --git a/sim/therm_chip_top/csrc/SIM_l.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/SIM_l.o similarity index 100% rename from sim/therm_chip_top/csrc/SIM_l.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/SIM_l.o diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_131020_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_131020_archive_1.so new file mode 100644 index 0000000..3e06bf7 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_131020_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131020_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_131039_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_131039_archive_1.so new file mode 100644 index 0000000..bcc14ae --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_131039_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131039_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_131040_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_131040_archive_1.so new file mode 100644 index 0000000..cd1589e --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_131040_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131040_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_14790_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_14790_archive_1.so new file mode 100644 index 0000000..44ea7b8 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_14790_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_14790_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_14816_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_14816_archive_1.so new file mode 100644 index 0000000..55f5635 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_14816_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_14816_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_26119_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_26119_archive_1.so new file mode 100644 index 0000000..545c5ef --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_26119_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_26119_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_30584_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_30584_archive_1.so new file mode 100644 index 0000000..9133c58 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_30584_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_30584_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_30603_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_30603_archive_1.so new file mode 100644 index 0000000..fcc4502 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_30603_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_30603_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_34047_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_34047_archive_1.so new file mode 100644 index 0000000..9e97f51 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_34047_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_34047_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_34065_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_34065_archive_1.so new file mode 100644 index 0000000..0b40fdc --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_34065_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_34065_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_37423_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_37423_archive_1.so new file mode 100644 index 0000000..2f072cf --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_37423_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_37423_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_37441_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_37441_archive_1.so new file mode 100644 index 0000000..52cc95a --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_37441_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_37441_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_39101_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_39101_archive_1.so new file mode 100644 index 0000000..4566c55 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_39101_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_39101_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_39120_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_39120_archive_1.so new file mode 100644 index 0000000..8b2b889 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_39120_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_39120_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_40330_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_40330_archive_1.so new file mode 100644 index 0000000..7b4dd8a --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_40330_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_40330_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_40348_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_40348_archive_1.so new file mode 100644 index 0000000..88aeb42 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_40348_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_40348_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_41475_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_41475_archive_1.so new file mode 100644 index 0000000..5a8ef9e --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_41475_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_41475_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_41494_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_41494_archive_1.so new file mode 100644 index 0000000..12344ab --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_41494_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_41494_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_42301_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_42301_archive_1.so new file mode 100644 index 0000000..c4d6de0 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_42301_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_42301_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_42320_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_42320_archive_1.so new file mode 100644 index 0000000..f76c884 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_42320_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_42320_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_43406_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_43406_archive_1.so new file mode 100644 index 0000000..c8e868f --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_43406_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_43406_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_43443_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_43443_archive_1.so new file mode 100644 index 0000000..8cf3853 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_43443_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_43443_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_45855_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_45855_archive_1.so new file mode 100644 index 0000000..bfa54f9 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_45855_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_45855_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_45891_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_45891_archive_1.so new file mode 100644 index 0000000..72977dc --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_45891_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_45891_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_50099_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_50099_archive_1.so new file mode 100644 index 0000000..a848620 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_50099_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_50099_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_50120_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_50120_archive_1.so new file mode 100644 index 0000000..ade18f8 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_50120_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_50120_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_52045_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_52045_archive_1.so new file mode 100644 index 0000000..353d2a6 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_52045_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_52045_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_52081_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_52081_archive_1.so new file mode 100644 index 0000000..c9933c7 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_52081_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_52081_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_53444_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_53444_archive_1.so new file mode 100644 index 0000000..daccfbd --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_53444_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_53444_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_53462_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_53462_archive_1.so new file mode 100644 index 0000000..805c65a --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_53462_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_53462_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_54606_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_54606_archive_1.so new file mode 100644 index 0000000..ac3eb90 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_54606_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_54606_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_54624_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_54624_archive_1.so new file mode 100644 index 0000000..d72738e --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_54624_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_54624_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_56094_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_56094_archive_1.so new file mode 100644 index 0000000..619f329 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_56094_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_56094_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_56112_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_56112_archive_1.so new file mode 100644 index 0000000..3868b49 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_56112_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_56112_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_57246_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_57246_archive_1.so new file mode 100644 index 0000000..22f611f --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_57246_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_57246_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_57264_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_57264_archive_1.so new file mode 100644 index 0000000..9a088e4 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_57264_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_57264_archive_1.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_csrc0.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_csrc0.so new file mode 100644 index 0000000..ea448c3 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_csrc0.so @@ -0,0 +1 @@ +.//../simv.daidir//_csrc0.so \ No newline at end of file diff --git a/spi_thermometer_digital/sim/therm_chip_top/csrc/_prev_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/csrc/_prev_archive_1.so new file mode 100644 index 0000000..718cfb3 --- /dev/null +++ b/spi_thermometer_digital/sim/therm_chip_top/csrc/_prev_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_prev_archive_1.so \ No newline at end of file diff --git a/sim/therm_chip_top/csrc/_prev_cginfo.json b/spi_thermometer_digital/sim/therm_chip_top/csrc/_prev_cginfo.json similarity index 100% rename from sim/therm_chip_top/csrc/_prev_cginfo.json rename to spi_thermometer_digital/sim/therm_chip_top/csrc/_prev_cginfo.json diff --git a/sim/therm_chip_top/csrc/_vcs_pli_stub_.c b/spi_thermometer_digital/sim/therm_chip_top/csrc/_vcs_pli_stub_.c similarity index 100% rename from sim/therm_chip_top/csrc/_vcs_pli_stub_.c rename to spi_thermometer_digital/sim/therm_chip_top/csrc/_vcs_pli_stub_.c diff --git a/sim/therm_chip_top/csrc/_vcs_pli_stub_.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/_vcs_pli_stub_.o similarity index 100% rename from sim/therm_chip_top/csrc/_vcs_pli_stub_.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/_vcs_pli_stub_.o diff --git a/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a b/spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a similarity index 100% rename from sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a rename to spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a diff --git a/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a.info b/spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a.info similarity index 100% rename from sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a.info rename to spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a.info diff --git a/sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a b/spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a similarity index 100% rename from sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a rename to spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a diff --git a/sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a.info b/spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a.info similarity index 100% rename from sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a.info rename to spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57264_archive_1.a.info diff --git a/sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a b/spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a similarity index 100% rename from sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a rename to spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a diff --git a/sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a.info b/spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a.info similarity index 100% rename from sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a.info rename to spi_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_prev_archive_1.a.info diff --git a/sim/therm_chip_top/csrc/cgincr.sdb b/spi_thermometer_digital/sim/therm_chip_top/csrc/cgincr.sdb similarity index 100% rename from sim/therm_chip_top/csrc/cgincr.sdb rename to spi_thermometer_digital/sim/therm_chip_top/csrc/cgincr.sdb diff --git a/sim/therm_chip_top/csrc/cginfo.json b/spi_thermometer_digital/sim/therm_chip_top/csrc/cginfo.json similarity index 100% rename from sim/therm_chip_top/csrc/cginfo.json rename to spi_thermometer_digital/sim/therm_chip_top/csrc/cginfo.json diff --git a/sim/therm_chip_top/csrc/cgproc.57246.json b/spi_thermometer_digital/sim/therm_chip_top/csrc/cgproc.57246.json similarity index 100% rename from sim/therm_chip_top/csrc/cgproc.57246.json rename to spi_thermometer_digital/sim/therm_chip_top/csrc/cgproc.57246.json diff --git a/sim/therm_chip_top/csrc/cgproc.57264.json b/spi_thermometer_digital/sim/therm_chip_top/csrc/cgproc.57264.json similarity index 100% rename from sim/therm_chip_top/csrc/cgproc.57264.json rename to spi_thermometer_digital/sim/therm_chip_top/csrc/cgproc.57264.json diff --git a/sim/therm_chip_top/csrc/cgproc.57265.json b/spi_thermometer_digital/sim/therm_chip_top/csrc/cgproc.57265.json similarity index 100% rename from sim/therm_chip_top/csrc/cgproc.57265.json rename to spi_thermometer_digital/sim/therm_chip_top/csrc/cgproc.57265.json diff --git a/sim/therm_chip_top/csrc/filelist b/spi_thermometer_digital/sim/therm_chip_top/csrc/filelist similarity index 100% rename from sim/therm_chip_top/csrc/filelist rename to spi_thermometer_digital/sim/therm_chip_top/csrc/filelist diff --git a/sim/therm_chip_top/csrc/filelist.cu b/spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.cu similarity index 100% rename from sim/therm_chip_top/csrc/filelist.cu rename to spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.cu diff --git a/sim/therm_chip_top/csrc/filelist.dpi b/spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.dpi similarity index 100% rename from sim/therm_chip_top/csrc/filelist.dpi rename to spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.dpi diff --git a/sim/therm_chip_top/csrc/filelist.hsopt b/spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt similarity index 100% rename from sim/therm_chip_top/csrc/filelist.hsopt rename to spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt diff --git a/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs b/spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs similarity index 100% rename from sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs rename to spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs diff --git a/sim/therm_chip_top/csrc/filelist.hsopt.objs b/spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.objs similarity index 100% rename from sim/therm_chip_top/csrc/filelist.hsopt.objs rename to spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.objs diff --git a/sim/therm_chip_top/csrc/filelist.pli b/spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.pli similarity index 100% rename from sim/therm_chip_top/csrc/filelist.pli rename to spi_thermometer_digital/sim/therm_chip_top/csrc/filelist.pli diff --git a/sim/therm_chip_top/csrc/hsim/hsim.sdb b/spi_thermometer_digital/sim/therm_chip_top/csrc/hsim/hsim.sdb similarity index 100% rename from sim/therm_chip_top/csrc/hsim/hsim.sdb rename to spi_thermometer_digital/sim/therm_chip_top/csrc/hsim/hsim.sdb diff --git a/sim/therm_chip_top/csrc/import_dpic.h b/spi_thermometer_digital/sim/therm_chip_top/csrc/import_dpic.h similarity index 100% rename from sim/therm_chip_top/csrc/import_dpic.h rename to spi_thermometer_digital/sim/therm_chip_top/csrc/import_dpic.h diff --git a/sim/therm_chip_top/csrc/objs/amcQw_d.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/objs/amcQw_d.o similarity index 100% rename from sim/therm_chip_top/csrc/objs/amcQw_d.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/objs/amcQw_d.o diff --git a/sim/therm_chip_top/csrc/pre.cgincr.sdb b/spi_thermometer_digital/sim/therm_chip_top/csrc/pre.cgincr.sdb similarity index 100% rename from sim/therm_chip_top/csrc/pre.cgincr.sdb rename to spi_thermometer_digital/sim/therm_chip_top/csrc/pre.cgincr.sdb diff --git a/sim/therm_chip_top/csrc/product_timestamp b/spi_thermometer_digital/sim/therm_chip_top/csrc/product_timestamp similarity index 100% rename from sim/therm_chip_top/csrc/product_timestamp rename to spi_thermometer_digital/sim/therm_chip_top/csrc/product_timestamp diff --git a/sim/therm_chip_top/csrc/rmapats.c b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats.c similarity index 100% rename from sim/therm_chip_top/csrc/rmapats.c rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats.c diff --git a/sim/therm_chip_top/csrc/rmapats.h b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats.h similarity index 100% rename from sim/therm_chip_top/csrc/rmapats.h rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats.h diff --git a/sim/therm_chip_top/csrc/rmapats.m b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats.m similarity index 100% rename from sim/therm_chip_top/csrc/rmapats.m rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats.m diff --git a/sim/therm_chip_top/csrc/rmapats.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats.o similarity index 100% rename from sim/therm_chip_top/csrc/rmapats.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats.o diff --git a/sim/therm_chip_top/csrc/rmapats_mop.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats_mop.o similarity index 100% rename from sim/therm_chip_top/csrc/rmapats_mop.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmapats_mop.o diff --git a/sim/therm_chip_top/csrc/rmar.c b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmar.c similarity index 100% rename from sim/therm_chip_top/csrc/rmar.c rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmar.c diff --git a/sim/therm_chip_top/csrc/rmar.h b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmar.h similarity index 100% rename from sim/therm_chip_top/csrc/rmar.h rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmar.h diff --git a/sim/therm_chip_top/csrc/rmar.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmar.o similarity index 100% rename from sim/therm_chip_top/csrc/rmar.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmar.o diff --git a/sim/therm_chip_top/csrc/rmar0.h b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmar0.h similarity index 100% rename from sim/therm_chip_top/csrc/rmar0.h rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmar0.h diff --git a/sim/therm_chip_top/csrc/rmar_llvm_0_0.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_0.o similarity index 100% rename from sim/therm_chip_top/csrc/rmar_llvm_0_0.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_0.o diff --git a/sim/therm_chip_top/csrc/rmar_llvm_0_1.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_1.o similarity index 100% rename from sim/therm_chip_top/csrc/rmar_llvm_0_1.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_1.o diff --git a/sim/therm_chip_top/csrc/rmar_nd.o b/spi_thermometer_digital/sim/therm_chip_top/csrc/rmar_nd.o similarity index 100% rename from sim/therm_chip_top/csrc/rmar_nd.o rename to spi_thermometer_digital/sim/therm_chip_top/csrc/rmar_nd.o diff --git a/sim/therm_chip_top/csrc/vcspieces.incr b/spi_thermometer_digital/sim/therm_chip_top/csrc/vcspieces.incr similarity index 100% rename from sim/therm_chip_top/csrc/vcspieces.incr rename to spi_thermometer_digital/sim/therm_chip_top/csrc/vcspieces.incr diff --git a/sim/therm_chip_top/filelist_vlg.f b/spi_thermometer_digital/sim/therm_chip_top/filelist_vlg.f similarity index 100% rename from sim/therm_chip_top/filelist_vlg.f rename to spi_thermometer_digital/sim/therm_chip_top/filelist_vlg.f diff --git a/sim/therm_chip_top/novas.conf b/spi_thermometer_digital/sim/therm_chip_top/novas.conf similarity index 100% rename from sim/therm_chip_top/novas.conf rename to spi_thermometer_digital/sim/therm_chip_top/novas.conf diff --git a/sim/therm_chip_top/novas.rc b/spi_thermometer_digital/sim/therm_chip_top/novas.rc similarity index 100% rename from sim/therm_chip_top/novas.rc rename to spi_thermometer_digital/sim/therm_chip_top/novas.rc diff --git a/sim/therm_chip_top/novas_dump.log b/spi_thermometer_digital/sim/therm_chip_top/novas_dump.log similarity index 100% rename from sim/therm_chip_top/novas_dump.log rename to spi_thermometer_digital/sim/therm_chip_top/novas_dump.log diff --git a/sim/therm_chip_top/rx_data.txt b/spi_thermometer_digital/sim/therm_chip_top/rx_data.txt similarity index 100% rename from sim/therm_chip_top/rx_data.txt rename to spi_thermometer_digital/sim/therm_chip_top/rx_data.txt diff --git a/sim/therm_chip_top/sim.log b/spi_thermometer_digital/sim/therm_chip_top/sim.log similarity index 100% rename from sim/therm_chip_top/sim.log rename to spi_thermometer_digital/sim/therm_chip_top/sim.log diff --git a/sim/therm_chip_top/simv b/spi_thermometer_digital/sim/therm_chip_top/simv similarity index 100% rename from sim/therm_chip_top/simv rename to spi_thermometer_digital/sim/therm_chip_top/simv diff --git a/sim/therm_chip_top/simv.daidir/.daidir_complete b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/.daidir_complete similarity index 100% rename from sim/therm_chip_top/simv.daidir/.daidir_complete rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/.daidir_complete diff --git a/sim/therm_chip_top/simv.daidir/.normal_done b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/.normal_done similarity index 100% rename from sim/therm_chip_top/simv.daidir/.normal_done rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/.normal_done diff --git a/sim/therm_chip_top/simv.daidir/.vcs.timestamp b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/.vcs.timestamp similarity index 100% rename from sim/therm_chip_top/simv.daidir/.vcs.timestamp rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/.vcs.timestamp diff --git a/sim/therm_chip_top/simv.daidir/_57246_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/_57246_archive_1.so similarity index 100% rename from sim/therm_chip_top/simv.daidir/_57246_archive_1.so rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/_57246_archive_1.so diff --git a/sim/therm_chip_top/simv.daidir/_57264_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/_57264_archive_1.so similarity index 100% rename from sim/therm_chip_top/simv.daidir/_57264_archive_1.so rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/_57264_archive_1.so diff --git a/sim/therm_chip_top/simv.daidir/_csrc0.so b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/_csrc0.so similarity index 100% rename from sim/therm_chip_top/simv.daidir/_csrc0.so rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/_csrc0.so diff --git a/sim/therm_chip_top/simv.daidir/_prev_archive_1.so b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/_prev_archive_1.so similarity index 100% rename from sim/therm_chip_top/simv.daidir/_prev_archive_1.so rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/_prev_archive_1.so diff --git a/sim/therm_chip_top/simv.daidir/binmap.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/binmap.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/binmap.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/binmap.sdb diff --git a/sim/therm_chip_top/simv.daidir/build_db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/build_db similarity index 100% rename from sim/therm_chip_top/simv.daidir/build_db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/build_db diff --git a/sim/therm_chip_top/simv.daidir/cc/cc_bcode.db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_bcode.db similarity index 100% rename from sim/therm_chip_top/simv.daidir/cc/cc_bcode.db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_bcode.db diff --git a/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file similarity index 100% rename from sim/therm_chip_top/simv.daidir/cc/cc_dummy_file rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file diff --git a/sim/therm_chip_top/simv.daidir/cgname.json b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/cgname.json similarity index 100% rename from sim/therm_chip_top/simv.daidir/cgname.json rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/cgname.json diff --git a/sim/therm_chip_top/simv.daidir/covg_defs b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/covg_defs similarity index 100% rename from sim/therm_chip_top/simv.daidir/covg_defs rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/covg_defs diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/.version b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/.version similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/.version rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/.version diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/dumpcheck.db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dumpcheck.db similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/dumpcheck.db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dumpcheck.db diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_DBCEI2.xml.gz b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_DBCEI2.xml.gz similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_DBCEI2.xml.gz rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_DBCEI2.xml.gz diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/src_files_verilog b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/src_files_verilog similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/src_files_verilog rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/src_files_verilog diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/topmodules b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/topmodules similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/topmodules rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/topmodules diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb diff --git a/sim/therm_chip_top/simv.daidir/eblklvl.db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/eblklvl.db similarity index 100% rename from sim/therm_chip_top/simv.daidir/eblklvl.db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/eblklvl.db diff --git a/sim/therm_chip_top/simv.daidir/elabmoddb.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/elabmoddb.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/elabmoddb.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/elabmoddb.sdb diff --git a/sim/therm_chip_top/simv.daidir/external_functions b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/external_functions similarity index 100% rename from sim/therm_chip_top/simv.daidir/external_functions rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/external_functions diff --git a/sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb diff --git a/sim/therm_chip_top/simv.daidir/hslevel_level.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_level.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/hslevel_level.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_level.sdb diff --git a/sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb diff --git a/sim/therm_chip_top/simv.daidir/hsscan_cfg.dat b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/hsscan_cfg.dat similarity index 100% rename from sim/therm_chip_top/simv.daidir/hsscan_cfg.dat rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/hsscan_cfg.dat diff --git a/sim/therm_chip_top/simv.daidir/indcall.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_131020.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131020.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_131020.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131020.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_131039.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131039.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_131039.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131039.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_131040.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131040.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_131040.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131040.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_14816.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_14816.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_14816.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_14816.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_30603.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_30603.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_30603.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_30603.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_34065.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_34065.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_34065.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_34065.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_37441.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_37441.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_37441.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_37441.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_39120.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_39120.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_39120.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_39120.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_40348.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_40348.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_40348.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_40348.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_41494.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_41494.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_41494.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_41494.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_42320.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_42320.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_42320.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_42320.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_43443.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_43443.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_43443.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_43443.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_45891.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_45891.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_45891.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_45891.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_50120.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_50120.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_50120.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_50120.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_52081.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_52081.sdb similarity index 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spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_56112.sdb diff --git a/sim/therm_chip_top/simv.daidir/indcall_57264.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_57264.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/indcall_57264.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_57264.sdb diff --git a/sim/therm_chip_top/simv.daidir/nsparam.dat b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/nsparam.dat similarity index 100% rename from sim/therm_chip_top/simv.daidir/nsparam.dat rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/nsparam.dat diff --git a/sim/therm_chip_top/simv.daidir/pcc.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/pcc.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/pcc.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/pcc.sdb diff --git a/sim/therm_chip_top/simv.daidir/pcxpxmr.dat b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/pcxpxmr.dat similarity index 100% rename from sim/therm_chip_top/simv.daidir/pcxpxmr.dat rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/pcxpxmr.dat diff --git a/sim/therm_chip_top/simv.daidir/prof.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/prof.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/prof.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/prof.sdb diff --git a/sim/therm_chip_top/simv.daidir/rmapats.dat b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.dat similarity index 100% rename from sim/therm_chip_top/simv.daidir/rmapats.dat rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.dat diff --git a/sim/therm_chip_top/simv.daidir/rmapats.so b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.so similarity index 100% rename from sim/therm_chip_top/simv.daidir/rmapats.so rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.so diff --git a/sim/therm_chip_top/simv.daidir/saifNetInfo.db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/saifNetInfo.db similarity index 100% rename from sim/therm_chip_top/simv.daidir/saifNetInfo.db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/saifNetInfo.db diff --git a/sim/therm_chip_top/simv.daidir/stitch_nsparam.dat b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/stitch_nsparam.dat similarity index 100% rename from sim/therm_chip_top/simv.daidir/stitch_nsparam.dat rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/stitch_nsparam.dat diff --git a/sim/therm_chip_top/simv.daidir/tt.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/tt.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/tt.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/tt.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_131020.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131020.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_131020.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131020.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_131039.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131039.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_131039.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131039.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_131040.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131040.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_131040.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131040.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_14790.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14790.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_14790.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14790.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_14816.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14816.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_14816.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14816.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_14817.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14817.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_14817.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14817.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_26119.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26119.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_26119.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26119.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_26137.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26137.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_26137.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26137.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_26138.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26138.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_26138.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26138.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_30584.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30584.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_30584.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30584.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_30603.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30603.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_30603.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30603.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_30604.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30604.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_30604.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30604.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_34047.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_34047.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_34047.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_34047.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_34065.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_34065.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_34065.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_34065.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_34066.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_34066.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_34066.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_34066.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_37423.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_37423.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_37423.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_37423.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_37441.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_37441.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_37441.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_37441.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_37442.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_37442.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_37442.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_37442.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_39101.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_39101.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_39101.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_39101.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_39120.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_39120.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_39120.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_39120.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_39121.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_39121.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_39121.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_39121.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_40330.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_40330.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_40330.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_40330.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_40348.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_40348.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_40348.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_40348.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_40349.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_40349.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_40349.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_40349.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_41475.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_41475.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_41475.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_41475.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_41494.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_41494.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_41494.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_41494.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_41495.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_41495.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_41495.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_41495.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_42301.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_42301.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_42301.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_42301.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_42320.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_42320.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_42320.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_42320.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_42321.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_42321.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_42321.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_42321.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_43406.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_43406.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_43406.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_43406.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_43443.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_43443.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_43443.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_43443.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_43444.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_43444.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_43444.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_43444.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_45855.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_45855.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_45855.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_45855.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_45891.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_45891.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_45891.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_45891.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_45892.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_45892.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_45892.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_45892.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_50099.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_50099.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_50099.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_50099.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_50120.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_50120.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_50120.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_50120.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_50121.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_50121.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_50121.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_50121.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_52045.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_52045.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_52045.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_52045.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_52081.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_52081.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_52081.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_52081.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_52082.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_52082.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_52082.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_52082.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_53444.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_53444.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_53444.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_53444.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_53462.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_53462.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_53462.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_53462.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_53463.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_53463.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_53463.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_53463.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_54606.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_54606.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_54606.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_54606.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_54624.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_54624.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_54624.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_54624.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_54625.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_54625.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_54625.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_54625.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_56094.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_56094.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_56094.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_56094.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_56112.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_56112.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_56112.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_56112.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_56113.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_56113.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_56113.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_56113.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_57246.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57246.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_57246.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57246.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_57264.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57264.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_57264.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57264.sdb diff --git a/sim/therm_chip_top/simv.daidir/ttIncr_57265.sdb b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57265.sdb similarity index 100% rename from sim/therm_chip_top/simv.daidir/ttIncr_57265.sdb rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57265.sdb diff --git a/sim/therm_chip_top/simv.daidir/vcs_rebuild b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcs_rebuild similarity index 100% rename from sim/therm_chip_top/simv.daidir/vcs_rebuild rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcs_rebuild diff --git a/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db similarity index 100% rename from sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db diff --git a/sim/therm_chip_top/simv.daidir/vcselab_misc_hsdef.db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsdef.db similarity index 100% rename from sim/therm_chip_top/simv.daidir/vcselab_misc_hsdef.db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsdef.db diff --git a/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_elab.db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_elab.db similarity index 100% rename from sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_elab.db rename to spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_elab.db diff --git a/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_fegate.db b/spi_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_fegate.db similarity index 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sim/therm_chip_top/verdiLog/turbo.log rename to spi_thermometer_digital/sim/therm_chip_top/verdiLog/turbo.log diff --git a/sim/therm_chip_top/verdiLog/verdi.cmd b/spi_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd similarity index 100% rename from sim/therm_chip_top/verdiLog/verdi.cmd rename to spi_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd diff --git a/sim/therm_chip_top/verdiLog/verdi.cmd.bak b/spi_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd.bak similarity index 100% rename from sim/therm_chip_top/verdiLog/verdi.cmd.bak rename to spi_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd.bak diff --git a/sim/therm_chip_top/verdiLog/verdi_perf_err.log b/spi_thermometer_digital/sim/therm_chip_top/verdiLog/verdi_perf_err.log similarity index 100% rename from sim/therm_chip_top/verdiLog/verdi_perf_err.log rename to spi_thermometer_digital/sim/therm_chip_top/verdiLog/verdi_perf_err.log diff --git a/sim/therm_chip_top/wave.fsdb b/spi_thermometer_digital/sim/therm_chip_top/wave.fsdb similarity index 100% rename from sim/therm_chip_top/wave.fsdb rename to spi_thermometer_digital/sim/therm_chip_top/wave.fsdb diff --git a/spi_thermometer_digital/tb/tb_diginal_top.sv b/spi_thermometer_digital/tb/tb_diginal_top.sv new file mode 100644 index 0000000..9d7c69b --- /dev/null +++ b/spi_thermometer_digital/tb/tb_diginal_top.sv @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps + +module tb_digital_top(); + + // 参数定义 + parameter CLK_PERIOD = 20; // 100MHz 系统时钟 + parameter SCLK_PERIOD = 200; // 10MHz SPI时钟 (必须比系统时钟慢) + + // 信号声明 + logic clk; + logic rst_n; + logic [4:0] cfgid; + + logic sclk; + logic csn; + logic mosi; + logic miso; + logic oen; + logic sig_in; + + // 实例化 DUT + digital_top u_digital_top ( + .clk (clk ), + .rst_n (rst_n ), + .cfgid (cfgid ), + .sclk (sclk ), + .csn (csn ), + .mosi (mosi ), + .miso (miso ), + .oen (oen ), + .sig_in ( sig_in ) + ); + + // 系统时钟产生 + initial begin + clk = 0; + forever #(CLK_PERIOD/2) clk = ~clk; + end + + // 初始复位与赋值 + initial begin + rst_n = 0; + sclk = 0; + csn = 1; + mosi = 0; + cfgid = 5'h00; // 设定芯片ID为 10 + #(CLK_PERIOD * 10); + rst_n = 1; + #(CLK_PERIOD * 10); + fork + begin // --- 开始测试 --- + #2ms; + spi_read(25'h08, 5'h00); + #(CLK_PERIOD * 10); + spi_read(25'h0c, 5'h00); + #(CLK_PERIOD * 10); + spi_write(25'h08, 5'h00, 32'h2); + end + + begin + gen_pulses(1000,5); + end + join + + + // spi_read(25'h04, 5'h00); + //aa + // spi_read(25'h00, 5'h0A); + // #(SCLK_PERIOD * 5); + // spi_read(25'h00, 5'h0A); + // // 1. 测试写操作: 写入 0x12345678 到 地址 0x100 + // spi_write(25'h00, 5'h0A, 32'h12345678); + + // #(SCLK_PERIOD * 5); + + // // 2. 测试读操作: 从地址 0x100 读取 (验证读使能和地址) + // spi_read(25'h00, 5'h0A); + + #(SCLK_PERIOD * 20); + $display("Test Bench Finished."); + $finish; + end + + // --------------------------------------------------------- + // Task: SPI 发送/接收 32位数据 + // --------------------------------------------------------- + task spi_xfer_32(input [31:0] data_in, output [31:0] data_out); + for (int i = 31; i >= 0; i--) begin + mosi = data_in[i]; // MSB First ,psclk前给数据 psclk让人采样. 自己什么时候采？要看别人什么时候给数据 + #(SCLK_PERIOD/2); + sclk = 1; // 上升沿，DUT采样 + data_out[i] = miso; + // 采样从机发回的数据 + #(SCLK_PERIOD/2); + sclk = 0; + end + endtask + + // --------------------------------------------------------- + // Task: 写操作 (wnr=0) + // --------------------------------------------------------- + task spi_write(input [24:0] target_addr, input [4:0] id, input [31:0] data); + logic [31:0] header; + logic [31:0] dummy; + + header = {1'b0, target_addr, id, 1'b0}; // 构造命令帧 + + $display("[WRITE] Addr: %h, Data: %h", target_addr, data); + + csn = 0; + spi_xfer_32(header, dummy); // 发送命令 + spi_xfer_32(data, dummy); // 发送数据 + csn = 1; + mosi = 0; + endtask + + // --------------------------------------------------------- + // Task: 读操作 (wnr=1) + // --------------------------------------------------------- + task spi_read(input [24:0] target_addr, input [4:0] id); + logic [31:0] header; + logic [31:0] read_val; + + header = {1'b1, target_addr, id, 1'b0}; // 构造命令帧 (wnr=1) + + $display("[READ] Addr: %h", target_addr); + + csn = 0; + spi_xfer_32(header, read_val); // 发送命令帧，此时读回的可能是无用数据 + spi_xfer_32(32'h0, read_val); // 发送Dummy，接收真正的读数据 + csn = 1; + mosi = 0; + + $display("[READ] Result: %h", read_val); + endtask + + + task automatic gen_pulses(input int freq_khz, input int duration_ms); + int half_period_ns; + longint end_time_ns; + begin + if (freq_khz <= 0) begin + sig_in = 0; + #(duration_ms * 1000000); + end else begin + half_period_ns = 500000 / freq_khz; + end_time_ns = $time + (longint'(duration_ms) * 1000000); + + $display("[%0t] Start generating signal: %0d kHz", $time, freq_khz); + while ($time < end_time_ns) begin + sig_in = 1; + #(half_period_ns); + sig_in = 0; + #(half_period_ns); + end + end + end + endtask +endmodule \ No newline at end of file diff --git a/spi_thermometer_digital/tb/tb_diginal_top.v b/spi_thermometer_digital/tb/tb_diginal_top.v new file mode 100644 index 0000000..b9b60ef --- /dev/null +++ b/spi_thermometer_digital/tb/tb_diginal_top.v @@ -0,0 +1,119 @@ +`timescale 1ns / 1ps + +module tb_digital_top(); + + // 参数定义 + parameter CLK_PERIOD = 10; // 100MHz 系统时钟 + parameter SCLK_PERIOD = 100; // 10MHz SPI时钟 (必须比系统时钟慢) + + // 信号声明 + logic clk; + logic rst_n; + logic [4:0] cfgid; + + logic sclk; + logic csn; + logic mosi; + logic miso; + logic oen; + + + // 实例化 DUT + digital_top u_digital_top ( + .clk (clk ), + .rst_n (rst_n ), + .cfgid (cfgid ), + .sclk (sclk ), + .csn (csn ), + .mosi (mosi ), + .miso (miso ), + .oen (oen ), + .sig_in ( ) + ); + + // 系统时钟产生 + initial begin + clk = 0; + forever #(CLK_PERIOD/2) clk = ~clk; + end + + // 初始复位与赋值 + initial begin + rst_n = 0; + sclk = 0; + csn = 1; + mosi = 0; + cfgid = 5'h0A; // 设定芯片ID为 10 + + #(CLK_PERIOD * 10); + rst_n = 1; + #(CLK_PERIOD * 10); + + // --- 开始测试 --- + + // 1. 测试写操作: 写入 0x12345678 到 地址 0x100 + spi_write(25'h100, 5'h0A, 32'h12345678); + + #(SCLK_PERIOD * 5); + + // 2. 测试读操作: 从地址 0x100 读取 (验证读使能和地址) + spi_read(25'h222, 5'h0A); + + #(SCLK_PERIOD * 20); + $display("Test Bench Finished."); + $finish; + end + + // --------------------------------------------------------- + // Task: SPI 发送/接收 32位数据 + // --------------------------------------------------------- + task spi_xfer_32(input [31:0] data_in, output [31:0] data_out); + for (int i = 31; i >= 0; i--) begin + mosi = data_in[i]; // MSB First + #(SCLK_PERIOD/2); + sclk = 1; // 上升沿，DUT采样 + #(SCLK_PERIOD/2); + data_out[i] = miso; // 采样从机发回的数据 + sclk = 0; + end + endtask + + // --------------------------------------------------------- + // Task: 写操作 (wnr=0) + // --------------------------------------------------------- + task spi_write(input [24:0] target_addr, input [4:0] id, input [31:0] data); + logic [31:0] header; + logic [31:0] dummy; + + header = {1'b0, target_addr, id, 1'b0}; // 构造命令帧 + + $display("[WRITE] Addr: %h, Data: %h", target_addr, data); + + csn = 0; + spi_xfer_32(header, dummy); // 发送命令 + spi_xfer_32(data, dummy); // 发送数据 + csn = 1; + mosi = 0; + endtask + + // --------------------------------------------------------- + // Task: 读操作 (wnr=1) + // --------------------------------------------------------- + task spi_read(input [24:0] target_addr, input [4:0] id); + logic [31:0] header; + logic [31:0] read_val; + + header = {1'b1, target_addr, id, 1'b0}; // 构造命令帧 (wnr=1) + + $display("[READ] Addr: %h", target_addr); + + csn = 0; + spi_xfer_32(header, read_val); // 发送命令帧，此时读回的可能是无用数据 + spi_xfer_32(32'h0, read_val); // 发送Dummy，接收真正的读数据 + csn = 1; + mosi = 0; + + $display("[READ] Result: %h", read_val); + endtask + +endmodule \ No newline at end of file diff --git a/doc/设计报告/温度计数字模块设计报告.assets/局部截取_20260311_125312.png b/uart_thermometer_digital/doc/设计报告/温度计数字模块设计报告.assets/局部截取_20260311_125312.png similarity index 100% rename from doc/设计报告/温度计数字模块设计报告.assets/局部截取_20260311_125312.png rename to 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b/uart_thermometer_digital/doc/设计报告/温度计数字模块设计报告.md @@ -16,7 +16,7 @@ # 设计细节确定 -**通信方式**：串口通信，为115200波特率， 不可更改。采用如下指定数据帧结构配置寄存器，帧传输为大端序。 + | 数据结构 | 子字段 | 位宽 | 比特序 | 功能描述 | 备注 | | -------- | -------- | --------- | ------- | -------------------------------- | ------------------------------------------------------------ | @@ -28,8 +28,12 @@ | ^ | LENGTH | 20 bits | [19:0] | 指示读写数据长度，以 Byte 为单位 | 最大支持 1MByte | | **DATA** | - | N*4 bytes | [31:0] | 数据 | 读操作时，无需包含该项 | +**通信方式**：串口通信，为115200波特率， 不可更改。采用如上指定数据帧结构配置寄存器（大端序）。 + **温度精度**：温度分辨率为小数点后2位，-4032表示-40.32度 +**温度测量范围**：-40°C~85°C ，超过则显示最大值。 + **系统时钟周期**：50MHz。 **标定方式**：线性标定。**范围**：默认为-40°C对应160kHz, 85°C对应600kHz. @@ -38,7 +42,11 @@ **采样窗口时长**：默认1ms, 支持配置 -**主动回传模式**：默认关闭。可通过配置0x10上报寄存器开启，数据回传间隔可配置。 +**读回方式**：两种，可选择主动回传，也可以通过串口发指令直接读寄存器得结果。 + +**主动回传模式**：默认关闭。可通过配置0x10上报寄存器开启。 + +**主动回传间隔**：默认50ms，可配置。 @@ -62,11 +70,7 @@ freq_valid拉高，下一个周期就把freq_valid也拉高同时freq_x100hz更 - - - - - +逻辑延时93-98 总延时148 **设计通信模块** @@ -106,6 +110,10 @@ parse状态 ， 基于上面拿到的cmd ,解析，可以知道是读还是写 +![局部截取_20260408_101045](./温度计数字模块设计报告.assets/局部截取_20260408_101045.png + + + # 寄存器设置 根据刚才补全的 `system_regfile` 模块逻辑，为您整理的寄存器说明表格如下。这些寄存器地址采用 **32位（4字节）对齐** 方式。 @@ -119,7 +127,7 @@ parse状态 ， 基于上面拿到的cmd ,解析，可以知道是读还是写 | `16'h08` | **WIN_MODE_R** | R/W | `32'h000003E8` | 测量窗口时间与输出模式配置 | | `16'h0C` | **CALIB_R** | R/W | `32'h025800A0` | 温度计频率标定参数 | | `16'h10` | **REPORT_R** | R/W | `32'h0000c350` | 自动上报使能与间隔配置 | -| `16'h14` | **STATUS** | **RO** | `32'h00000000` | 当前温度计状态与测量结果 | +| `16'h14` | **RESULT** | **RO** | `32'h00000000` | 当前温度计状态与测量结果 | ------ @@ -165,7 +173,17 @@ parse状态 ， 基于上面拿到的cmd ,解析，可以知道是读还是写 +读data寄存器 +80000004 00000004 + +00000004 00000004 20260407 + +开启主动上报使能 + +00000010 00000004 800fc350 + +00000010 00000004 0000c350 关闭 # 总结 diff --git a/rtl/digital_top.v b/uart_thermometer_digital/rtl/digital_top.v similarity index 100% rename from rtl/digital_top.v rename to uart_thermometer_digital/rtl/digital_top.v diff --git a/uart_thermometer_digital/rtl/divider.v b/uart_thermometer_digital/rtl/divider.v new file mode 100644 index 0000000..21dfc53 --- /dev/null +++ b/uart_thermometer_digital/rtl/divider.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2026/04/08 10:49:33 +// Design Name: +// Module Name: divider +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module divider( + + ); +endmodule diff --git a/rtl/systemregfile/my_systemregfile.v b/uart_thermometer_digital/rtl/systemregfile/my_systemregfile.v similarity index 97% rename from rtl/systemregfile/my_systemregfile.v rename to uart_thermometer_digital/rtl/systemregfile/my_systemregfile.v index 86eb5f1..9730993 100644 --- a/rtl/systemregfile/my_systemregfile.v +++ b/uart_thermometer_digital/rtl/systemregfile/my_systemregfile.v @@ -1,134 +1,134 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Add a new register: - -// SECTION A: Add localparam ADDR_NEW = 16'hXX;. - -// SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;. - -// SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);. - -// SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);. - -// SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block. - -// SECTION G: Map reg_new to the module's output ports. -//-FHDR-------------------------------------------------------------------------------------------------------- - -module system_regfile ( - // [BLOCK 0] System and Bus Interface - input clk, - input rst_n, - input [31:0] wrdata, - input wren, - input [24:0] rwaddr, - input rden, - output [31:0] rddata, - - output [23:0]win_us, - output [1:0]out_mode, //0: output temperature, 1: output frequency, 2: output pulse count per window - output [15:0]temp_85_fre_k, //Frequency at 85¡ãC, default 600khz - output [15:0]temp_neg_40_fre_k , //Frequency at -40¡ãC, default 160khz, unit khz - output report_en, - output [23:0]rep_gap_us, //Minimum interval (us), no reporting if smaller than win_us - input [23:0]therm_out, - input therm_vld - -); - -// ============================================================================= -// [SECTION A] Address Offset Definition (Localparams) -// ============================================================================= - localparam TESTR = 16'h00, DATER = 16'h04; - localparam WIN_MODE_R = 16'h08; // Configure window time and output mode - localparam CALIB_R = 16'h0C; // Calibration parameter register - localparam REPORT_R = 16'h10; // Report enable and interval - localparam RESULT_R = 16'h14; // Status and result register (Read-only) - - - -// ============================================================================= -// [SECTION B] Internal Wire Declaration (Wires) -// ============================================================================= - -// Register selection signals (Enable Wires) - wire sel_testr, sel_dater; - wire sel_win_mode, sel_calib, sel_report, sel_result; - -// Write enable signals (Write Enable Wires) - wire we_testr, we_dater; - wire we_win_mode, we_calib, we_report; - - -// Register storage wires (Storage Wires) - wire [31:0] testr, dater; - wire [31:0] win_mode_r, calib_r, report_r, result_r; -// ============================================================================= -// [SECTION C] Decoding Logic (Decoding) -// ============================================================================= - assign sel_testr = (rwaddr[15:0] == TESTR ); - assign sel_dater = (rwaddr[15:0] == DATER ); - assign sel_win_mode = (rwaddr[15:0] == WIN_MODE_R ); - assign sel_calib = (rwaddr[15:0] == CALIB_R ); - assign sel_report = (rwaddr[15:0] == REPORT_R ); - assign sel_result = (rwaddr[15:0] == RESULT_R ); - -// Write enable allocation -assign we_testr = sel_testr & wren; -assign we_dater = sel_dater & wren; -assign we_win_mode = sel_win_mode & wren; -assign we_calib = sel_calib & wren; -assign we_report = sel_report & wren; - - -// ============================================================================= -// [SECTION D] Register Instantiation (Storage Implementation) -// ============================================================================= - -// --- General and Test Registers --- -sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n); -sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n); - -// --- Thermometer Functional Registers --- -// win_mode_r: [25:24] out_mode, [23:0] win_us (Default window 1000us) -sirv_gnrl_dfflrd #(32) win_mode_dff (32'h0000_03E8, we_win_mode, wrdata, win_mode_r, clk, rst_n); -// calib_r: [31:16] Frequency at 85¡ãC (default 600k), [15:0] Frequency at -40¡ãC (default 160k) -sirv_gnrl_dfflrd #(32) calib_dff (32'h0258_00A0, we_calib, wrdata, calib_r, clk, rst_n); -// report_r: [31] report_en, [23:0] rep_gap_us (Default interval 50ms) -sirv_gnrl_dfflrd #(32) report_dff (32'h0000_C350, we_report, wrdata, report_r, clk, rst_n); - -sirv_gnrl_dffr #(32) result_dff ({8'b0,therm_out},result_r, clk, rst_n); - -// ============================================================================= -// [SECTION E] Special Business Logic (Business Logic) -// ============================================================================= - -// LVDS Real-time status register -// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n); - -// ============================================================================= -// [SECTION F] Readback Logic (Readback Mux) -// ============================================================================= -reg [31:0] rddata_reg; -always @(*) begin - rddata_reg = 32'b0; - if (sel_testr) rddata_reg = testr; - else if (sel_dater) rddata_reg = dater; - else if (sel_win_mode) rddata_reg = win_mode_r; - else if (sel_calib) rddata_reg = calib_r; - else if (sel_report) rddata_reg = report_r; - else if (sel_result) rddata_reg = result_r; -end - - sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n); - -// ============================================================================= -// [SECTION G] Output Mapping (Output Assignments) -// ============================================================================= -assign win_us = win_mode_r[23:0]; -assign out_mode = win_mode_r[25:24]; -assign temp_85_fre_k = calib_r[31:16]; -assign temp_neg_40_fre_k = calib_r[15:0]; -assign report_en = report_r[31]; -assign rep_gap_us = report_r[23:0]; - +//+FHDR-------------------------------------------------------------------------------------------------------- +// Add a new register: + +// SECTION A: Add localparam ADDR_NEW = 16'hXX;. + +// SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;. + +// SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);. + +// SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);. + +// SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block. + +// SECTION G: Map reg_new to the module's output ports. +//-FHDR-------------------------------------------------------------------------------------------------------- + +module system_regfile ( + // [BLOCK 0] System and Bus Interface + input clk, + input rst_n, + input [31:0] wrdata, + input wren, + input [24:0] rwaddr, + input rden, + output [31:0] rddata, + + output [23:0]win_us, + output [1:0]out_mode, //0: output temperature, 1: output frequency, 2: output pulse count per window + output [15:0]temp_85_fre_k, //Frequency at 85¡ãC, default 600khz + output [15:0]temp_neg_40_fre_k , //Frequency at -40¡ãC, default 160khz, unit khz + output report_en, + output [23:0]rep_gap_us, //Minimum interval (us), no reporting if smaller than win_us + input [23:0]therm_out, + input therm_vld + +); + +// ============================================================================= +// [SECTION A] Address Offset Definition (Localparams) +// ============================================================================= + localparam TESTR = 16'h00, DATER = 16'h04; + localparam WIN_MODE_R = 16'h08; // Configure window time and output mode + localparam CALIB_R = 16'h0C; // Calibration parameter register + localparam REPORT_R = 16'h10; // Report enable and interval + localparam RESULT_R = 16'h14; // Status and result register (Read-only) + + + +// ============================================================================= +// [SECTION B] Internal Wire Declaration (Wires) +// ============================================================================= + +// Register selection signals (Enable Wires) + wire sel_testr, sel_dater; + wire sel_win_mode, sel_calib, sel_report, sel_result; + +// Write enable signals (Write Enable Wires) + wire we_testr, we_dater; + wire we_win_mode, we_calib, we_report; + + +// Register storage wires (Storage Wires) + wire [31:0] testr, dater; + wire [31:0] win_mode_r, calib_r, report_r, result_r; +// ============================================================================= +// [SECTION C] Decoding Logic (Decoding) +// ============================================================================= + assign sel_testr = (rwaddr[15:0] == TESTR ); + assign sel_dater = (rwaddr[15:0] == DATER ); + assign sel_win_mode = (rwaddr[15:0] == WIN_MODE_R ); + assign sel_calib = (rwaddr[15:0] == CALIB_R ); + assign sel_report = (rwaddr[15:0] == REPORT_R ); + assign sel_result = (rwaddr[15:0] == RESULT_R ); + +// Write enable allocation +assign we_testr = sel_testr & wren; +assign we_dater = sel_dater & wren; +assign we_win_mode = sel_win_mode & wren; +assign we_calib = sel_calib & wren; +assign we_report = sel_report & wren; + + +// ============================================================================= +// [SECTION D] Register Instantiation (Storage Implementation) +// ============================================================================= + +// --- General and Test Registers --- +sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n); +sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n); + +// --- Thermometer Functional Registers --- +// win_mode_r: [25:24] out_mode, [23:0] win_us (Default window 1000us) +sirv_gnrl_dfflrd #(32) win_mode_dff (32'h0000_03E8, we_win_mode, wrdata, win_mode_r, clk, rst_n); +// calib_r: [31:16] Frequency at 85¡ãC (default 600k), [15:0] Frequency at -40¡ãC (default 160k) +sirv_gnrl_dfflrd #(32) calib_dff (32'h0258_00A0, we_calib, wrdata, calib_r, clk, rst_n); +// report_r: [31] report_en, [23:0] rep_gap_us (Default interval 50ms) +sirv_gnrl_dfflrd #(32) report_dff (32'h0000_C350, we_report, wrdata, report_r, clk, rst_n); + +sirv_gnrl_dffr #(32) result_dff ({8'b0,therm_out},result_r, clk, rst_n); + +// ============================================================================= +// [SECTION E] Special Business Logic (Business Logic) +// ============================================================================= + +// LVDS Real-time status register +// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n); + +// ============================================================================= +// [SECTION F] Readback Logic (Readback Mux) +// ============================================================================= +reg [31:0] rddata_reg; +always @(*) begin + rddata_reg = 32'b0; + if (sel_testr) rddata_reg = testr; + else if (sel_dater) rddata_reg = dater; + else if (sel_win_mode) rddata_reg = win_mode_r; + else if (sel_calib) rddata_reg = calib_r; + else if (sel_report) rddata_reg = report_r; + else if (sel_result) rddata_reg = result_r; +end + + sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n); + +// ============================================================================= +// [SECTION G] Output Mapping (Output Assignments) +// ============================================================================= +assign win_us = win_mode_r[23:0]; +assign out_mode = win_mode_r[25:24]; +assign temp_85_fre_k = calib_r[31:16]; +assign temp_neg_40_fre_k = calib_r[15:0]; +assign report_en = report_r[31]; +assign rep_gap_us = report_r[23:0]; + endmodule \ No newline at end of file diff --git a/uart_thermometer_digital/rtl/systemregfile/sirv_gnrl_dffs.v b/uart_thermometer_digital/rtl/systemregfile/sirv_gnrl_dffs.v new file mode 100644 index 0000000..6526cd4 --- /dev/null +++ b/uart_thermometer_digital/rtl/systemregfile/sirv_gnrl_dffs.v @@ -0,0 +1,342 @@ + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// All of the general DFF and Latch modules +// +// ==================================================================== + +// + + +// +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 1 +// +// =========================================================================== +`define DISABLE_SV_ASSERTION +`define dly #0.2 +module sirv_gnrl_dfflrs # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dfflr # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is input +// +// =========================================================================== + +module sirv_gnrl_dfflrd # ( + parameter DW = 32 +) ( + input [DW-1:0] init, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= init; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable, no reset +// +// =========================================================================== + +module sirv_gnrl_dffl # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk +); + +reg [DW-1:0] qout_r; + +always @(posedge clk) +begin : DFFL_PROC + if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 1 +// +// =========================================================================== + +module sirv_gnrl_dffrs # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dffr # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module for general latch +// +// =========================================================================== + +module sirv_gnrl_ltch # ( + parameter DW = 32 +) ( + + //input test_mode, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout +); + +reg [DW-1:0] qout_r; + +always @ * +begin : LTCH_PROC + if (lden == 1'b1) + qout_r <= dnxt; +end + +//assign qout = test_mode ? dnxt : qout_r; +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +always_comb +begin + CHECK_THE_X_VALUE: + assert (lden !== 1'bx) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); +end + +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// module sirv_gnrl_edffr #(parameter type T = logic) ( +// input T dnxt, +// output T qout, +// input clk, rst_n +// ); + +// T qout_r; + +// always_ff @(posedge clk or negedge rst_n) begin +// if (!rst_n) qout_r <= T'('0); +// else qout_r <= `dly dnxt; +// end +// assign qout = qout_r; +// endmodule + diff --git a/rtl/therm/digital_thermometer.v b/uart_thermometer_digital/rtl/therm/digital_thermometer.v similarity index 84% rename from rtl/therm/digital_thermometer.v rename to uart_thermometer_digital/rtl/therm/digital_thermometer.v index 5cec864..e2b38ee 100644 --- a/rtl/therm/digital_thermometer.v +++ b/uart_thermometer_digital/rtl/therm/digital_thermometer.v @@ -24,26 +24,27 @@ module digital_thermometer( wire [23:0] wd_cnt_out; wire wd_cnt_vld; reg [23:0] gap_cnt; // Report interval counter - wire [23:0] cur_freq_khz; - reg signed [23:0] temp_scaled; + reg [23:0] cur_freq_khz; + reg signed [23:0] temp_scaled; - assign cur_freq_khz = (wd_cnt_out * 1000) / win_us; - //Scale temperature result by 100 times - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin +always @(posedge clk or negedge rst_n)begin + if(!rst_n)begin + cur_freq_khz <= 0; temp_scaled <= 0; - end else if (wd_cnt_vld) begin - //If current frequency <= calibrated frequency at -40¡ãC, output -4000 directly + end + else begin + cur_freq_khz <= (wd_cnt_out * 1000) / win_us; + if (cur_freq_khz <= temp_neg_40_fre_k) begin temp_scaled <= -32'sd4000; end else begin - //Calculate interpolation only when frequency > lower limit to avoid subtraction overflow temp_scaled <= ((cur_freq_khz - temp_neg_40_fre_k) * 12500) / (temp_85_fre_k - temp_neg_40_fre_k) - 4000; end end end + // Report logic and output selection always @(posedge clk or negedge rst_n) begin if (!rst_n) begin diff --git a/uart_thermometer_digital/rtl/therm/pulse_cnt.v b/uart_thermometer_digital/rtl/therm/pulse_cnt.v new file mode 100644 index 0000000..06ee09b --- /dev/null +++ b/uart_thermometer_digital/rtl/therm/pulse_cnt.v @@ -0,0 +1,59 @@ +`timescale 1ns / 1ps + +module pulse_cnt #( + parameter CLK_FREQ = 50_000_000 +) ( + input wire clk, + input wire rst_n, + input wire sig_in, + input wire [23:0] win_us, + output reg [23:0] cnt_out, + output reg vld_out +); + + + reg [31:0] window_cnt; // Current clock cycle count + reg [31:0] target_cnt; // Required clock cycles for current measurement window + + // Pulse counter (width matches output to prevent overflow) + reg [23:0] pulse_cnt; + + + + reg sig_sync1, sig_sync2, sig_sync3; + wire sig_rise = sig_sync2 & ~sig_sync3; + + always @(posedge clk) begin + sig_sync1 <= sig_in; + sig_sync2 <= sig_sync1; + sig_sync3 <= sig_sync2; + end + + // Main control logic + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + window_cnt <= 0; + pulse_cnt <= 0; + cnt_out <= 0; + vld_out <= 0; + target_cnt <= 24'd50_000; + + end else begin + vld_out <= 1'b0; + target_cnt <= ( {40'd0, win_us} * CLK_FREQ) / 1_000_000 ; + // Window count end condition: current count reaches target_cnt + if (window_cnt >= target_cnt) begin + cnt_out <= pulse_cnt; + vld_out <= 1'b1; + // Reset window counter and pulse counter, trigger target value recalculation + window_cnt <= 0; + pulse_cnt <= 0; + end else begin + window_cnt <= window_cnt + 1; + if (sig_rise) + pulse_cnt <= pulse_cnt + 1; + end + end + end + +endmodule \ No newline at end of file diff --git a/rtl/uart/uart_byte_rx.v b/uart_thermometer_digital/rtl/uart/uart_byte_rx.v similarity index 100% rename from rtl/uart/uart_byte_rx.v rename to uart_thermometer_digital/rtl/uart/uart_byte_rx.v diff --git a/rtl/uart/uart_byte_tx.v b/uart_thermometer_digital/rtl/uart/uart_byte_tx.v similarity index 100% rename from rtl/uart/uart_byte_tx.v rename to uart_thermometer_digital/rtl/uart/uart_byte_tx.v diff --git a/rtl/uart/uart_ctrl_sysreg.v b/uart_thermometer_digital/rtl/uart/uart_ctrl_sysreg.v similarity index 100% rename from rtl/uart/uart_ctrl_sysreg.v rename to uart_thermometer_digital/rtl/uart/uart_ctrl_sysreg.v diff --git a/rtl/uart/uart_top_32bit.v b/uart_thermometer_digital/rtl/uart/uart_top_32bit.v similarity index 100% rename from rtl/uart/uart_top_32bit.v rename to uart_thermometer_digital/rtl/uart/uart_top_32bit.v diff --git a/uart_thermometer_digital/sim/therm_chip_top/Makefile b/uart_thermometer_digital/sim/therm_chip_top/Makefile new file mode 100644 index 0000000..d594bea --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/Makefile @@ -0,0 +1,74 @@ + +WAVE ?= 0 + +SIM = RTL + +folder = simv + +ifeq ($(WAVE),1) + WAVE_OPTS = -debug_access+all -debug_region+cell+encrypt -P $(NOVAS_HOME)/share/PLI/VCS/linux64/novas_new_dumper.tab $(NOVAS_HOME)/share/PLI/VCS/linux64/pli.a +define+DUMP_FSDB + WAVE_SIM_OPTS = -fsdbDumpfile=sim.fsdb + else + WAVE_OPTS = -debug_access+pp +endif + +ifeq ($(SIM),PostPr) +VCS = vcs -full64 -sverilog -Mupdate +lint=TFIPC-L +v2k +warn=noSDFCOM_IWSBA,noNTCDNC -notice +mindelays +tchk+edge+warn +neg_tchk -negdelay +overlap +sdfverbose -sdfretain +optconfigfile+notimingcheck.cfg -override_timescale=1ns/1ps -debug_access+all $(WAVE_OPTS) -lca -q -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb |tee +else +VCS = vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k $(WAVE_OPTS) -lca -q -timescale=1ns/1ps +nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb +endif + +ifeq ($(SIM),PostPr) + post_dir = ./data_PostPr +else + post_dir = ./data_PostSyn +endif + + +ifeq ($(SIM),PostSyn) +FileList = filelist_syn.f +else + ifeq ($(SIM),PostPr) + FileList = filelist_pr.f + else + FileList = filelist_vlg.f + endif +endif + +SIMV = ./simv sync:busywait $(WAVE_SIM_OPTS) -l |tee sim.log + +all:comp run dbg +rsim: comp run + +comp: +# ${VCS} -f $(FileList) +incdir+./../../rtl/define +incdir+./../../rtl/qubitmcu +incdir+./../../model + ${VCS} -f $(FileList) + +run: + ${SIMV} + +dbg: + verdi -sverilog -f $(FileList) -top TB -ssf *.fsdb -nologo & + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *fsdb* *.dat *.daidir *.vdb *~ + +compare: + ./compare_files.csh ${post_dir} ./data_RTL ./compare.txt + +regress: + ./regress.csh $(SIM) + +rmwork: + rm -rf ./work* + +rmdata: + rm -rf ./data* +cov: + verdi -cov -covdir coverage/merged.vdb & +cov_d: + dve -full64 -covdir coverage/*.vdb & +merge: + urg -full64 -dbname coverage/merged.vdb -flex_merge union -dir coverage/simv.vdb -parallel -maxjobs 64& +merge_i: + urg -full64 -flex_merge union -dir coverage/merged.vdb -dir coverage/$(folder) -dbname coverage/merged.vdb -parallel -maxjobs 64& diff --git a/uart_thermometer_digital/sim/therm_chip_top/TB.sv b/uart_thermometer_digital/sim/therm_chip_top/TB.sv new file mode 100644 index 0000000..6dc8678 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/TB.sv @@ -0,0 +1,230 @@ +`timescale 1ns / 1ps + +module TB(); + + // ========================================== + // Parameters & Signal Definitions + // ========================================== + parameter CLK_PERIOD = 20; // 50MHz + parameter BAUD = 115200; + localparam BIT_TIME = 1_000_000_000 / BAUD; + + reg clk; + reg rst_n; + reg uart_rx; // DUT RX + wire uart_tx; // DUT TX + reg sig_in; + + // Clock Generation + initial clk = 0; + always #(CLK_PERIOD/2) clk = ~clk; + // initial begin + // $fsdbDumpfile("wave.fsdb"); + // $fsdbDumpvars(); + // end + // ========================================== + // DUT Instantiation + // ========================================== + digital_top u_digital_top( + .clk (clk), + .rst_n (rst_n), + .uart_rx (uart_rx), + .uart_tx (uart_tx), + .sig_in (sig_in) + ); + + + // // ========================================== + // // TX Driver: Read from case.txt + // // ========================================== + // initial begin + // int file_h; + // int status; + // logic [63:0] val; + + // // Initialize signals + // rst_n = 0; + // uart_rx = 1; + // #(CLK_PERIOD * 10); + // rst_n = 1; + // file_h = $fopen("case.txt", "r"); + // if (!file_h) begin + // $display("[TX ERROR] Cannot open case.txt"); + // $finish; + // end + + // $display("[TX] Starting transmission..."); + + // while (!$feof(file_h)) begin + // // Read hex data per line + // status = $fscanf(file_h, "%h\n", val); + // if (status == 1) begin + // if (val > 64'hFFFF_FFFF) begin + // $display("[%t] TX CMD: %h", $time, val); + // send_data(val, 64); + // end else begin + // $display("[%t] TX DATA: %h", $time, val[31:0]); + // send_data(val[31:0], 32); + // end + // #(BIT_TIME * 5); // Frame gap + // } + // end + + // $fclose(file_h); + // $display("[TX] All cases sent."); + + // // Wait for RX return data + // #(BIT_TIME * 500); + // $display("[SIM] Simulation finished."); + // $finish; + // end + + + + // ========================================== + // RX Monitor: Save to rx_data.txt + // ========================================== + int rx_file_h; + initial begin + + logic [7:0] rx_byte; + + rx_file_h = $fopen("rx_data.txt", "w"); + if (!rx_file_h) begin + $display("[RX ERROR] Cannot create rx_data.txt"); + $finish; + end + + forever begin + logic [31:0] packet_word; // 32-bit data packet + logic [7:0] rx_byte; + // Collect 4 bytes to form 32-bit data + for (int byte_idx = 0; byte_idx < 4; byte_idx++) begin + // 1. Wait for start bit (falling edge) + @(negedge uart_tx); + // 2. Skip start bit, sample at center point + #(BIT_TIME / 2); + #(BIT_TIME); + // Read 8 data bits + for (int i = 0; i < 8; i++) begin + rx_byte[i] = uart_tx; + #(BIT_TIME); + end + // Combine to 32-bit (little-endian) + packet_word[24 - 8*byte_idx +: 8] = rx_byte; + // $display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte); + // Wait for end of stop bit + if (byte_idx < 3) begin + #(BIT_TIME / 2); + end + end + + // Write to file (one 32-bit data per line) + $fdisplay(rx_file_h, "%08h", packet_word); + $display("[%0t] Packet (32-bit): 0x%08h", $time, packet_word); + // Wait for end of last stop bit + #(BIT_TIME / 2); + end + end + + final begin + if (rx_file_h) begin + $fclose(rx_file_h); + $display("[RX] File closed at %t",$time); + end + end + + // --- Pulse Generation Task --- + // freq_khz: Target frequency (kHz) + // duration_ms: Test duration (ms) + task automatic gen_pulses(input int freq_khz, input int duration_ms); + int half_period_ns; + longint end_time_ns; + begin + if (freq_khz <= 0) begin + sig_in = 0; + #(duration_ms * 1000000); + end else begin + half_period_ns = 500000 / freq_khz; + end_time_ns = $time + (longint'(duration_ms) * 1000000); + + $display("[%0t] Start generating signal: %0d kHz", $time, freq_khz); + while ($time < end_time_ns) begin + sig_in = 1; + #(half_period_ns); + sig_in = 0; + #(half_period_ns); + end + end + end + endtask + + // ========================================== + // Task: Send one byte (Serial TX) + // ========================================== + task automatic send_byte(input [7:0] data); + begin + uart_rx = 0; // Start bit + #(BIT_TIME); + for (int i = 0; i < 8; i++) begin + uart_rx = data[i]; // LSB First + #(BIT_TIME); + end + uart_rx = 1; // Stop bit + #(BIT_TIME); + end + endtask + + // Task: Send 32/64 bit data + task automatic send_data(input [63:0] data, input int len_bits); + int bytes = len_bits / 8; + for (int i = bytes - 1; i >= 0; i--) begin // Send from highest byte + send_byte(data[i*8 +: 8]); + end + endtask + + initial begin + // 1. Initialization + rst_n = 0; uart_rx = 1; sig_in = 0; + #(CLK_PERIOD * 20); + rst_n = 1; + #(CLK_PERIOD * 100); + $display("------- Step 1: read Thermometer Regs -------"); + send_data(64'h80000004_00000004,64); + send_data(64'h80000008_00000004,64); //mode[25:24] + win + send_data(64'h8000000c_00000004,64); //calibration H / L + send_data(64'h80000010_00000004,64); //rep[31] +rep_gap[23:0] + send_data(64'h80000014_00000004,64); //result [23:0] + + + $display("------- Step 2: Running Concurrent Tasks -------"); + fork + // Process A: Generate input pulses (simulate temperature change) + begin + gen_pulses(200, 10); // 100kHz for 10ms + gen_pulses(300, 20); + gen_pulses(400, 30); + end + + // Process B: Insert read command during reporting + begin + #(6ms); // Wait for first report packet + send_data(64'h80000014_00000004,64); $display("[%0t] == Sending Read Request ==", $time); + send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); $display("[%0t] == open report_en==",$time); + send_data(64'h0000008_00000004,64);send_data(32'h0100_03e8,32); $display("[%0t] == mode = 1 ==",$time); + #15ms; + send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);$display("[%0t] == cloese report_en==",$time); + + //send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); $display("[%0t] == open report_en==",$time); + //send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);$display("[%0t] == cloese report_en==",$time); + #30000; + send_data(64'h80000014_00000004,64); + end + join + + #(BIT_TIME * 500); + $display("Test Done."); + $finish; + end + +endmodule \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/compile.log b/uart_thermometer_digital/sim/therm_chip_top/compile.log new file mode 100644 index 0000000..685d9a4 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/compile.log @@ -0,0 +1,22 @@ +Command: vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k -debug_access+pp -lca -q -timescale=1ns/1ps \ ++nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb \ +-f filelist_vlg.f + +Warning-[LCA_FEATURES_ENABLED] Usage warning + LCA features enabled by '-lca' argument on the command line. For more + information regarding list of LCA features please refer to Chapter "LCA + features" in the VCS/VCS-MX Release Notes + +VCS Coverage Metrics Release O-2018.09-SP2_Full64 Copyright (c) 1991-2018 by Synopsys Inc. + +Note-[VCS_PARAL] Parallel code-gen enabled + VCS is running with parallel code generation(-j)... + +6 modules and 0 UDP read. +make[1]: Entering directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \ + +ld -shared -Bsymbolic -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o +rm -f _csrc0.so +../simv up to date +make[1]: Leaving directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \ + diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.cmoptions b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.cmoptions new file mode 100644 index 0000000..aa3c928 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.cmoptions @@ -0,0 +1,16 @@ +Instrument +cond 3 +line 3 +fsm 65539 +tgl 8 +assign 0 +obc 0 +path 0 +branch 3 +Count 0 +Glitch -1 +cm_tglmda 0 +cm_tglstructarr 0 +cm_tglcount 0 +cm_hier 0 +cm_assert_hier 0 \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.mode64 b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.mode64 new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.vdb_version b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.vdb_version new file mode 100644 index 0000000..7239f16 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/.vdb_version @@ -0,0 +1 @@ +O-2018.09-SP2 \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml new file mode 100644 index 0000000..a1ab81d Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt new file mode 100644 index 0000000..68f2e80 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt @@ -0,0 +1,7 @@ +TB.u_digital_top.u_uart_ctrl.S_IDLE0 +TB.u_digital_top.u_uart_ctrl.S_PARSE2 +TB.u_digital_top.u_uart_ctrl.S_RD_DATA4 +TB.u_digital_top.u_uart_ctrl.S_REPORT6 +TB.u_digital_top.u_uart_ctrl.S_RX_CMD_L1 +TB.u_digital_top.u_uart_ctrl.S_WAIT_RD3 +TB.u_digital_top.u_uart_ctrl.S_WR_DATA5 diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml new file mode 100644 index 0000000..045ec15 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml new file mode 100644 index 0000000..dfb0d61 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml new file mode 100644 index 0000000..68ed56b Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml new file mode 100644 index 0000000..871fb0a Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml new file mode 100644 index 0000000..dfb4bdc Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml new file mode 100644 index 0000000..871fb0a Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt new file mode 100644 index 0000000..c24aa49 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt @@ -0,0 +1,97 @@ +// Synopsys, Inc. +// User: shbyang +// Date: Tue Apr 7 11:12:31 2026 + +// ================================================================================================== +// This config file prototype is produced from the last run using the complete list of extracted fsms. +// Please note that by providing your own description of the module you are enforcing what will be +// extracted for that module. +// Copy this file to your source directory and edit it as described below, +// then pass the file to VCS using the -cm_fsmcfg command line option. +// FSMs will be extracted normally for any module not mentioned in this file +// ================================================================================================== +// 1. For every module that you want to specify yourself, use: +// MODULE==name +// ----------------------------------------------------- +// The following options are defining the behavior on the module level. +// ----------------------------------------------------- +// 1.1 You can control what fsms should be used within this module: +// FSMS=AUTO +// this means that you want VCS to automatically extract all +// detectable FSMs from this module. +// ----------------------------------------------------- +// FSMS=EXCLUDE +// this means that you want all fsms except the ones from the list that follows +// if the list is empty, all fsms will be extracted for this module +// ----------------------------------------------------- +// FSMS=RESTRICT +// this means that you want only the fsms from the list that follows +// if the list is empty, no fsms will be extracted for this module +// ----------------------------------------------------- +// If none of these options are specified, the program will assume FSMS=RESTRICT +// ----------------------------------------------------- +// 1.2 You can specify that the state with the minimal value should be used as a +// start state for all sequences in every fsm in the module. +// FSMS=START_STATE_DFLT +// For any particular fsm you can overwrite this behavior inside its description. +// ----------------------------------------------------- +// 2. Each fsm description in the list of fsms should be specified as follows: +// 2.1 provide the current state variable declaration: +// CURRENT= name of the current state variable +// ----------------------------------------------------- +// 2.2 if next state variable is different from the current state provide: +// NEXT= next state variable +// if you don't use NEXT=, the program will assume that CURRENT and NEXT are the same +// ----------------------------------------------------- +// 2.3 if you want to provide the restrictive the list of states, provide: +// STATES= s0,s1 etc. where s0 is either a name or a value of the state +// if you don't use STATES=, the program will assume that you want to use all states +// ----------------------------------------------------- +// 2.4 if you want to ignore some states, specify them in the following list: +// STATES_X= s0,s1, etc. +// ----------------------------------------------------- +// 2.5 if you want to mark, that some states should never be reached, specify them as a list: +// STATES_NEVER= s0,s1, etc. +// ----------------------------------------------------- +// 2.6 similar to the STATES, if you want to provide the restrictive the list of transitions, specify: +// TRANSITIONS= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.7 similar to the STATES_X, if you want to ignore some transitions, specify them in the following list: +// TRANSITIONS_X= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.8 similar to the STATES_NEVER,if you want to mark, that some transitions should never occur, +// specify them as a list: +// TRANSITIONS_NEVER= s0->s1,s1->s2, etc. +// ----------------------------------------------------- +// 2.9 if you want to specify the start state use: +// START_STATE= s0 +// ----------------------------------------------------- +// Please note: +// - that a state in every list can be specified either by name or by value. +// - in specifying the transitions you can use * in order to refer to 'any' state. +// ================================================================================================== +// Uncomment and modify the following 2 line to override default FSM sequence limits for all FSMs in the design. +//SEQ_NUMBER_MAX=10000 +//SEQ_LENGTH_MAX=32 + +MODULE=uart_ctrl_sysreg +CURRENT=state +NEXT=state +STATES=S_IDLE,S_PARSE,S_RD_DATA,S_REPORT,S_RX_CMD_L,S_WAIT_RD,S_WR_DATA,'h0 +TRANSITIONS=S_IDLE->'h0, +S_IDLE->S_REPORT, +S_IDLE->S_RX_CMD_L, +S_PARSE->'h0, +S_PARSE->S_WAIT_RD, +S_PARSE->S_WR_DATA, +S_RD_DATA->'h0, +S_RD_DATA->S_IDLE, +S_REPORT->'h0, +S_REPORT->S_IDLE, +S_RX_CMD_L->'h0, +S_RX_CMD_L->S_PARSE, +S_WAIT_RD->'h0, +S_WAIT_RD->S_RD_DATA, +S_WR_DATA->'h0, +S_WR_DATA->S_IDLE, +'h0->S_IDLE diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml new file mode 100644 index 0000000..3252b63 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.exclude.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.exclude.xml new file mode 100644 index 0000000..871fb0a Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.exclude.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml new file mode 100644 index 0000000..dde5a32 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml new file mode 100644 index 0000000..58c56e2 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/Makefile b/uart_thermometer_digital/sim/therm_chip_top/csrc/Makefile new file mode 100644 index 0000000..9f5afa1 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/Makefile @@ -0,0 +1,116 @@ +# Makefile generated by VCS to build your model +# This file may be modified; VCS will not overwrite it unless -Mupdate is used + +# define default verilog source directory +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Choose name of executable +PRODUCTBASE=$(VSRC)/simv + +PRODUCT=$(PRODUCTBASE) + +# Product timestamp file. If product is newer than this one, +# we will also re-link the product. +PRODUCT_TIMESTAMP=product_timestamp + +# Path to runtime library +DEPLIBS= +VCSUCLI=-lvcsucli +RUNTIME=-lvcsnew -lsimprofile -lreader_common /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libBA.a -luclinative /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_tls.o $(DEPLIBS) + +VCS_SAVE_RESTORE_OBJ=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ + +# Strip Flags for target product +STRIPFLAGS= + +PRE_LDFLAGS= # Loader Flags +LDFLAGS= -rdynamic -Wl,-rpath=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib -L/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib +# Picarchive Flags +PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir + +# C run time startup +CRT0= +# C run time startup +CRTN= +# Machine specific libraries +SYSLIBS=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + +CFLAGS_O0=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O0 -fno-strict-aliasing + +CFLAGS_CG=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O -fno-strict-aliasing + +LD_PARTIAL_LOADER=ld +# Partial linking +LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o +ASFLAGS= +LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs +# Note: if make gives you errors about include, either get gmake, or +# replace the following line with the contents of the file filelist, +# EACH TIME IT CHANGES +# included file defines OBJS, and is automatically generated by vcs +include filelist + +OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS) + +product : $(PRODUCT_TIMESTAMP) + @echo $(PRODUCT) up to date + +objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) + +clean : + rm -f $(VCS_OBJS) $(CU_OBJS) + +clobber : clean + rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP) + +picclean : + @rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so + @rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null + +product_clean_order : + @$(MAKE) -f Makefile --no-print-directory picclean + @$(MAKE) -f Makefile --no-print-directory product_order + +product_order : $(PRODUCT) + +$(PRODUCT_TIMESTAMP) : product_clean_order + @-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi + @$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN) + @rm -f csrc[0-9]*.o + @touch $(PRODUCT_TIMESTAMP) + @-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi + +$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvcsnew.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsimprofile.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libreader_common.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libBA.a /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libuclinative.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_tls.o /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ) + @touch $(PRODUCT) + diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/Makefile.hsopt b/uart_thermometer_digital/sim/therm_chip_top/csrc/Makefile.hsopt new file mode 100644 index 0000000..dcb7127 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/Makefile.hsopt @@ -0,0 +1,47 @@ +# Makefile generated by VCS to build rmapats.so for your model +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc + +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ +# Loader Flags +LDFLAGS= + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + +CFLAGS_CG=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O -fno-strict-aliasing + +ASFLAGS= +LIBS= + +include filelist.hsopt + + +rmapats.so: $(HSOPT_OBJS) + @$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS) diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/SIM_l.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/SIM_l.o new file mode 100644 index 0000000..8fd683e Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/SIM_l.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_131020_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_131020_archive_1.so new file mode 100644 index 0000000..3e06bf7 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_131020_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131020_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_131039_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_131039_archive_1.so new file mode 100644 index 0000000..bcc14ae --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_131039_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131039_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_131040_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_131040_archive_1.so new file mode 100644 index 0000000..cd1589e --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_131040_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131040_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_14790_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_14790_archive_1.so new file mode 100644 index 0000000..44ea7b8 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_14790_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_14790_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_14816_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_14816_archive_1.so new file mode 100644 index 0000000..55f5635 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_14816_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_14816_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_26119_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_26119_archive_1.so new file mode 100644 index 0000000..545c5ef --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_26119_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_26119_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_30584_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_30584_archive_1.so new file mode 100644 index 0000000..9133c58 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_30584_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_30584_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_30603_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_30603_archive_1.so new file mode 100644 index 0000000..fcc4502 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_30603_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_30603_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_34047_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_34047_archive_1.so new file mode 100644 index 0000000..9e97f51 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_34047_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_34047_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_34065_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_34065_archive_1.so new file mode 100644 index 0000000..0b40fdc --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_34065_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_34065_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_37423_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_37423_archive_1.so new file mode 100644 index 0000000..2f072cf --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_37423_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_37423_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_37441_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_37441_archive_1.so new file mode 100644 index 0000000..52cc95a --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_37441_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_37441_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_39101_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_39101_archive_1.so new file mode 100644 index 0000000..4566c55 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_39101_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_39101_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_39120_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_39120_archive_1.so new file mode 100644 index 0000000..8b2b889 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_39120_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_39120_archive_1.so \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_40330_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/csrc/_40330_archive_1.so new file mode 100644 index 0000000..7b4dd8a --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_40330_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_40330_archive_1.so \ No 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--- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/_vcs_pli_stub_.c @@ -0,0 +1,964 @@ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* VCS_dlsymLookup(const char *); +extern void vcsMsgReportNoSource1(const char *, const char*); + +/* PLI routine: $fsdbDumpvars:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars +#define __VCS_PLI_STUB_novas_call_fsdbDumpvars +extern void novas_call_fsdbDumpvars(int data, int reason); +#pragma weak novas_call_fsdbDumpvars +void novas_call_fsdbDumpvars(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */ + +/* PLI routine: $fsdbDumpvars:misc */ +#ifndef __VCS_PLI_STUB_novas_misc +#define __VCS_PLI_STUB_novas_misc +extern void novas_misc(int data, int reason, int iparam ); +#pragma weak novas_misc +void novas_misc(int data, int reason, int iparam ) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason, iparam ); + } +} +void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc; +#endif /* __VCS_PLI_STUB_novas_misc */ + +/* PLI routine: $fsdbDumpvarsByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +extern void novas_call_fsdbDumpvarsByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpvarsByFile +void novas_call_fsdbDumpvarsByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */ + +/* PLI routine: $fsdbAddRuntimeSignal:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +extern void novas_call_fsdbAddRuntimeSignal(int data, int reason); +#pragma weak novas_call_fsdbAddRuntimeSignal +void novas_call_fsdbAddRuntimeSignal(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal; +#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */ + +/* PLI routine: $sps_create_transaction_stream:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +extern void novas_call_sps_create_transaction_stream(int data, int reason); +#pragma weak novas_call_sps_create_transaction_stream +void novas_call_sps_create_transaction_stream(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream; +#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */ + +/* PLI routine: $sps_begin_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction +#define __VCS_PLI_STUB_novas_call_sps_begin_transaction +extern void novas_call_sps_begin_transaction(int data, int reason); +#pragma weak novas_call_sps_begin_transaction +void novas_call_sps_begin_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */ + +/* PLI routine: $sps_end_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction +#define __VCS_PLI_STUB_novas_call_sps_end_transaction +extern void novas_call_sps_end_transaction(int data, int reason); +#pragma weak novas_call_sps_end_transaction +void novas_call_sps_end_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */ + +/* PLI routine: $sps_free_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction +#define __VCS_PLI_STUB_novas_call_sps_free_transaction +extern void novas_call_sps_free_transaction(int data, int reason); +#pragma weak novas_call_sps_free_transaction +void novas_call_sps_free_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */ + +/* PLI routine: $sps_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute +#define __VCS_PLI_STUB_novas_call_sps_add_attribute +extern void novas_call_sps_add_attribute(int data, int reason); +#pragma weak novas_call_sps_add_attribute +void novas_call_sps_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */ + +/* PLI routine: $sps_update_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_update_label +#define __VCS_PLI_STUB_novas_call_sps_update_label +extern void novas_call_sps_update_label(int data, int reason); +#pragma weak novas_call_sps_update_label +void novas_call_sps_update_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label; +#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */ + +/* PLI routine: $sps_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation +#define __VCS_PLI_STUB_novas_call_sps_add_relation +extern void novas_call_sps_add_relation(int data, int reason); +#pragma weak novas_call_sps_add_relation +void novas_call_sps_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */ + +/* PLI routine: $fsdbWhatif:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif +#define __VCS_PLI_STUB_novas_call_fsdbWhatif +extern void novas_call_fsdbWhatif(int data, int reason); +#pragma weak novas_call_fsdbWhatif +void novas_call_fsdbWhatif(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif; +#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */ + +/* PLI routine: $paa_init:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_init +#define __VCS_PLI_STUB_novas_call_paa_init +extern void novas_call_paa_init(int data, int reason); +#pragma weak novas_call_paa_init +void novas_call_paa_init(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init; +#endif /* __VCS_PLI_STUB_novas_call_paa_init */ + +/* PLI routine: $paa_sync:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_sync +#define __VCS_PLI_STUB_novas_call_paa_sync +extern void novas_call_paa_sync(int data, int reason); +#pragma weak novas_call_paa_sync +void novas_call_paa_sync(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync; +#endif /* __VCS_PLI_STUB_novas_call_paa_sync */ + +/* PLI routine: $fsdbDumpClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +extern void novas_call_fsdbDumpClassMethod(int data, int reason); +#pragma weak novas_call_fsdbDumpClassMethod +void novas_call_fsdbDumpClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */ + +/* PLI routine: $fsdbSuppressClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +extern void novas_call_fsdbSuppressClassMethod(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassMethod +void novas_call_fsdbSuppressClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */ + +/* PLI routine: $fsdbSuppressClassProp:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +extern void novas_call_fsdbSuppressClassProp(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassProp +void novas_call_fsdbSuppressClassProp(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */ + +/* PLI routine: $fsdbDumpMDAByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +extern void novas_call_fsdbDumpMDAByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpMDAByFile +void novas_call_fsdbDumpMDAByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */ + +/* PLI routine: $fsdbTrans_create_stream_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_begin +void novas_call_fsdbEvent_create_stream_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */ + +/* PLI routine: $fsdbTrans_define_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_stream_attribute +void novas_call_fsdbEvent_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_create_stream_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +extern void novas_call_fsdbEvent_create_stream_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_end +void novas_call_fsdbEvent_create_stream_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */ + +/* PLI routine: $fsdbTrans_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin +extern void novas_call_fsdbEvent_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_begin +void novas_call_fsdbEvent_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */ + +/* PLI routine: $fsdbTrans_set_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +extern void novas_call_fsdbEvent_set_label(int data, int reason); +#pragma weak novas_call_fsdbEvent_set_label +void novas_call_fsdbEvent_set_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */ + +/* PLI routine: $fsdbTrans_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +extern void novas_call_fsdbEvent_add_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_attribute +void novas_call_fsdbEvent_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */ + +/* PLI routine: $fsdbTrans_add_tag:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +extern void novas_call_fsdbEvent_add_tag(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_tag +void novas_call_fsdbEvent_add_tag(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */ + +/* PLI routine: $fsdbTrans_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_end +extern void novas_call_fsdbEvent_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_end +void novas_call_fsdbEvent_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */ + +/* PLI routine: $fsdbTrans_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +extern void novas_call_fsdbEvent_add_relation(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_relation +void novas_call_fsdbEvent_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */ + +/* PLI routine: $fsdbTrans_get_error_code:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +extern void novas_call_fsdbEvent_get_error_code(int data, int reason); +#pragma weak novas_call_fsdbEvent_get_error_code +void novas_call_fsdbEvent_get_error_code(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */ + +/* PLI routine: $fsdbTrans_add_stream_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_stream_attribute +void novas_call_fsdbTrans_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_add_scope_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_scope_attribute +void novas_call_fsdbTrans_add_scope_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */ + +/* PLI routine: $sps_interactive:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_interactive +#define __VCS_PLI_STUB_novas_call_sps_interactive +extern void novas_call_sps_interactive(int data, int reason); +#pragma weak novas_call_sps_interactive +void novas_call_sps_interactive(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive; +#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */ + +/* PLI routine: $sps_test:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_test +#define __VCS_PLI_STUB_novas_call_sps_test +extern void novas_call_sps_test(int data, int reason); +#pragma weak novas_call_sps_test +void novas_call_sps_test(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test; +#endif /* __VCS_PLI_STUB_novas_call_sps_test */ + +/* PLI routine: $fsdbDumpClassObject:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +extern void novas_call_fsdbDumpClassObject(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObject +void novas_call_fsdbDumpClassObject(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */ + +/* PLI routine: $fsdbDumpClassObjectByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObjectByFile +void novas_call_fsdbDumpClassObjectByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */ + +/* PLI routine: $ridbDump:call */ +#ifndef __VCS_PLI_STUB_novas_call_ridbDump +#define __VCS_PLI_STUB_novas_call_ridbDump +extern void novas_call_ridbDump(int data, int reason); +#pragma weak novas_call_ridbDump +void novas_call_ridbDump(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump; +#endif /* __VCS_PLI_STUB_novas_call_ridbDump */ + +/* PLI routine: $sps_flush_file:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file +#define __VCS_PLI_STUB_novas_call_sps_flush_file +extern void novas_call_sps_flush_file(int data, int reason); +#pragma weak novas_call_sps_flush_file +void novas_call_sps_flush_file(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file; +#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */ + +/* PLI routine: $fsdbDumpSingle:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle +#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle +extern void novas_call_fsdbDumpSingle(int data, int reason); +#pragma weak novas_call_fsdbDumpSingle +void novas_call_fsdbDumpSingle(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */ + +/* PLI routine: $fsdbDumpIO:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO +#define __VCS_PLI_STUB_novas_call_fsdbDumpIO +extern void novas_call_fsdbDumpIO(int data, int reason); +#pragma weak novas_call_fsdbDumpIO +void novas_call_fsdbDumpIO(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */ + +#ifdef __cplusplus +} +#endif diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/_vcs_pli_stub_.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/_vcs_pli_stub_.o new file mode 100644 index 0000000..7927935 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/_vcs_pli_stub_.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a b/uart_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a new file mode 100644 index 0000000..fafaad6 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/archive.17/_57246_archive_1.a.info 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/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so + +# This file is automatically generated by VCS. Any changes you make to it +# will be overwritten the next time VCS is run +VCS_LIBEXT= +XTRN_OBJS= + +DPI_WRAPPER_OBJS = +DPI_STUB_OBJS = +# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS +include filelist.dpi +PLI_STUB_OBJS = +include filelist.pli + +include filelist.hsopt + +include filelist.cu + +VCS_MISC_OBJS= +VCS_INCR_OBJS= + + +AUGDIR= +AUG_LDFLAGS= +SHARED_OBJ_SO= + + + +VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS) diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.cu b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.cu new file mode 100644 index 0000000..ab65b79 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.cu @@ -0,0 +1,58 @@ +PIC_LD=ld + +ARCHIVE_OBJS= +ARCHIVE_OBJS += _57246_archive_1.so +_57246_archive_1.so : archive.17/_57246_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_57246_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_57246_archive_1.so $@ + + +ARCHIVE_OBJS += _57264_archive_1.so +_57264_archive_1.so : archive.17/_57264_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_57264_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_57264_archive_1.so $@ + + +ARCHIVE_OBJS += _prev_archive_1.so +_prev_archive_1.so : archive.17/_prev_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_prev_archive_1.so $@ + + + +VCS_ARC0 =_csrc0.so + +VCS_OBJS0 =objs/amcQw_d.o + + +O0_OBJS = + +$(O0_OBJS) : %.o: %.c + $(CC_CG) $(CFLAGS_O0) -c -o $@ $< + + +%.o: %.c + $(CC_CG) $(CFLAGS_CG) -c -o $@ $< + +$(VCS_ARC0) : $(VCS_OBJS0) + $(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0) + rm -f $(VCS_ARC0) + @ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0) + +CU_UDP_OBJS = \ + + +CU_LVL_OBJS = \ +SIM_l.o + +MAIN_OBJS = \ + + +CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS) + diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.dpi b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.dpi new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt new file mode 100644 index 0000000..468b268 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt @@ -0,0 +1,13 @@ +rmapats_mop.o: rmapats.m + @/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o + +rmapats.o: rmapats.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c +rmapats%.o: rmapats%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< +rmar.o: rmar.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c +rmar%.o: rmar%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< + +include filelist.hsopt.objs diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs new file mode 100644 index 0000000..4c31419 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs @@ -0,0 +1 @@ +LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.objs b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.objs new file mode 100644 index 0000000..f40e57c --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.hsopt.objs @@ -0,0 +1,7 @@ +HSOPT_OBJS +=rmapats_mop.o \ + rmapats.o \ + rmar.o rmar_nd.o + +include filelist.hsopt.llvm2_0.objs +HSOPT_OBJS += $(LLVM_OBJS) + diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.pli b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.pli new file mode 100644 index 0000000..653944b --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/filelist.pli @@ -0,0 +1,4 @@ +PLI_STUB_OBJS += _vcs_pli_stub_.o +_vcs_pli_stub_.o: _vcs_pli_stub_.c + @$(CC) -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c + @strip -g _vcs_pli_stub_.o diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/hsim/hsim.sdb b/uart_thermometer_digital/sim/therm_chip_top/csrc/hsim/hsim.sdb new file mode 100644 index 0000000..db7720b Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/hsim/hsim.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/import_dpic.h b/uart_thermometer_digital/sim/therm_chip_top/csrc/import_dpic.h new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/objs/amcQw_d.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/objs/amcQw_d.o new file mode 100644 index 0000000..8656eab Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/objs/amcQw_d.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/pre.cgincr.sdb b/uart_thermometer_digital/sim/therm_chip_top/csrc/pre.cgincr.sdb new file mode 100644 index 0000000..b0ccfff Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/pre.cgincr.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/product_timestamp b/uart_thermometer_digital/sim/therm_chip_top/csrc/product_timestamp new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.c b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.c new file mode 100644 index 0000000..0c43907 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.c @@ -0,0 +1,43 @@ +// file = 0; split type = patterns; threshold = 100000; total count = 0. +#include +#include +#include +#include "rmapats.h" + +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685) +{ + U I1547; + U I1548; + U I1549; + struct futq * I1550; + struct dummyq_struct * pQ = I1289; + I1547 = ((U )vcs_clocks) + I685; + I1549 = I1547 & ((1 << fHashTableSize) - 1); + I1283->I727 = (EBLK *)(-1); + I1283->I731 = I1547; + if (I1547 < (U )vcs_clocks) { + I1548 = ((U *)&vcs_clocks)[1]; + sched_millenium(pQ, I1283, I1548 + 1, I1547); + } + else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) { + I1283->I733 = (struct eblk *)peblkFutQ1Tail; + peblkFutQ1Tail->I727 = I1283; + peblkFutQ1Tail = I1283; + } + else if ((I1550 = pQ->I1190[I1549].I745)) { + I1283->I733 = (struct eblk *)I1550->I744; + I1550->I744->I727 = (RP )I1283; + I1550->I744 = (RmaEblk *)I1283; + } + else { + sched_hsopt(pQ, I1283, I1547); + } +} +#ifdef __cplusplus +extern "C" { +#endif +void SinitHsimPats(void); +#ifdef __cplusplus +} +#endif diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.h b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.h new file mode 100644 index 0000000..680890e --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.h @@ -0,0 +1,2474 @@ +#ifndef __DO_RMAHDR_ +#define __DO_RMAHDR_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define VCS_RTLIB_TLS_MODEL __attribute__((tls_model("initial-exec"))) + +typedef unsigned long UP; +typedef unsigned U; +typedef unsigned char UB; +typedef unsigned char scalar; +typedef struct vec32 vec32; +typedef unsigned short US; +typedef unsigned char SVAL; +typedef unsigned char TYPEB; +typedef struct qird QIRD; +typedef unsigned char UST_e; +typedef unsigned uscope_t; +typedef U NumLibs_t; +struct vec32 { + U I1; + U I2; +}; +typedef unsigned long RP; +typedef unsigned long RO; +typedef unsigned long long ULL; +typedef U GateCount; +typedef U NodeCount; +typedef unsigned short HsimEdge; +typedef unsigned char HsimExprChar; +typedef struct { + U I706; + RP I707; +} RmaReceiveClock1; +typedef NodeCount FlatNodeNum; +typedef U InstNum; +typedef unsigned ProcessNum; +typedef unsigned long long TimeStamp64; +typedef unsigned long long TimeStamp; +typedef enum { + PD_SING = 0, + PD_RF = 1, + PD_PLSE = 2, + PD_PLSE_RF = 3, + PD_NULL = 4 +} PD_e; +typedef TimeStamp RmaTimeStamp; +typedef TimeStamp64 RmaTimeStamp64; +typedef struct { + int * I708; + int * I709; + int I710; + union { + long long enumDesc; + long long classId; + } I711; +} TypeData; +struct etype { + U I586 :8; + U I587; + U I588; + U I589 :1; + U I590 :1; + U I591 :1; + U I592 :1; + U I593 :1; + U I594 :1; + U I595 :1; + U I596 :1; + U I597 :1; + U I598 :4; + U I599 :1; + U I600 :1; + U I601 :1; + U I602 :1; + U I603 :1; + U I604 :1; + U I605 :1; + U I606 :1; + U I607 :2; + U I608 :1; + U I609 :2; + U I610 :1; + U I611 :1; + U I612 :1; + U I613 :1; + U I614 :1; + U I615 :1; + TypeData * I616; + U I617; + U I618; + U I619 :1; + U I620 :1; + U I621 :1; + U I622 :1; + U I623 :2; + U I624 :2; + U I625 :1; + U I626 :1; + U I627 :1; + U I628 :1; + U I629 :1; + U I630 :1; + U I631 :1; + U I632 :1; + U I633 :1; + U I634 :1; + U I635 :1; + U I636 :13; +}; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} rma_clock_struct; +typedef struct eblk EBLK; +typedef int (* E_fn)(void); +typedef struct eblk { + struct eblk * I727; + E_fn I728; + struct iptmpl * I729; + unsigned I731; + unsigned I732; + struct eblk * I733; +} eblk_struct; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; +} RmaEblk; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; + unsigned val; +} RmaEblklq; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} clock_struct; +typedef clock_struct RmaClockStruct; +typedef struct RmaRetain_t RmaRetain; +struct RmaRetain_t { + RP I769; + RmaEblk I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I569 :1; + scalar newval; + scalar I780; + RP I781; +}; +struct retain_t { + struct retain_t * I769; + EBLK I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I778 :1; + scalar newval; + scalar I780; + void * I781; +}; +typedef struct MPSched MPS; +typedef struct RmaMPSched RmaMps; +struct MPSched { + MPS * I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + EBLK I766; + void * I767; + UP I768[1]; +}; +struct RmaMPSched { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + RP I767; + RP I768[1]; +}; +typedef struct RmaMPSchedPulse RmaMpsp; +struct RmaMPSchedPulse { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar I181; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U I789; + RmaClockStruct I790; + RmaClockStruct I791; + U state; + U I792; + RP I729; + RP I793; + RP I794; + RP I768[1]; +}; +typedef struct MPItem MPI; +struct MPItem { + U * I796; + void * I797; +}; +typedef struct { + RmaEblk I726; + RP I798; + scalar I799; + scalar I777; + scalar I800; +} RmaTransEventHdr; +typedef struct RmaMPSchedPulseNewCsdf RmaMpspNewCsdf; +struct RmaMPSchedPulseNewCsdf { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U state :4; + U I802 :28; + RmaClockStruct I790; + RmaClockStruct I791; + RP I803; + RP I729; + RP I804; + RP I768[1]; +}; +typedef struct red_t { + U I805; + U I806; + U I685; +} RED; +typedef struct predd { + PD_e I181; + RED I807[0]; +} PREDD; +union rhs_value { + vec32 I808; + scalar I799; + vec32 * I777; + double I809; + U I810; +}; +typedef struct nbs_t { + struct nbs_t * I811; + struct nbs_t * I813; + void (* I814)(struct nbs_t * I781); + U I815 :1; + U I816 :1; + U I817 :1; + U I818 :1; + U I819 :1; + U I820 :1; + U I821 :26; + U I822; + void * I823; + union rhs_value I824; + vec32 I718; + union { + struct nbs_t * first; + struct nbs_t * last; + } I826; +} NBS; +typedef struct { + RP I827; + RP I793; + RP I729; + RP I794; + RmaEblk I726; + RmaEblk I828; + RP I829; + scalar I799; + scalar I777; + char state; + uscope_t I830; + U I831; + RP I832; + scalar I786; + scalar I787; + scalar I788; + RmaClockStruct I790; + RmaClockStruct I791; + RP I767; +} RmaPulse; +typedef enum { + QIRDModuleC = 1, + QIRDSVPackageC = 2, + QIRDSpiceModuleC = 3 +} QIRDModuleType; +typedef struct { + U I836 :1; + U I837 :1; + U I838 :1; + U I839 :1; + U I840 :1; + U I841 :1; + U I842 :1; + U I843 :1; + U I844 :1; + U I845 :1; + U I846 :1; + U I847 :1; + U I848 :1; + U I849 :1; + U I850 :1; + U I851 :1; + U I852 :1; + U I853 :1; + QIRDModuleType I854 :2; + U I855 :1; + U I856 :1; + U I857 :1; + U I858 :1; + U I859 :1; + U I860 :1; + U I861 :1; + U I862 :1; + U I863 :1; + U I864 :1; + U I865 :1; + U I866 :1; + U I867 :1; + U I868 :1; + U I869 :1; + U I870 :1; + U I871 :1; + U I872 :1; + U I873 :1; + U I874 :1; +} BitFlags; +struct qird { + US I4; + US I5; + U I6; + U I7; + char * I8; + char * I9; + U * I10; + char * I11; + char * I12; + U I13; + U I14; + struct vcd_rt * I15; + U I17; + struct _vcdOffset_rt * I18; + U I20; + U I21; + U * I22; + U * I23; + void * I24; + void * I25; + U I26; + int I27; + UP I28; + U I29; + U I30; + U I31; + UP I32; + U * I33; + UP I34; + U I35; + BitFlags I36; + U I37; + U I38; + U I39; + U I40; + U I41; + U * I42; + U I43; + U * I44; + U I45; + U I46; + U I47; + U I48; + U I49; + U I50; + U I51; + U * I52; + U * I53; + U I54; + U I55; + U * I56; + U I57; + U * I58; + U I59; + U I60; + U I61; + U I62; + U * I63; + U I64; + U * I65; + U I66; + U I67; + U I68; + U I69; + U I70; + U I71; + U * I72; + char * I73; + U I74; + U I75; + U I76; + U I77; + U I78; + U * I79; + U I80; + U I81; + U I82; + UP * I83; + U I84; + U I85; + U I86; + U I87; + U I88; + U I89; + U * I90; + U I91; + U I92; + U * I93; + U * I94; + U * I95; + U * I96; + U * I97; + U I98; + U I99; + struct taskInfo * I100; + U I102; + U I103; + U I104; + int * I105; + U * I106; + UP * I107; + U * I108; + U I109; + U I110; + U I111; + U I112; + U I113; + struct qrefer * I114; + U * I116; + unsigned * I117; + void * I118; + U I119; + U I120; + struct classStaticReferData * I121; + U I123; + U * I124; + U I125; + U * I126; + U I127; + struct wakeupInfoStruct * I128; + U I130; + U I131; + U I132; + U * I133; + U I134; + U * I135; + U I136; + U I137; + U I138; + U * I139; + U I140; + U * I141; + U I142; + U I143; + U * I144; + U I145; + U I146; + U * I147; + U * I148; + U * I149; + U I150; + U I151; + U I152; + U I153; + U I154; + struct qrefee * I155; + U * I157; + U I158; + struct qdefrefee * I159; + U * I161; + int (* I162)(void); + char * I163; + U I164; + U I165; + void * I166; + void * I167; + NumLibs_t I168; + char * I169; + U * I170; + U I171; + U I172; + U I173; + U I174; + U I175; + U * I176; + U * I177; + int I178; + struct clock_load * I179; + int I194; + struct clock_data * I195; + int I211; + struct clock_hiconn * I212; + U I216; + U I217; + U I218; + U I219; + U * I220; + U * I221; + U I222; + void * I223; + U I224; + U I225; + UP * I226; + void * I227; + U I228; + UP * I229; + U * I230; + int (* I231)(void); + U * I232; + UP * I233; + U * I234; + U I235 :1; + U I236 :31; + U I237; + U I238; + UP * I239; + U * I240; + U I241 :1; + U I242 :1; + U I243 :1; + U I244 :1; + U I245 :28; + U I246; + U I247; + U I248; + U I249 :31; + U I250 :1; + UP * I251; + UP * I252; + U * I253; + U * I254; + U * I255; + U * I256; + UP * I257; + UP * I258; + UP * I259; + U * I260; + UP * I261; + UP * I262; + UP * I263; + UP * I264; + char * I265; + U I266; + U I267; + U I268; + UP * I269; + U I270; + UP * I271; + UP * I272; + UP * I273; + UP * I274; + UP * I275; + UP * I276; + UP * I277; + UP * I278; + UP * I279; + UP * I280; + UP * I281; + UP * I282; + UP * I283; + UP * I284; + U * I285; + U * I286; + UP * I287; + U I288; + U I289; + U I290; + U I291; + U I292; + U I293; + U I294; + U I295; + char * I296; + U * I297; + U I298; + U I299; + U I300; + U I301; + U I302; + UP * I303; + UP * I304; + UP * I305; + UP * I306; + struct daidirInfo * I307; + struct vcs_tftable * I309; + U I311; + UP * I312; + UP * I313; + U I314; + U I315; + U I316; + UP * I317; + U * I318; + UP * I319; + UP * I320; + struct qird_hil_data * I321; + UP (* I323)(void); + UP (* I324)(void); + UP (* I325)(void); + UP (* I326)(void); + UP (* I327)(void); + int * I328; + int (* I329)(void); + char * I330; + UP * I331; + UP * I332; + UP (* I333)(void); + int (* I334)(void); + int * I335; + int (* I336)(void); + int * I337; + char * I338; + U * I339; + U * I340; + U * I341; + U * I342; + void * I343; + U I344; + void * I345; + U I346; + U I347; + U I348; + U I349; + U I350; + U I351; + char * I352; + UP * I353; + U * I354; + U * I355; + U I356 :15; + U I357 :14; + U I358 :1; + U I359 :1; + U I360 :1; + U I361 :3; + U I362 :1; + U I363 :1; + U I364 :17; + U I365 :3; + U I366 :5; + U I367 :1; + U I368 :1; + U I369; + U I370; + struct scope * I371; + U I373; + U I374; + U I375; + U * I376; + U * I377; + U * I378; + U I379; + U I380; + U I381; + struct pcbt * I382; + U I392; + U I393; + U I394; + U I395; + void * I396; + void * I397; + void * I398; + int I399; + U * I400; + U I401; + U I402; + U I403; + U I404; + U I405; + U I406; + U I407; + void * I408; + UP * I409; + U I410; + U I411; + void * I412; + U I413; + void * I414; + U I415; + void * I416; + U I417; + int (* I418)(void); + int (* I419)(void); + void * I420; + void * I421; + void * I422; + U I423; + U I424; + U I425; + U I426; + U I427; + U I428; + char * I429; + U I430; + U * I431; + U I432; + U * I433; + U I434; + U I435; + U I436; + U I437; + U I438; + U I439; + U * I440; + U I441; + U I442; + U * I443; + U I444; + U I445; + U I446; + U * I447; + char * I448; + U I449; + U I450; + U I451; + U I452; + U * I453; + U * I454; + U I455; + U * I456; + U * I457; + U I458; + U I459; + U I460; + UP * I461; + U I462; + U I463; + U I464; + struct cosim_info * I465; + U I467; + U * I468; + U I469; + void * I470; + U I471; + U * I472; + U I473; + struct hybridSimReferrerData * I474; + U I476; + U * I477; + U I478; + U I479; + U * I480; + U I481; + U * I482; + U I483; + U * I484; + U I485; + U I486; + U I487; + U I488; + U I489; + U I490; + U I491; + U I492; + U I493; + U * I494; + U * I495; + void (* I496)(void); + U * I497; + UP * I498; + struct mhdl_outInfo * I499; + UP * I501; + U I502; + UP * I503; + U I504; + void * I505; + U * I506; + void * I507; + char * I508; + int (* I509)(void); + U * I510; + char * I511; + char * I512; + U I513; + U * I514; + char * I515; + U I516; + struct regInitInfo * I517; + UP * I519; + U * I520; + char * I521; + U I522; + U I523; + U I524; + U I525; + U I526; + U I527; + U I528; + U I529; + UP * I530; + U I531; + U I532; + U I533; + U I534; + UP * I535; + U I536; + UP * I537; + U I538; + U I539; + U I540; + U * I541; + U I542; + U I543; + U I544; + U * I545; + U * I546; + UP * I547; + UP * I548; + void * I549; + UP I550; + void * I551; + void * I552; + void * I553; + void * I554; + void * I555; + UP I556; + U * I557; + U * I558; + void * I559; + U I560 :1; + U I561 :31; + U I562; + U I563; + U I564; + int I565; + U I566 :1; + U I567 :1; + U I568 :1; + U I569 :29; + void * I570; + void * I571; + void * I572; + void * I573; + void * I574; + UP * I575; + U * I576; + U I577; + char * I578; + U * I579; + U * I580; + char * I581; + int * I582; + UP * I583; + struct etype * I584; + U I637; + U I638; + U * I639; + struct etype * I640; + U I641; + U I642; + U I643; + U * I644; + void * I645; + U I646; + U I647; + void * I648; + U I649; + U I650; + U * I651; + U * I652; + char * I653; + U I654; + struct covreg_rt * I655; + U I657; + U I658; + U * I659; + U I660; + U * I661; + U I662; + U I663; + U * I664; +}; +typedef struct pcbt { + U * I384; + UP I385; + U I386; + U I387; + U I388; + U I389; + U I390; + U I391; +} PCBT; +struct iptmpl { + QIRD * I734; + struct vcs_globals_t * I735; + void * I737; + UP I738; + UP I739; + struct iptmpl * I729[2]; +}; +typedef unsigned long long FileOffset; +typedef struct _RmaMultiInputTable { + U I881 :1; + U I882 :1; + U I672 :2; + U I673 :4; + U I674 :5; + U I883 :1; + U I884 :1; + U I885 :1; + U I886 :1; + U I887 :1; + U I888 :1; + U I889; + U I890; + U I203; + U I891; + U I892 :1; + U I893 :31; + union { + U utable; + U edgeInputNum; + } I699; + U I894 :4; + U I895 :4; + U I896 :4; + U I897 :4; + U I898 :4; + U I899 :4; + U I900 :1; + U I901 :1; + U I902 :1; + U I903 :1; + U I904 :5; + HsimExprChar * I905; + UB * I906; + UB * I907; + struct _RmaMultiInputTable * I880; + struct _RmaMultiInputTable * I909; +} RmaMultiInputTable; +typedef struct _HsCgPeriod { + U I955; + U I956; +} HsCgPeriod; +typedef struct { + U I957[2]; + U I958 :1; + U I959 :1; + U I960 :8; + U I961 :8; + U I962 :8; + U I963 :4; + U I964 :1; + U I965 :1; + unsigned long long I966; + unsigned long long I967; + unsigned long long I968; + unsigned long long I969; + unsigned long long I956; + U I955; + U I970; + U I971; + U I972; + U I973; + U I974; + HsCgPeriod * I975[10]; +} HsimSignalMonitor; +typedef struct { + FlatNodeNum I976; + InstNum I977; + U I915; + scalar I978; + UB I979; + UB I980; + UB I981; + UB I982; + UB I983; + UB I984; + U I985; + U I986; + U I987; + U I988; + U I989; + U I990; + U I991; + U I992; + U I993; + HsimSignalMonitor * I994; + RP I995; + RmaTimeStamp64 I996; + U I997; + RmaTimeStamp64 I998; + U I999; + UB I1000; +} HsimNodeRecord; +typedef RP RCICODE; +typedef struct { + RP I1005; + RP I729; +} RmaIbfIp; +typedef struct { + RP I1005; + RP pcode; +} RmaIbfPcode; +typedef struct { + RmaEblk I726; +} RmaEvTriggeredOrSyncLoadCg; +typedef struct { + RO I877; + RP pcode; +} SchedGateFanout; +typedef struct { + RO I877; + RP pcode; + U I936[4]; +} SchedSelectGateFanout; +typedef struct { + RP pcode; + RmaEblklq I726; +} SchedGateEblk; +typedef struct { + RP pcode; + RmaEblklq I726; + UB * I1006; +} SchedSelectGateEblk; +typedef struct { + RP I1007; + RP pfn; + RP pcode; +} RmaSeqPrimOutputEblkData; +typedef struct { + RmaEblk I726; + RP I1008; +} RmaAnySchedSampleSCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I1009; +} RmaAnySchedVCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I776[1]; +} RmaAnySchedWCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + scalar I1010[1]; +} RmaAnySchedECg; +typedef struct { + U I1011; + U I714; + U I915; + U I1012; + RmaIbfIp * I1013; + EBLK I726; + void * val; +} RmaThreadSchedCompiledLoads; +typedef struct { + U I714; + U I722; + RmaThreadSchedCompiledLoads * I1014; +} RmaSchedCompileLoadsCg; +typedef struct { + RP I1015; +} RmaRootCbkCg; +typedef struct { + RP I1016; +} RmaRootForceCbkCg; +typedef struct { + RmaEblk I726; + RP I1017; +} RmaForceCbkJmpCg; +typedef struct { + U I5; + U I722 :31; + U I1018 :1; + vec32 I808; + U I1019; + RP I1020; + RP I1021; +} RmaForceSelectorV; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeDriverGate; +typedef struct { + U I5; + U I668; + RmaIbfPcode I1027[1]; +} RmaNetTypeScatterGate; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeGatherGate; +typedef struct { + RmaIbfPcode I1028; + U I1029 :3; + U I1030 :1; + U I1031 :1; + U I890 :16; +} RmaNbaGateOfn; +typedef struct { + U I5; + NBS I1032; + RmaIbfPcode I1028; +} RmaNbaGate1; +typedef struct { + RP ptable; + RP pfn; + RP pcode; +} Rma1InputGateFaninCgS; +typedef struct RmaSeqPrimOutputS_ RmaSeqPrimOutputOnClkS; +struct RmaSeqPrimOutputS_ { + RP pfn; + RP I1035; + U state; + U I1036; + RP I1037; + U I706; + scalar val; +}; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaCondOptLoad; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaMacroStateUpdate; +typedef struct { + U I5; + U state; + U I1041; + UB I1039; + U * I1042; +} RmaMacroState; +typedef struct { + U iinput; + RP I1043; +} RmaMultiInputLogicGateCg; +typedef struct { + U iinput; + RP ptable; + RP I1043; +} RmaSeqPrimEdgeInputCg; +typedef struct { + RmaEblk I726; + RP pcode; +} RmaSched0GateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; +} RmaUdpDeltaGateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; + scalar I1044; +} RmaSchedDeltaGateCg; +typedef struct { + UB I1045; + RP I1046; + RP I1047; +} RmaPropNodeSeqLhsSCg; +typedef struct { + RmaEblk I726; + RP pcode; + U I915; + U I715[1]; +} RmaBitEdgeEblk; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateBehavioralDelay; +typedef struct { + U I5; + union { + RP I1290; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaMPDelay; +typedef struct { + U I5; + RmaPulse I1048; + RmaIbfPcode I1028; +} RmaMPPulseHybridDelay; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMps I1049; +} RmaMPHybridDelay; +typedef struct { + U I5; + U I1050; + RmaIbfPcode I1028; + RmaEblk I766; +} RmaMPHybridDelayPacked; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMpspNewCsdf I1051; +} RmaMPPulseDelay; +typedef struct { + U I5; + RmaMpsp I1051; + RmaIbfPcode I1028; +} RmaMPPulseOptHybridDelay; +typedef struct _RmaBehavioralTransportDelay { + U I5; + RP I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaBehavioralTransportDelayS; +typedef struct { + U I5; + U I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelay; +typedef struct { + U I5; + U I685; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransZeroDelay; +typedef struct { + U I5; + U I1052; + U I1053; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelayRF; +typedef struct { + U I5; + U I1052; + U I1053; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelayRF; +typedef struct { + U I5; + RP I1054; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaICTransDelay; +typedef struct { + U I5; + RP I1054; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransZeroDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICSimpleDelay; +typedef struct { + U I5; + union { + RP psimple; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaICDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaPortDelay; +typedef struct { + U I890; + RP I1058; +} RmaRtlXEdgesLoad; +typedef struct { + U I5; + RmaRtlXEdgesLoad I1058[(5)]; +} RmaRtlXEdgesHdr; +typedef struct { + U I5; + US I1059; + US I1060 :1; + US I904 :15; + RP I1061; + RP I1062; + RP I1063; +} RmaRtlEdgeBlockHdr; +typedef struct { + RP I1064; + RP I1065; +} RemoteDbsedLoad; +typedef struct { + RmaEblk I726; + RP I1066; + RP I1067; + U I1068 :16; + U I1069 :2; + U I1070 :2; + U I1071 :1; + U I1072 :8; + U I904 :3; + U I471; + RP I1073; + RP I811[(5)]; + RP I813[(5)]; + US I1074; + US I1075; + RemoteDbsedLoad I1076[1]; +} RmaRtlEdgeBlock; +typedef struct TableAssign_ { + struct TableAssign_ * I880; + struct TableAssign_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RP I1043; +} TableAssign; +typedef struct TableAssignLayoutOnClk_ { + struct TableAssignLayoutOnClk_ * I880; + struct TableAssignLayoutOnClk_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RmaSeqPrimOutputOnClkS I1089; + RmaEblk I726; +} TableAssignLayoutOnClk; +typedef struct { + U state; + U I1090; +} RmaSeqPrimOutputOnClkOpt; +typedef struct TableAssignLayoutOnClkOpt_ { + struct TableAssignLayoutOnClkOpt_ * I880; + struct TableAssignLayoutOnClkOpt_ * I798; + U I1092; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RmaSeqPrimOutputOnClkOpt I1089; + RmaSeqPrimOutputEblkData I1093; +} TableAssignLayoutOnClkOpt; +typedef struct { + U I5; + RP I798; + RP I1094; +} RmaTableAssignList; +typedef struct { + U I5; + RP I798; + RP I1094; + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; + RP I1098[0]; +} RmaThreadTableAssignList; +typedef struct { + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; +} RmaThreadTableHeader; +typedef struct { + RP I1064; +} RmaWakeupListCg; +typedef struct { + RP I1064; +} RmaWakeupArrayCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupListCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupArrayCg; +typedef struct { + U I1100; + U I706; + RmaTimeStamp I1101[1]; +} RmaTsArray; +typedef struct { + U iinput; + RP I1102; +} RmaConditionsMdb; +typedef struct { + RP I1103; + RP I1104; + U I1105; +} RmaTcListHeader; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimple; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditional; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOpt; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtc; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimpleNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1035; +} RmaTcCoreSimpleNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditionalNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOptNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + RP I1035; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1035; +} RmaTcCoreConditionalNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + U I1122; + RP I1123; + RP I1124; + RP I1117; + RP I1125; + RP I1126; + RmaTimeStamp I1127; +} RmaTcCoreNochange; +typedef struct { + RP I1128; + RP I880; +} RmaTcCoreNochangeList; +typedef struct { + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoadNoList; +typedef struct { + RP I880; + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoad; +typedef struct { + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOptNoList; +typedef struct { + RP I880; + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOpt; +typedef struct { + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoList; +typedef struct { + RP I1035; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoListMdb; +typedef struct { + RP I880; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtc; +typedef struct { + U I1132; + U I1133; + FlatNodeNum I1004; + U I915; + U I1134; + U I1135; + RmaIbfPcode I1028; + union { + scalar I1136; + vec32 I1137; + scalar * I1138; + vec32 * I1139; + } val; +} RmaScanSwitchData; +typedef struct { + RP I880; + RP I798; + RP I1140; +} RmaDoublyLinkedListElem; +typedef struct { + RP I1141; + U I1142 :1; + U I1143 :1; + U I1144 :1; + U I1145 :4; + U I904 :25; + U I1146; +} RmaSwitchGateInCbkListInfo; +typedef struct { + union { + RmaDoublyLinkedListElem I1640; + RmaSwitchGateInCbkListInfo I2; + } I699; + RmaIbfPcode I1028; +} RmaSwitchGate; +typedef struct RmaNonEdgeLoadData1_ { + US I1147; + scalar val; + scalar I1148 :1; + scalar I1149 :1; + scalar I1150 :1; + scalar I1151 :1; + scalar I1152 :1; + U I1153; + RP I811; + RP I1154; + RP I1004; + RP I1155; + RP I1156; +} RmaNonEdgeLoadData1; +typedef struct RmaNonEdgeLoadHdr1_ { + UB I1148; + UB I1157; + UB I978; + RmaNonEdgeLoadData1 * I1058; + RmaNonEdgeLoadData1 * I798; + void * I1158; +} RmaNonEdgeLoadHdr1; +typedef struct RmaNonEdgeLoadHdrPrl1_ { + U I1159; + RP I721; +} RmaNonEdgeLoadHdrPrl1; +typedef struct RmaChildClockProp_ { + RP I811; + RP I1160; + RP I1004; + RP pcode; + scalar val; +} RmaChildClockProp; +typedef struct RmaChildClockPropList1_ { + RmaChildClockProp * I1058; + RmaChildClockProp * I798; +} RmaChildClockPropList1; +typedef struct { + U I5; + U I1161; +} RmaHDLCosimDUTGate; +typedef struct { + UB I1162; + UB I1163 :1; + UB I1164 :1; + UB I1165 :1; + UB I1166 :1; + UB I904 :4; + US cedges; +} RmaMasterXpropLoadHdr; +typedef struct { + UB I1167; + UB I1168; + UB I1169; + UB I1170; + U cedges :30; + U I1164 :1; + U I1171 :1; + U I1172; + U I1173; + RP I1174; + RP I1175; + RmaRtlEdgeBlockHdr * I1176; +} RmaChildXpropLoadHdr; +struct clock_load { + U I181 :5; + U I182 :12; + U I183 :1; + U I184 :2; + U I185 :1; + U I186 :1; + U I187 :1; + U I188 :9; + U I189; + U I190; + void (* pfn)(void * I192, char val); +}; +typedef struct clock_data { + U I197 :1; + U I198 :1; + U I199 :1; + U I200 :1; + U I181 :5; + U I182 :12; + U I201 :6; + U I202 :1; + U I184 :2; + U I185 :1; + U I188 :1; + U I203; + U I204; + U I205; + U I189; + U I206; + U I207; + U I208; + U I209; + U I210; +} HdbsClockData; +struct clock_hiconn { + U I214; + U I215; + U I189; + U I184; +}; +typedef struct _RmaDaiCg { + RP I1177; + RP I1178; + U I1179; +} RmaDaiCg; +typedef union _RmaCbkMemOptUnion { + RP I1177; + RP I1180; + RP I1181; +} RmaCbkMemOptUnion; +typedef struct _RmaDaiOptCg { + RmaCbkMemOptUnion I1182; +} RmaDaiOptCg; +struct futq_slot2 { + U I758; + U I759[32]; +}; +struct futq_slot1 { + U I755; + struct futq_slot2 I756[32]; +}; +struct futq_info { + scalar * I750; + U I751; + U I752; + struct futq_slot1 I753[32]; +}; +struct futq { + struct futq * I740; + struct futq * I742; + RmaEblk * I743; + RmaEblk * I744; + U I731; + U I1; +}; +struct sched_table { + struct futq * I745; + struct futq I746; + struct hash_bucket * I747; + struct hash_bucket * I749; +}; +struct dummyq_struct { + clock_struct I1183; + EBLK * I1184; + EBLK * I1185; + EBLK * I1186; + struct futq * I1187; + struct futq * I1188; + struct futq * I1189; + struct sched_table * I1190; + struct futq_info * I1192; + struct futq_info * I1194; + U I1195; + U I1196; + U I1197; + U I1198; + U I1199; + U I1200; + U I1201; + struct millenium * I1202; + EBLK * I1204; + EBLK * I1205; + EBLK * I1206; + EBLK * I1207; + EBLK * I1208; + EBLK * I1209; + EBLK * I1210; + EBLK * I1211; + EBLK * I1212; + EBLK * I1213; + EBLK * I1214; + EBLK * I1215; + EBLK * I1216; + EBLK * I1217; + EBLK * I1218; + EBLK * I1219; + EBLK * I1220; + EBLK * I1221; + MPS * I1222; + struct retain_t * I1223; + EBLK * I1224; + EBLK * I1225; + EBLK * I1226; + EBLK * I1227; + EBLK * I1228; + EBLK * I1229; + EBLK * I1230; + EBLK * I1231; + EBLK * I1232; + EBLK * I1233; + EBLK * I1234; + EBLK * I1235; + EBLK * I1236; + EBLK * I1237; + EBLK * I1238; + EBLK * I1239; + EBLK * I1240; + EBLK * I1241; + EBLK * I1242; + EBLK * I1243; + EBLK * I1244; + EBLK * I1245; + EBLK * I1246; + EBLK * I1247; + EBLK * I1248; + EBLK * I1249; + EBLK I1250; + EBLK * I1251; + EBLK * I1252; + EBLK * I1253; + EBLK * I1254; + int I1255; + int I1256; + struct vcs_globals_t * I1257; + clock_struct I1258; + unsigned long long I1259; + EBLK * I1260; + EBLK * I1261; + void * I1262; +}; +typedef void (* FP)(void * , scalar ); +typedef void (* FP1)(void * ); +typedef void (* FPRAP)(void * , vec32 * , U ); +typedef U (* FPU1)(void * ); +typedef void (* FPV)(void * , UB * ); +typedef void (* FPVU)(void * , UB * , U ); +typedef void (* FPLSEL)(void * , scalar , U ); +typedef void (* FPLSELV)(void * , vec32 * , U , U ); +typedef void (* FPFPV)(UB * , UB * , U , U , U , U , U , UB * , U ); +typedef void (* FPFA)(UB * , UB * , U , U , U , U , U , U , UB * , U ); +typedef void (* FPRPV)(UB * , U , U , U ); +typedef void (* FPEVCDLSEL)(void * , scalar , U , UB * ); +typedef void (* FPEVCDLSELV)(void * , vec32 * , U , U , UB * ); +typedef void (* FPNTYPE_L)(void * , void * , U , U , UB * , UB * , UB * , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_H)(void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_LPAP)(void * , void * , void * , U , U , UB * , UB * , U ); +typedef void (* FPNTYPE_HPAP)(void * , void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef struct _lqueue { + EBLK * I727; + EBLK * I1263; + int I1264; + struct _lqueue * I769; +} Queue; +typedef struct { + void * I1266; + void * I1267; + void * I1268[2]; + void * I1269; +} ClkLevel; +typedef struct { + unsigned long long I1270; + EBLK I1171; + U I1271; + U I1272; + union { + void * pHeap; + Queue * pList; + } I699; + unsigned long long I1273; + ClkLevel I1274; + Queue I1275[1]; +} Qhdr; +extern UB Xvalchg[]; +extern UB X4val[]; +extern UB X3val[]; +extern UB X2val[]; +extern UB XcvtstrTR[]; +extern UB Xcvtstr[]; +extern UB Xbuf[]; +extern UB Xbitnot[]; +extern UB Xwor[]; +extern UB Xwand[]; +extern U Xbitnot4val[]; +extern UB globalTable1Input[]; +extern __thread unsigned long long vcs_clocks; +extern UB Xunion[]; +extern U fRTFrcRelCbk; +extern FP txpFnPtr; +extern FP rmaFunctionArray[]; +extern UP rmaFunctionRtlArray[]; +extern FP rmaFunctionLRArray[]; +extern U rmaFunctionCount; +extern U rmaFunctionLRCount; +extern U rmaFunctionLRDummyCount; +extern UP rmaFunctionDummyEndPtr; +extern FP rmaFunctionFanoutArray[]; +extern __thread UB dummyScalar; +extern __thread UB fScalarIsForced; +extern __thread UB fScalarIsReleased; +extern U fNotimingchecks; +extern U fFsdbDumpOn; +extern RP * iparr; +extern FP1 * rmaPostAnySchedFnPtr; +extern FP1 * rmaPostAnySchedFnSamplePtr; +extern FP1 * rmaPostAnySchedVFnPtr; +extern FP1 * rmaPostAnySchedWFnPtr; +extern FP1 * rmaPostAnySchedEFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusNonCongruentFnPtr; +extern FP1 * rmaPostSchedUpdateEvTrigFnPtr; +extern FP1 * rmaSched0UpdateEvTrigFnPtr; +extern FP1 * rmaPostSchedRecoveryResetDbsFnPtr; +extern U fGblDataOrTime0Prop; +extern UB rmaEdgeStatusValArr[]; +extern FP1 * propForceCbkSPostSchedCgFnPtr; +extern FP1 * propForceCbkMemoptSPostSchedCgFnPtr; +extern UB * ptableGbl; +extern U * vcs_ptableOffsetsGbl; +extern UB * expandedClkValues; +extern __thread Qhdr * lvlQueue; +extern __thread unsigned threadIndex; +extern int cPeblkThreads; +extern US xedges[]; +extern U mhdl_delta_count; +extern U ignoreSchedForScanOpt; +extern U fignoreSchedForDeadComboCloud; +extern int fZeroUser; +extern U fEveBusPullVal; +extern U fEveBusPullFlag; +extern U fFutEventPRL; +extern U fParallelEBLK; +extern U fBufferingEvent; +extern __thread UB fNettypeIsForced; +extern __thread UB fNettypeIsReleased; +extern EBLK * peblkFutQ1Head; +extern EBLK * peblkFutQ1Tail; +extern US * edgeActionT; +extern unsigned long long * derivedClk; +extern U fHashTableSize; +extern U fSkipStrChangeOnDelay; +extern U fHsimTcheckOpt; +extern scalar edgeChangeLookUp[4][4]; +extern U fDoingTime0Prop; +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; + + +extern void *mempcpy(void* s1, void* s2, unsigned n); +extern UB* rmaEvalDelays(UB* pcode, scalar val); +extern UB* rmaEvalDelaysV(UB* pcode, vec32* pval); +extern void rmaPopTransEvent(UB* pcode); +extern void rmaSetupFuncArray(UP* ra, U c, U w); +extern void rmaSetupRTLoopReportPtrs(UP* funcs, UP* rtlFuncs, U cnt, U cntDummy, UP end); +extern void SinitHsimPats(void); +extern void VVrpDaicb(void* ip, U nIndex); +extern int SDaicb(void *ip, U nIndex); +extern void SDaicbForHsimNoFlagScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlagStrengthScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlag2(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimWithFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlagFrcRel(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimNoFlagFrcRel2(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void VcsHsimValueChangeCB(void* pRmaDaiCg, void* pValue, unsigned int valueFormat); +extern U isNonDesignNodeCallbackList(void* pRmaDaiCg); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void VVrpNonEventNonRegdScalarForHsimOptCbkMemopt(void* ip, U nIndex); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabFrcRel(U* mem, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimCbkMemOptNoFlagFrcRel(void* pDaiCb, unsigned char reason, int msb, int lsb, int ndx); +extern void hsimDispatchCbkMemOptForVcd(RP p, U val); +extern void* hsimGetCbkMemOptCallback(RP p); +extern void hsimDispatchCbkMemOptNoDynElabS(RP* p, U val, U isStrength); +extern void* hsimGetCbkPtrNoDynElab(RP p); +extern void hsimDispatchCbkMemOptDynElabS(U** pvcdarr, U** pcbkarr, U val, U isScalForced, U isScalReleased, U isStrength); +extern void hsimDispatchCbkMemOptNoDynElabVector(RP* /*RmaDaiOptCg* */p, void* pval, U /*RmaValueType*/ vt, U cbits); +extern void copyAndPropRootCbkCgS(RmaRootCbkCg* pRootCbk, scalar val); +extern void copyAndPropRootCbkCgV(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgW(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgE(RmaRootCbkCg* rootCbk, scalar* pval); +extern void Wsvvar_callback_non_dynamic1(RP* ptr, int); +extern void rmaExecEvSyncList(RP plist); +extern void Wsvvar_callback_virt_intf(RP* ptr); +extern void Wsvvar_callback_hsim_var(RP* ptr); +extern void checkAndConvertVec32To2State(vec32* value, vec32* svalue, U cbits, U* pforcedBits); +extern unsigned int fGblDataOrTime0Prop; +extern void SchedSemiLerMP1(UB* pmps, U partId); +extern void SchedSemiLerMPO(UB* pmpso, U partId); +extern void rmaDummyPropagate(void); +extern RP rmaTestCg(RP pcode, U vt, UB* value); +extern void hsUpdateModpathTimeStamp(UB* pmps); +extern void doMpd32One(UB* pmps); +extern void doMpdCommon(MPS* pmps); +extern TimeStamp GET_DIFF_DELAY_FUNC(TimeStamp ts); +extern void SchedSemiLerMP(UB* ppulse, U partId); +extern EBLK *peblkFutQ1Head; +extern EBLK *peblkFutQ1Tail; +extern void scheduleuna(UB *e, U t); +extern void scheduleuna_mp(EBLK *e, unsigned t); +extern void schedule(UB *e, U t); +extern void sched_hsopt(struct dummyq_struct * pQ, EBLK *e, U t); +extern void sched_millenium(struct dummyq_struct * pQ, void *e, U thigh, U t); +extern void schedule_1(EBLK *e); +extern void sched0(UB *e); +extern void sched0Raptor(UB *e); +extern void sched0lq(EBLK *e); +extern void sched0lqnc(EBLK *e); +extern void sched0una(UB *e); +extern void sched0una_th(struct dummyq_struct *pq, UB *e); +extern void hsopt_sched0u_th(struct dummyq_struct *pq, UB *e); +extern void scheduleuna_mp_th(struct dummyq_struct *pq, EBLK *e, unsigned t); +extern void schedal(UB *e); +extern void sched0_th(struct dummyq_struct * pQ, EBLK *e); +extern void sched0u(UB *e); +extern void sched0u_th(struct dummyq_struct *pq, UB *e); +extern void sched0_hsim_front_th(struct dummyq_struct * pQ, UB *e); +extern void sched0_hsim_frontlq_th(struct dummyq_struct * pQ, UB *e); +extern void sched0lq_th(struct dummyq_struct * pQ, UB *e); +extern void schedal_th(struct dummyq_struct * pQ, UB *e); +extern void scheduleuna_th(struct dummyq_struct * pQ, void *e, U t); +extern void schedule_th(struct dummyq_struct * pQ, UB *e, U t); +extern void schedule_1_th(struct dummyq_struct * pQ, EBLK *peblk); +extern void SetupLER_th(struct dummyq_struct * pQ, EBLK *e); +extern void FsdbReportClkGlitch(UB*,U); +extern void AddToClkGLitchArray(EBLK*); +extern void SchedSemiLer_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXP_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXPFreeVar_th(struct dummyq_struct * pQ, EBLK *e); +extern U getVcdFlags(UB *ip); +extern void VVrpNonEventNonRegdScalarForHsimOpt(void* ip, U nIndex); +extern void VVrpNonEventNonRegdScalarForHsimOpt2(void* ip, U nIndex); +extern void SchedSemiLerTBReactiveRegion(struct eblk* peblk); +extern void SchedSemiLerTBReactiveRegion_th(struct eblk* peblk, U partId); +extern void SchedSemiLerTr(UB* peblk, U partId); +extern void SchedSemiLerNBA(UB* peblk, U partId); +extern void NBA_Semiler(void *ip, void *pNBS); +extern void sched0sd_hsim(UB* peblk); +extern void vcs_sched0sd_hsim_udpclk(UB* peblk); +extern void vcs_sched0sd_hsim_udpclkopt(UB* peblk); +extern void sched0sd_hsim_PRL(UB* peblk); +extern void sched0lq_parallel_clk(EBLK* peblk); +extern U isRtlClockScheduled(EBLK* peblk); +extern void doFgpRaceCheck(UB* pcode, UB* p, U flag); +extern void doSanityLvlCheck(); +extern void sched0lq_parallel_ova(EBLK* peblk); +extern void sched0lq_parallel_ova_precheck(EBLK* peblk); +extern void rmaDlpEvalSeqPrim(UB* peblk, UB val, UB preval); +extern void appendNtcEvent(UB* phdr, scalar s, U schedDelta); +extern void appendTransEventS(RmaTransEventHdr* phdr, scalar s, U schedDelta); +extern void schedRetainHsim(MPS* pMPS, scalar sv, scalar pv); +extern void updateRetainHsim(MPS* pMPS,scalar sv, scalar pv); +extern void hsimCountXEdges(void* record, scalar s); +extern void hsimRegisterEdge(void* sm, scalar s); +extern U pvcsGetPartId(); +extern void HsimPVCSPartIdCheck(U instNo); +extern void debug_func(U partId, struct dummyq_struct* pQ, EBLK* EblkLastEventx); +extern struct dummyq_struct* pvcsGetQ(U thid); +extern EBLK* pvcsGetLastEventEblk(U thid); +extern void insertTransEvent(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, int re, UB* predd, U fpdd); +extern void insertNtcEventRF(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, U* delays); +extern U doTimingViolation(RmaTimeStamp ts,RP* pdata, U fskew, U limit, U floaded, U fcondopt, RmaTimeStamp tsNochange); +extern void sched_gate_hsim(EBLK* peblk, unsigned t, RP* offset, U gd_info, U encodeInPcode, void* propValue); +extern int getCurSchedRegion(); +extern FP getRoutPtr(RP, U); +extern U rmaChangeCheckAndUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern void rmaUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaChangeCheckAndUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaLhsPartSelUpdateE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaUpdateWithForceSelectorE(scalar* pvalDst, scalar* pvalSrc, U cbits, U* pforceSelector); +extern void rmaUpdateWFromE(vec32* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaLhsPartSelWithChangeCheckE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaLhsPartSelWFromE(vec32* pvalDst, scalar* pvalSrc, U index,U width); +extern U rmaChangeCheckAndUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void *VCSCalloc(size_t size, size_t count); +extern void *VCSMalloc(size_t size); +extern void VCSFree(void *ptr); +extern U rmaLhsPartSelWithChangeCheckW(vec32* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern U rmaLhsPartSelWithChangeCheckEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelUpdateW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void rmaEvalWunionW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWorW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWandW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalUnionE(scalar* dst, scalar* src, U cbits, U count, RP ptable); +typedef U RmaCgFunctionType; +extern RmaIbfPcode* rmaEvalPartSelectsW(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWLe32(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWToE(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern RmaIbfPcode* rmaEvalPartSelectsEToE(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsEToW(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern U rmaEvalBitPosEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U VcsForceVecVCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U/*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecVCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecWCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecWCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecECg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecACg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecCg(UB* pcode, UB* pvDst, U ibeginDst, U width, U /*RmaValueType*/ type,U fisRoot, UB* prhsDst, U frhs, U* pforcedbits); +extern U VcsDriveBitsAndDoChangeCheckV(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckW(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckE(scalar* pvSel, scalar* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern void cgvecDebug_Eblk(UB* pcode); +extern U rmaCmpW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void copyVec32ArrMask(vec32* pv1, vec32* pv2, U len, U* mask); +extern void* memcpy(void*, const void*, size_t); +extern int memcmp(const void*, const void*, size_t); +extern void propagateScanOptPathVal(EBLK *peblk); +extern UB* rmaProcessScanSwitches(UB* pcode, scalar val); +extern UB* rmaProcessScanSwitchesV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanoptDump(UB* pcode, scalar val); +extern UB* rmaProcessScanoptDumpV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanChainOptSeqPrims(UB* pcode, scalar val); +extern void rmaProcessPvcsCcn(UB* pcode, scalar val); +extern void rmaProcessPvcsCcnE(UB* pcode, scalar* val); +extern void rmaProcessPvcsCcnW(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnV(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnCompiledS(UB* pcode, U offset, scalar ibnval); +extern void rmaProcessPvcsCcnCompiledV(UB* pcode, U offset, vec32* pval); +extern void schedResetRecoveryDbs(U cedges, EBLK* peblkFirst); +extern UB* rmaEvalUnaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVOneFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVLargeFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalAndOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpV(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpV(UB* pcode, vec32* value); +extern UB* rmaEvalTernaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalTernaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalBinaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpS(UB* pcode, scalar val); +extern scalar rmaGetScalarFromWCg(vec32* pval, U index); +extern void rmaSetScalarInWCg(vec32* pval, U index, scalar s); +extern void rmaSetWInW(vec32* dst, vec32* src, U index, U indexSrc, U width); +extern void rmaCountRaptorBits(void* pval, void* pvalPrev, U cbits, U vt); +extern void setHsimFunc(void* ip); +extern void unsetHsimFunc(void* ip); +extern UB* getEvcdStatusByFlagsE(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsV(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsW(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsS(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table); +extern UB* getSingleDrvEvcdStatusS(UB value, U fTBDriver); +extern UB* getSingleDrvEvcdStatusE(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusV(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusW(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getEvcdStatusByDrvEvcdStatus(UB* pdrvevcdStatus, U cdrivers, UB* table, U cbits); +extern void evcdCallback(UP pcode, U cbits); +extern UB* getSavedEvcdStatus(void); +extern void saveEvcdStatus(UB*); +extern void mhdlMarkExport(void*, U); +extern void levelInsertQueue(int); +extern void VcsRciRtl(RP pcode); +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; +extern void rtSched0LoopDectDumpProcess(void* e, void* rtn, void* PQ); +extern void pushHsimRtnCtxt(void* pcode); +extern void popHsimRtnCtxt(); +extern EBLK* loopReportInlinedSched0Wrapper(EBLK *peblk); +extern void loopReportSched0Wrapper(EBLK *peblk, unsigned int sfType, unsigned int fTH, struct dummyq_struct* pq); +extern void loopReportSchedSemiLerWrapper(EBLK *peblk, int sfType); +extern void CallGraphPushNodeAndAddToGraph(UP flatNode, UP instNum, U dummy); +extern void CallGraphPopNode(void); +extern RP elabGetIpTpl(U in); +extern U rmaEvalBitBothEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQXW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval01EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval0XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval10EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval1XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX1EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX0EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitPosEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitBothEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern void rmaScheduleNbaGate(RP pcode, scalar val); +extern void rmaEvalRtlEdgeLoads(RmaRtlEdgeBlockHdr *phdr, US clkEdge, scalar clkVal, scalar prevClkVal, scalar val4, scalar prevval4, scalar master4val); +extern void rmaEvaluateDynamicGateLoadsCg(RP p, scalar s); +extern void rmaEvaluateFusedWithDynamicGateLoadsCg(RP p, scalar s); +extern void rmaScheduleGatedClockEdgeLoadNew(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaScheduleGatedClockEdgeLoad(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaRemoveNonEdgeLoads(UB* pcode); +extern void rmaRecordEvents(HsimNodeRecord *pnr); +extern void handlePCBs(UB* p, U i); +extern void markMasterClkOvaLists(U fdbs, RP p); +extern void rmaChildClockPropAfterWrite(UB* p); +extern void rmaSchedChildClockPropAfterWrite(UB* p, UB* pmasterList, UB val); +extern void HDLCosimProcessDUTInputChange(U inputId, void* val); +extern void rmaChangeListForMovedGates(UB clkVal, UB f10Edge, UB* subMasterVal, UB* plist, RP* p, U count); +extern void rmaEvalSeqPrimLoadsByteArray(UB* pcode, UB val, UB prevval4); +extern void rmaEvalSeqPrimLoadsByteArrayX(UB* pcode, UB val, UB prevval4); +extern void vcsRmaEvalSeqPrimLoadsByteArraySCT(UB* pcode, UB val, UB prevval4, U c); +extern void vcsAbortForBadEBlk(void); +extern scalar edgeChangeLookUp[4][4]; +extern void Wsvvar_sched_virt_intf_eval(RP* ptr); +extern void vcs_hwcosim_drive_dut_scalar(uint id, char val); +extern void vcs_hwcosim_drive_dut_vector_4state(uint id, vec32* val); +extern U vcs_rmaGetClkValForSeqUdpLayoutOnClkOpt(UB* poutput); +extern U rmaIsS2State(scalar s); +extern U rmaIsV2State(vec32* pval, U cbits); +extern U rmaIsW2State(vec32* pval, U cbits); +extern U rmaIsE2State(scalar* pval, U cbits); +extern void rmaUpdateRecordFor2State(HsimNodeRecord* record, U f2state); +typedef void (*FuncPtr)(); +static inline U asm_bsf (U in) +{ +#if defined(linux) + U out; +#if !defined(__aarch64__) + asm ("movl %1, %%eax; bsf %%eax, %%eax; movl %%eax, %0;" + :"=r"(out) + :"r"(in) + :"%eax" + ); +#else + out = ffs(in) - 1; +#endif + return out; +#else + return 0; +#endif +} + + +#ifdef __cplusplus +extern "C" { +#endif +void hs_0_M_0_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_0_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_1_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_1_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_2_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_2_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_3_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_3_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_4_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_4_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_5_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_5_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_5_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_6_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_7_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_7_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_8_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_8_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_9_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_10_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_11_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_12_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_13_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_14_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_15_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_17_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_18_0__simv_daidir (UB * pcode, scalar val); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + } +#endif +#endif /*__DO_RMAHDR_*/ + diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.m b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.m new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.o new file mode 100644 index 0000000..d0c32e0 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats_mop.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats_mop.o new file mode 100644 index 0000000..2fa2e54 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmapats_mop.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.c b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.c new file mode 100644 index 0000000..21b81fa --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.c @@ -0,0 +1,13 @@ +#include +#include +#include "rmar0.h" + +// stubs for Hil functions +#ifdef __cplusplus +extern "C" { +#endif +void __Hil__Static_Init_Func__(void) {} +#ifdef __cplusplus +} +#endif + diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.h b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.h new file mode 100644 index 0000000..77865aa --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.h @@ -0,0 +1,18 @@ +#ifndef _RMAR1_H_ +#define _RMAR1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __DO_RMAHDR_ +#include "rmar0.h" +#endif /*__DO_RMAHDR_*/ + +extern UP rmaFunctionRtlArray[]; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.o new file mode 100644 index 0000000..1989370 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar0.h b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar0.h new file mode 100644 index 0000000..48e8516 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar0.h @@ -0,0 +1,13 @@ +#ifndef _RMAR0_H_ +#define _RMAR0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_0.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_0.o new file mode 100644 index 0000000..3663b36 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_0.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_1.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_1.o new file mode 100644 index 0000000..0119f49 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_llvm_0_1.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_nd.o b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_nd.o new file mode 100644 index 0000000..99927ba Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/csrc/rmar_nd.o differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/csrc/vcspieces.incr b/uart_thermometer_digital/sim/therm_chip_top/csrc/vcspieces.incr new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/filelist_vlg.f b/uart_thermometer_digital/sim/therm_chip_top/filelist_vlg.f new file mode 100644 index 0000000..f26981d --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/filelist_vlg.f @@ -0,0 +1,10 @@ +../../rtl/systemregfile/my_systemregfile.v +../../rtl/systemregfile/sirv_gnrl_dffs.v +../../rtl/digital_top.v +../../rtl/uart/uart_byte_rx.v +../../rtl/uart/uart_ctrl_sysreg.v +../../rtl/uart/uart_top_32bit.v +../../rtl/uart/uart_byte_tx.v +../../rtl/therm/digital_thermometer.v +../../rtl/therm/pulse_cnt.v +./TB.sv diff --git a/uart_thermometer_digital/sim/therm_chip_top/novas.conf b/uart_thermometer_digital/sim/therm_chip_top/novas.conf new file mode 100644 index 0000000..2de62cd --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/novas.conf @@ -0,0 +1,377 @@ +[QwMainWindow] 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+Verdi_1\qBaseWindowNextStateGroup\6\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\size=@Size(1440 723) +Verdi_1\qBaseWindowNextStateGroup\6\geometry_x=239 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_y=111 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_width=1440 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_height=723 + +[qBaseWindow_saveRestoreSession_group] +10=/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=239 +Verdi_1\position.y=111 +Verdi_1\width=1440 +Verdi_1\height=723 diff --git a/uart_thermometer_digital/sim/therm_chip_top/novas.rc b/uart_thermometer_digital/sim/therm_chip_top/novas.rc new file mode 100644 index 0000000..c823fbd --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/novas.rc @@ -0,0 +1,1312 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +184615126 = disabled +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwWarnMsgDlg = 650,444,600,250 +QwUserAskDlg = 798,524,324,134 +SetWindowTimeUnitDialog = 742,466,433,86 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/verdiLog/novas_autosave.ses +2 = /home/shbyang/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VCS +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = 239 111 1440 723 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 1440 265 143 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/shbyang/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = shbyang +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1440 265 143 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/uart_thermometer_digital/sim/therm_chip_top/novas_dump.log b/uart_thermometer_digital/sim/therm_chip_top/novas_dump.log new file mode 100644 index 0000000..52ba875 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/novas_dump.log @@ -0,0 +1,348 @@ +####################################################################################### +# log primitive debug message of FSDB dumping # +# This is for R&D to analyze when there are issues happening when FSDB dump # +####################################################################################### +ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status') +ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback') +ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback') +ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name') +ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info') +ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info') +ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback') +ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info') +ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle') +ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle') +ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle') +ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent') +ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope') +ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled') +ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted') +ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue') +ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue') +ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue') +ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb') +ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb') +ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode') +ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info') +ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init') +ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk') +ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores') +ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode') +ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion') +ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp') +ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady') +ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback') +ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle') +ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst') +ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle') +ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig') +ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo') +ANF: msvRelease('./simv: undefined symbol: msvRelease') +ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc') +ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback') +ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback') +ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback') +ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue') +ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback') +ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe') +ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo') +ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo') +ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit') +ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync') +ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile') +ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback') +ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback') +ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback') +ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback') +ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus') +ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type') +ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key') +ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info') +ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info') +ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info') +ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info') +ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module') +ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope') +ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable') +ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi') +ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id') +ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi') +ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free') +ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope') +ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable') +ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi') +ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone') +ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free') +ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key') +ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare') +ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr') +ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback') +ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback') +ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force') +ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback') +ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback') +ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback') +ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data') +ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback') +ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr') +ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr') +ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted') +ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi') +ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id') +ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type') +ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback') +ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name') +ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt') +ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option') +ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode') +ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var') +ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis') +ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id') +ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback') +ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback') +ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr') +VCS compile option: + option[0]: ./simv + option[1]: sync:busywait + option[2]: -l + option[3]: /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 + option[4]: -Mcc=gcc + option[5]: -Mcplusplus=g++ + option[6]: -Masflags= + option[7]: -Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + option[8]: -Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + option[9]: -Mldflags= -rdynamic + option[10]: -Mout=simv + option[11]: -Mamsrun= + option[12]: -Mvcsaceobjs= + option[13]: -Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so + option[14]: -Mexternalobj= + option[15]: -Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + option[16]: -Mcrt0= + option[17]: -Mcrtn= + option[18]: -Mcsrc= + option[19]: -Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl + option[20]: -l + option[21]: compile.log + option[22]: -full64 + option[23]: -j8 + option[24]: +lint=TFIPC-L + option[25]: +v2k + option[26]: -debug_access+pp + option[27]: +vpi + option[28]: +vcsd1 + option[29]: +itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab + option[30]: -lca + option[31]: -q + option[32]: -timescale=1ns/1ps + option[33]: +nospecify + option[34]: -cm + option[35]: line+cond+fsm+tgl+branch + option[36]: -cm_dir + option[37]: ./coverage/simv.vdb + option[38]: -picarchive + option[39]: -P + option[40]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab + option[41]: -fsdb + option[42]: -sverilog + option[43]: -gen_obj + option[44]: -f + option[45]: filelist_vlg.f + option[46]: -load + option[47]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd + option[48]: timescale=1ns/1ps +Chronologic Simulation VCS Release O-2018.09-SP2_Full64 +Linux 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64 +CPU cores: 96 +Limit information: +====================================== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8192 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +====================================== +(Special)Runtime environment variables: + +Runtime environment variables: +INNOVUS_HOME=/opt/cadence/INNOVUS181 +VNCDESKTOP=cryo1:17 (shbyang) +MGC_PDF_REDER=evince +XDG_SESSION_ID=c5 +SSH_AGENT_PID=6119 +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +HOSTNAME=cryo1 +IMSETTINGS_INTEGRATE_DESKTOP=yes +CDSROOT=/opt/cadence/IC618 +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +HOST=cryo1 +TERM=xterm-256color +XDG_MENU_PREFIX=gnome- +VTE_VERSION=5204 +SHELL=/bin/csh +MAKEFLAGS= +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/c54e5016_f7fb_4a73_ae57_77787103df43 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +CDS_LOAD_ENV=CWD +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +QTDIR=/usr/lib64/qt-3.3 +QTINC=/usr/lib64/qt-3.3/include +MENTOR_HOME=/opt/mentor +IMSETTINGS_MODULE=none +QT_GRAPHICSSYSTEM_CHECKED=1 +GROUP=cryo +USER=shbyang +LD_LIBRARY_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/shared/pkgs/icv/tools/calibre_client/lib/64 +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +GNOME_TERMINAL_SERVICE=:1.2258 +W3264_NO_HOST_CHECK=1 +CDS=/opt/cadence/IC618 +HOSTTYPE=x86_64-linux +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +MAKELEVEL=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/5094,unix/unix:/tmp/.ICE-unix/5094 +SNPSLMD_LICENSE_FILE=27050@192.168.1.77 +MFLAGS= +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +GNOME_SHELL_SESSION_MODE=classic +GENUS_HOME=/opt/cadence/GENUS152 +MAIL=/var/spool/mail/shbyang +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +PATH=/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/ +SPECTRE_DEFAULTS=-E +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +QT_IM_MODULE=ibus +_=./simv +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +CDS_SPECTRERF_FBENABLE=1 +CADENCE_DIR=/opt/cadence/IC618 +PWD=/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top +CDSDIR=/opt/cadence/IC618 +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +XMODIFIERS=@im=ibus +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +LANG=C +VRST_HOME=/opt/cadence/INCISIVE152 +CDSHOME=/opt/cadence/IC618 +CDS_Netlisting_Mode=Analog +SYNOPSYS=/opt/synopsys +AMS_ENABLE_NOISE=YES +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +DBUS_STARTER_BUS_TYPE=session +SHLVL=5 +HOME=/home/shbyang +OSTYPE=linux +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +CDS_AUTO_64BIT=ALL +CADHOME=/opt/cadence +VENDOR=unknown +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +LOGNAME=shbyang +MACHTYPE=x86_64 +QTLIB=/usr/lib64/qt-3.3/lib +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67 +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +CDS_LIC_FILE=/opt/cadence/license/license.dat +MOZILLA_HOME=/usr/bin/firefox +LESSOPEN=||/usr/bin/lesspipe.sh %s +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +SCL_HOME=/opt/synopsys/scl/2018.06 +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +CDS_ENABLE_VMS=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +DISPLAY=unix:17 +XDG_RUNTIME_DIR=/run/user/1019 +CDS_LIC_ONLY=1 +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +CDS_ROOT=/opt/cadence/IC618 +XILINX_HOME=/opt/xilinx +INCISIVE_HOME=/opt/cadence/INCISIVE152 +XDG_CURRENT_DESKTOP=GNOME +CDS_SPECTRE_FBENABLE=1 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +CDS_INST_DIR=/opt/cadence/IC618 +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +COLORTERM=truecolor +VCS_HEAP_EXEC=true +VCS_PATHMAP_PRELOAD_DONE=1 +VCS_STACK_EXEC=true +VCS_EXEC_DONE=1 +LC_ALL=C +DVE=/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve +SPECMAN_OUTPUT_TO_TTY=1 +Runtime command line arguments: +argv[0]=./simv +argv[1]=sync:busywait +argv[2]=-l +291 profile - 100 + CPU/Mem usage: 0.050 sys, 0.210 user, 284.52M mem +292 Tue Apr 7 11:12:33 2026 +293 pliAppInit +294 FSDB_GATE is set. +295 FSDB_RTL is set. +296 Enable Parallel Dumping. +297 pliAppMiscSet: New Sim Round +298 pliEntryInit +299 LIBSSCORE=found /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting. +300 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +301 (C) 1996 - 2019 by Synopsys, Inc. +302 sps_call_fsdbDumpfile_main at 0 : ./TB.sv(22) +303 argv[0]: (wave.fsdb) +304 *Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. +305 *Verdi* : Create FSDB file 'wave.fsdb' +306 compile option from '/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/vcs_rebuild'. +307 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1" +308 FSDB_VCS_ENABLE_FAST_VC is enable +309 sps_call_fsdbDumpvars_vd_main at 0 : ./TB.sv(23) +310 [spi_vcs_vd_ppi_create_root]: no upf option +311 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. +312 *Verdi* : Begin traversing the scopes, layer (0). +313 *Verdi* : End of traversing. +314 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.090 sys, 0.220 user, 380.92M mem + incr: 0.010 sys, 0.000 user, 8.86M mem + accu: 0.010 sys, 0.000 user, 8.86M mem + accu incr: 0.010 sys, 0.000 user, 8.86M mem + + Count usage: 223 var, 122 idcode, 85 callback + incr: 223 var, 122 idcode, 85 callback + accu: 223 var, 122 idcode, 85 callback + accu incr: 223 var, 122 idcode, 85 callback +315 Tue Apr 7 11:12:33 2026 +316 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.090 sys, 0.220 user, 381.97M mem + incr: 0.000 sys, 0.000 user, 1.05M mem + accu: 0.010 sys, 0.000 user, 9.92M mem + accu incr: 0.000 sys, 0.000 user, 1.05M mem + + Count usage: 223 var, 122 idcode, 85 callback + incr: 0 var, 0 idcode, 0 callback + accu: 223 var, 122 idcode, 85 callback + accu incr: 0 var, 0 idcode, 0 callback +317 Tue Apr 7 11:12:33 2026 +318 End of simulation at 67816396000 +319 Tue Apr 7 11:12:36 2026 +320 Begin FSDB profile info: +321 FSDB Writer : bc1(6944429) bcn(4210234) mtf/stf(0/2) +FSDB Writer elapsed time : flush(0.508682) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) +FSDB Writer cpu time : MT Compression : 0 +322 End FSDB profile info +323 Parallel profile - Flush:3 Expand:0 ProduceWait:0 ConsumerWait:116 BlockUsed:122 +324 ProduceTime:2.819906888 ConsumerTime:1.842929702 Buffer:64MB +325 SimExit +326 Sim process exit diff --git a/uart_thermometer_digital/sim/therm_chip_top/rx_data.txt b/uart_thermometer_digital/sim/therm_chip_top/rx_data.txt new file mode 100644 index 0000000..8af1d8f --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/rx_data.txt @@ -0,0 +1,24 @@ +20260406 +000003e8 +025800a0 +0000c350 +00fff060 +00fff4d0 +aafff4d0 +aa0000c8 +aa0000fc +aa00012d +aa00012c +aa00012c +aa00012c +aa00012c +aa00012c +aa00012c +aa00012c +aa00012d +aa00012c +aa00012c +aa00012c +aa00012c +aa00012c +0000012c diff --git a/uart_thermometer_digital/sim/therm_chip_top/sim.log b/uart_thermometer_digital/sim/therm_chip_top/sim.log new file mode 100644 index 0000000..5015ba5 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/sim.log @@ -0,0 +1,51 @@ +Chronologic VCS simulator copyright 1991-2018 +Contains Synopsys proprietary information. +Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Apr 7 11:12 2026 +*Verdi* Loading libsscore_vcs201809.so +FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +(C) 1996 - 2019 by Synopsys, Inc. +*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. +*Verdi* : Create FSDB file 'wave.fsdb' +*Verdi* : Begin traversing the scopes, layer (0). +*Verdi* : End of traversing. +------- Step 1: read Thermometer Regs ------- +[1035750000] Packet (32-bit): 0x20260406 +[1730150000] Packet (32-bit): 0x000003e8 +[2424550000] Packet (32-bit): 0x025800a0 +[3118950000] Packet (32-bit): 0x0000c350 +------- Step 2: Running Concurrent Tasks ------- +[3474400000] Start generating signal: 200 kHz +[3813350000] Packet (32-bit): 0x00fff060 +[10168800000] == Sending Read Request == +[10507750000] Packet (32-bit): 0x00fff4d0 +[11210400000] == open report_en== +[12252000000] == mode = 1 == +[12590950000] Packet (32-bit): 0xaafff4d0 +[13343850000] Packet (32-bit): 0xaa0000c8 +[13474400000] Start generating signal: 300 kHz +[14343870000] Packet (32-bit): 0xaa0000fc +[15343890000] Packet (32-bit): 0xaa00012d +[16343910000] Packet (32-bit): 0xaa00012c +[17343930000] Packet (32-bit): 0xaa00012c +[18343950000] Packet (32-bit): 0xaa00012c +[19343970000] Packet (32-bit): 0xaa00012c +[20343990000] Packet (32-bit): 0xaa00012c +[21344010000] Packet (32-bit): 0xaa00012c +[22344030000] Packet (32-bit): 0xaa00012c +[23344050000] Packet (32-bit): 0xaa00012d +[24344070000] Packet (32-bit): 0xaa00012c +[25344090000] Packet (32-bit): 0xaa00012c +[26344110000] Packet (32-bit): 0xaa00012c +[27344130000] Packet (32-bit): 0xaa00012c +[28293600000] == cloese report_en== +[28632550000] Packet (32-bit): 0xaa00012c +[29356950000] Packet (32-bit): 0x0000012c +[33476396000] Start generating signal: 400 kHz +Test Done. +$finish called from file "./TB.sv", line 227. +[RX] File closed at 67816396000 +$finish at simulation time 67816396000 + V C S S i m u l a t i o n R e p o r t +Time: 67816396000 ps +CPU Time: 4.650 seconds; Data structure size: 0.0Mb +Tue Apr 7 11:12:36 2026 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv b/uart_thermometer_digital/sim/therm_chip_top/simv new file mode 100644 index 0000000..7b4d4e6 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/.daidir_complete b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/.daidir_complete new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/.normal_done b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/.normal_done new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/.vcs.timestamp b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/.vcs.timestamp new file mode 100644 index 0000000..4c55e09 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/.vcs.timestamp @@ -0,0 +1,172 @@ +0 +41 ++itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab ++lint=TFIPC-L ++nospecify ++v2k ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so +-Mout=simv +-Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-P +-cm +-cm_dir +-debug_access+pp +-f filelist_vlg.f +-fsdb +-full64 +-gen_obj +-l +-lca +-picarchive +-q +-sverilog +-timescale=1ns/1ps +./coverage/simv.vdb +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +compile.log +line+cond+fsm+tgl+branch +105 +sysc_uni_pwd=/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +XMODIFIERS=@im=ibus +XILINX_HOME=/opt/xilinx +XDG_SESSION_ID=c5 +XDG_RUNTIME_DIR=/run/user/1019 +XDG_MENU_PREFIX=gnome- +XDG_CURRENT_DESKTOP=GNOME +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +W3264_NO_HOST_CHECK=1 +VTE_VERSION=5204 +VRST_HOME=/opt/cadence/INCISIVE152 +VNCDESKTOP=cryo1:17 (shbyang) +VMR_MODE_FLAG=64 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +VENDOR=unknown +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +VCS_MX_HOME_INTERNAL=1 +VCS_MODE_FLAG=64 +VCS_LOG_FILE=compile.log +VCS_LCAMSG_PRINT_OFF=1 +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH=linux64 +UNAME=/bin/uname +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +TOOL_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64 +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +SYNOPSYS=/opt/synopsys +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +SSH_AGENT_PID=6119 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +SPECTRE_DEFAULTS=-E +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/5094,unix/unix:/tmp/.ICE-unix/5094 +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/opt/synopsys/scl/2018.06 +QT_IM_MODULE=ibus +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib64/qt-3.3/lib +QTINC=/usr/lib64/qt-3.3/include +QTDIR=/usr/lib64/qt-3.3 +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +OSTYPE=linux +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +MOZILLA_HOME=/usr/bin/firefox +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +MGC_PDF_REDER=evince +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +MFLAGS= +MENTOR_HOME=/opt/mentor +MAKELEVEL=1 +MAKEFLAGS= +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +INNOVUS_HOME=/opt/cadence/INNOVUS181 +INCISIVE_HOME=/opt/cadence/INCISIVE152 +IMSETTINGS_MODULE=none +IMSETTINGS_INTEGRATE_DESKTOP=yes +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +HOSTTYPE=x86_64-linux +GROUP=cryo +GNOME_TERMINAL_SERVICE=:1.2258 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/c54e5016_f7fb_4a73_ae57_77787103df43 +GNOME_SHELL_SESSION_MODE=classic +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +GENUS_HOME=/opt/cadence/GENUS152 +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +DBUS_STARTER_BUS_TYPE=session +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67 +COLORTERM=truecolor +CDS_SPECTRE_FBENABLE=1 +CDS_SPECTRERF_FBENABLE=1 +CDS_ROOT=/opt/cadence/IC618 +CDS_Netlisting_Mode=Analog +CDS_LOAD_ENV=CWD +CDS_LIC_ONLY=1 +CDS_LIC_FILE=/opt/cadence/license/license.dat +CDS_INST_DIR=/opt/cadence/IC618 +CDS_ENABLE_VMS=1 +CDS_AUTO_64BIT=ALL +CDSROOT=/opt/cadence/IC618 +CDSHOME=/opt/cadence/IC618 +CDSDIR=/opt/cadence/IC618 +CDS=/opt/cadence/IC618 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +CADHOME=/opt/cadence +CADENCE_DIR=/opt/cadence/IC618 +AMS_ENABLE_NOISE=YES +0 +14 +1775531547 ./TB.sv +1775526351 ../../rtl/therm/pulse_cnt.v +1775526160 ../../rtl/therm/digital_thermometer.v +1774925224 ../../rtl/uart/uart_byte_tx.v +1775526524 ../../rtl/uart/uart_top_32bit.v +1775526452 ../../rtl/uart/uart_ctrl_sysreg.v +1774924538 ../../rtl/uart/uart_byte_rx.v +1775525487 ../../rtl/digital_top.v +1774930574 ../../rtl/systemregfile/sirv_gnrl_dffs.v +1775525827 ../../rtl/systemregfile/my_systemregfile.v +1551421444 /opt/synopsys/vcs-mx/O-2018.09-SP2/include/cm_vcsd.tab +1775464043 filelist_vlg.f +1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1551421246 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab +4 +1551422344 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so +1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so +1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so +1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so +1775531552 simv.daidir +-1 partitionlib diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_57246_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_57246_archive_1.so new file mode 100644 index 0000000..4e920fc Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_57246_archive_1.so differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_57264_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_57264_archive_1.so new file mode 100644 index 0000000..5804621 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_57264_archive_1.so differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_csrc0.so b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_csrc0.so new file mode 100644 index 0000000..1c6a113 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_csrc0.so differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_prev_archive_1.so b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_prev_archive_1.so new file mode 100644 index 0000000..d506e23 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/_prev_archive_1.so differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/binmap.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/binmap.sdb new file mode 100644 index 0000000..9a020c4 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/binmap.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/build_db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/build_db new file mode 100644 index 0000000..dc9dc87 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/build_db @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' -static_dbgen_only -daidir=$1 2>&1 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_bcode.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_bcode.db new file mode 100644 index 0000000..45ea720 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_bcode.db @@ -0,0 +1,12 @@ +sid TB +bcid 0 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 1 1 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU WIDTH,30 CALL_ARG_VAL,3,0 OPT_CONST,433 WIDTH,1 M_EQU AND RET +bcid 2 2 WIDTH,30 CALL_ARG_VAL,2,0 OPT_CONST,216 WIDTH,1 M_EQU WIDTH,4 CALL_ARG_VAL,3,0 OPT_CONST,9 WIDTH,1 M_EQU AND RET +bcid 3 3 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 4 4 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 5 5 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 6 6 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 7 7 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 8 8 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 9 9 WIDTH,24 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,1000 MULTIPLY WIDTH,24 CALL_ARG_VAL,3,0 WIDTH,32 PAD DIVIDE OPT_CONST,0 WIDTH,24 SLICE,1 RET +bcid 10 10 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cgname.json b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cgname.json new file mode 100644 index 0000000..c5ebe0f --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/cgname.json @@ -0,0 +1,50 @@ +{ + "TB": [ + "TB", + "sH4Fc", + "module", + 7 + ], + "sirv_gnrl_dfflrs": [ + "sirv_gnrl_dfflrs", + "ZJgwY", + "module", + 2 + ], + "std": [ + "std", + "reYIK", + "module", + 1 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 6 + ], + "sirv_gnrl_dfflrd": [ + "sirv_gnrl_dfflrd", + "Uye5v", + "module", + 3 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 8 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 4 + ], + "sirv_gnrl_dffrs": [ + "sirv_gnrl_dffrs", + "QHiet", + "module", + 5 + ] +} \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/covg_defs b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/.version b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..ff98673 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-SP2_Full64 +Build Date = Feb 28 2019 22:34:30 +RedHat +Compile Location: /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000..7fcf662 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb new file mode 100644 index 0000000..3003437 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dumpcheck.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dumpcheck.db new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz new file mode 100644 index 0000000..a1ab81d Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db new file mode 100644 index 0000000..a92e999 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db @@ -0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_DBCEI2.xml.gz" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100644 index 0000000..46692b0 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../../../.. +fi + +if [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_DBCEI2.xml.gz b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_DBCEI2.xml.gz new file mode 100644 index 0000000..c30e794 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_DBCEI2.xml.gz differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz new file mode 100644 index 0000000..12cf6c1 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/src_files_verilog b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/src_files_verilog new file mode 100644 index 0000000..0306e76 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/src_files_verilog @@ -0,0 +1,10 @@ +/home/shbyang/Desktop/workplace/therm_design/rtl/digital_top.v +/home/shbyang/Desktop/workplace/therm_design/rtl/systemregfile/my_systemregfile.v +/home/shbyang/Desktop/workplace/therm_design/rtl/systemregfile/sirv_gnrl_dffs.v +/home/shbyang/Desktop/workplace/therm_design/rtl/therm/digital_thermometer.v +/home/shbyang/Desktop/workplace/therm_design/rtl/therm/pulse_cnt.v +/home/shbyang/Desktop/workplace/therm_design/rtl/uart/uart_byte_rx.v +/home/shbyang/Desktop/workplace/therm_design/rtl/uart/uart_byte_tx.v +/home/shbyang/Desktop/workplace/therm_design/rtl/uart/uart_ctrl_sysreg.v +/home/shbyang/Desktop/workplace/therm_design/rtl/uart/uart_top_32bit.v +/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/TB.sv diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/topmodules b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/topmodules new file mode 100644 index 0000000..9e9b8b8 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/topmodules @@ -0,0 +1 @@ +kb| \ No newline at end of file diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb new file mode 100644 index 0000000..588fa3b Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/eblklvl.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/eblklvl.db new file mode 100644 index 0000000..4ac5fc6 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/eblklvl.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/elabmoddb.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/elabmoddb.sdb new file mode 100644 index 0000000..035c85d Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/elabmoddb.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/external_functions b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/external_functions new file mode 100644 index 0000000..b76773b --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/external_functions @@ -0,0 +1,78 @@ +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbLog novas_call_fsdbLog - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_update_label novas_call_sps_update_label - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_relation novas_call_sps_add_relation - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_init novas_call_paa_init - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_sync novas_call_paa_sync - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_interactive novas_call_sps_interactive - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_test novas_call_sps_test - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $ridbDump novas_call_ridbDump - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_flush_file novas_call_sps_flush_file - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDisplay novas_call_fsdbDisplay - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMem novas_call_fsdbDumpMem - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpIO novas_call_fsdbDumpIO - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC +pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC +pli $dumpportson DumpPortsOnCALL - DumpPortsMISC +pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC +pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC +pli $simlearn simLearnCall simLearnCheck simLearnMisc +pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC +pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC +pli $countdrivers CountDriversCALL - - +pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb new file mode 100644 index 0000000..460b96a Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_level.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_level.sdb new file mode 100644 index 0000000..e578309 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_level.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb new file mode 100644 index 0000000..5225d9d Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hsscan_cfg.dat b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/hsscan_cfg.dat new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall.sdb new file mode 100644 index 0000000..c004a0c Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131020.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131020.sdb new file mode 100644 index 0000000..2d78748 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131020.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131039.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131039.sdb new file mode 100644 index 0000000..6b34138 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131039.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131040.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131040.sdb new file mode 100644 index 0000000..3c29e5e Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_131040.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_14816.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_14816.sdb new file mode 100644 index 0000000..3342d5b Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_14816.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_30603.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_30603.sdb new file mode 100644 index 0000000..b900361 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_30603.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_34065.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_34065.sdb new file mode 100644 index 0000000..20c5b2f Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_34065.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_37441.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_37441.sdb new file mode 100644 index 0000000..71e51a7 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_37441.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_39120.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_39120.sdb new file mode 100644 index 0000000..ddd4b46 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_39120.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_40348.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_40348.sdb new file mode 100644 index 0000000..ad3f3fb Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_40348.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_41494.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_41494.sdb new file mode 100644 index 0000000..a839ce6 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_41494.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_42320.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_42320.sdb new file mode 100644 index 0000000..3e2afbf Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_42320.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_43443.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_43443.sdb new file mode 100644 index 0000000..3fc8036 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_43443.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_45891.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_45891.sdb new file mode 100644 index 0000000..16feb14 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_45891.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_50120.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_50120.sdb new file mode 100644 index 0000000..70bd021 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_50120.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_52081.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_52081.sdb new file mode 100644 index 0000000..c6bbcfa Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_52081.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_53462.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_53462.sdb new file mode 100644 index 0000000..04dfbde Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_53462.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_54624.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_54624.sdb new file mode 100644 index 0000000..76b2649 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_54624.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_56112.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_56112.sdb new file mode 100644 index 0000000..2f36ec9 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_56112.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_57264.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_57264.sdb new file mode 100644 index 0000000..6d22a5c Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/indcall_57264.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/nsparam.dat b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/nsparam.dat new file mode 100644 index 0000000..1c1eb11 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/nsparam.dat differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/pcc.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/pcc.sdb new file mode 100644 index 0000000..ed622a7 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/pcc.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/pcxpxmr.dat b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/pcxpxmr.dat new file mode 100644 index 0000000..229151a Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/pcxpxmr.dat differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/prof.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/prof.sdb new file mode 100644 index 0000000..8db3553 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/prof.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.dat b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.dat new file mode 100644 index 0000000..ca2fdf8 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.dat differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.so b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.so new file mode 100644 index 0000000..6fd2b2d Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/rmapats.so differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/saifNetInfo.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/saifNetInfo.db new file mode 100644 index 0000000..573541a --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/saifNetInfo.db @@ -0,0 +1 @@ +0 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/stitch_nsparam.dat b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/stitch_nsparam.dat new file mode 100644 index 0000000..0357d47 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/stitch_nsparam.dat differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/tt.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/tt.sdb new file mode 100644 index 0000000..48e6674 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/tt.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131020.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131020.sdb new file mode 100644 index 0000000..4b4da55 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131020.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131039.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131039.sdb new file mode 100644 index 0000000..bcd1f15 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131039.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131040.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131040.sdb new file mode 100644 index 0000000..e7990b7 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_131040.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14790.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14790.sdb new file mode 100644 index 0000000..fa5f575 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14790.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14816.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14816.sdb new file mode 100644 index 0000000..f5fcaa8 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14816.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14817.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14817.sdb new file mode 100644 index 0000000..40bacd2 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_14817.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26119.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26119.sdb new file mode 100644 index 0000000..fab6481 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26119.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26137.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26137.sdb new file mode 100644 index 0000000..fa58ee0 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26137.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26138.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26138.sdb new file mode 100644 index 0000000..09486d2 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_26138.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30584.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30584.sdb new file mode 100644 index 0000000..a7f035e Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30584.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30603.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_30603.sdb new file mode 100644 index 0000000..e061215 Binary files /dev/null and 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b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57264.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57265.sdb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57265.sdb new file mode 100644 index 0000000..1d841bd Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/ttIncr_57265.sdb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcs_rebuild b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcs_rebuild new file mode 100644 index 0000000..0909dc0 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..b58f7c9 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,691 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 13 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimTransUsingdoMpd32 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 +fHsimCongruencyXpropFix 0 +fHsimCongruencyXpropDbsEdge 0 +fHsimCongruencyResetRecoveryDbs 0 +fHsimCongruencyClockControlDiag 0 +fHsimCongruencySampleUpdate 0 +fHsimCongruencyFFDbsFix 0 +fHsimCongruency 0 +fHsimCongruencySlave 0 +fHsimCongruencyCombinedLoads 0 +fHsimCongruencyFGP 0 +fHsimDeraceClockDataUdp 0 +fHsimDeraceClockDataLERUpdate 0 +fHsimCongruencyPC 0 +fHsimCongruencyPCInl 0 +fHsimCongruencyPCDbg 0 +fHsimCongruencyPCNoReuse 0 +fHsimCongruencyDumpHier 0 +fHsimCongruencyResolution 0 +fHsimCongruencyEveBus 0 +fHsimHcExpr 0 +fHsCgOptModOpt 0 +fHsCgOptSlowProp 0 +fHsimCcnOpt 1 +fHsimCcnOpt2 1 +fHsimCcnOpt3 0 +fHsimSmdMap 0 +fHsimSmdDiag 0 +fHsimSmdSimProf 0 +fHsimSgdDiag 0 +fHsimRtDiagLite 0 +fHsimRtDiagLiteCevent 100 +fHsimRtDiag 0 +fHsimSkRtDiag 0 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diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsdef.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsdef.db new file mode 100644 index 0000000..cc66934 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsdef.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_elab.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_elab.db new file mode 100644 index 0000000..998be95 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_elab.db @@ -0,0 +1,1217 @@ +psSimBaseName simv +psLogFileName compile.log +pDaiDir /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir +destPath csrc/ +fSharedMaster 0 +fHsimPCSharedLibSpecified 0 +hsMainFileCount 0 +hsMainFileName dummy +hsAuxFileName dummy +hsimDlpPartitionFilename 0 +partitionName 6 MASTER +hsimInitRegValue 3 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+fHsimSignedOp 0 +fHsimVarIndex 0 +fHsimNewMdbNstate 0 +fHsimProcessNstate 0 +fHsimMdbModpathNstate 0 +fHsimPgateConst 0 +fHsCgOpt 1 +fHsCgOptUdp 1 +fHsCgOptRtl 1 +fHsCgOptDiag 0 +fHsCgOptAggr 0 +fHsCgOptNoZCheck 0 +fHsCgOptEnableZSupport 0 +fHsCgOpt4StateInfra 0 +fHsCgOptDce 0 +fHsCgOptUdpChkDataForWakeup 1 +fHsNBACgOpt 1 +fHsCgOptXprop 0 +fHsimMdbcgDiag 0 +fHsCgMaxInputs 6 +fHsimMemory 0 +fHsCgOptFwdPass 1 +fHsimHpnodes 0 +fLightDump 0 +fRtdbgAccess 0 +fRtdbgOption 0 +fHDLCosim 0 +fHDLCosimDebug 0 +fHDLCosimTimeCoupled 0 +fHDLCosimTimeCoupledPorts 0 +HDLCosimMaxDataPerDpi 1 +HDLCosimMaxCallsPerDpi 2147483647 +fHDLCosimCompileDUT 0 +fHDLCosimCustomCompile 0 +fHDLCosimBoundaryAnalysis 0 +fVpdBeforeScan 1 +fHsCgOptMiSched0 0 +fgcAddSched0 0 +fParamClassOptRtDiag 0 +fHsRegress 0 +fHsBenchmark 0 +fHsimCgScalarVerilogForce 1 +fVcsElabToRoot 1 +fHilIbnObnCallByName 0 +fHsimMdbcgCellPartition 0 +fHsimCompressVpdSig 0 +fHsimLowPowerOpt 0 +fHsimUdpOpt 1 +fHsVecOneld 0 +fNativeVpdDebug 0 +fNewDtviFuse 0 +fHsimVcsGenTLS 1 +fAssertSuccDebugLevelDump 0 +fHsimMinputsChangeCheck 0 +fHsimClkLayout 0 +fHsimIslandLayout 0 +fHsimConfigSched0 0 +fHsimSelectFuseAfterDfuse 0 +vcsNettypeDbgOpt 4 +fHsimFoldedCell 0 +fHsimSimon2Mdb 0 +fHsimSWaveEmul 0 +fHsimSWaveDumpMDB 0 +fHsimSWaveDumpFlatData 0 +fHsimRenumberAlias 0 +fHsimAliasRenumbered 0 +fHilCgMode 115 +fHsimUnionOpt 0 +fHsimFuseSGDBoundaryNodes 0 +fHsimRemoveCapsVec 0 +fHsimSlowNfsRmapats 0 +fHsimCertRaptScal 0 +fHsimCertRaptMdbClock 0 +fHsCgOptMux 0 +fHsCgOptFrc 0 +fHsCgOpt30 0 +fHsLpNoCapsOpt 0 +fHsCgOpt4State 1 +fHashTableSize 12 +fSkipStrChangeOnDelay 1 +fHsimTcheckOpt 0 +fHsCgOptMuxMClk 0 +fHsCgOptMuxFrc 0 +fHsCgOptNoPcb 0 +fHsCgOptMin1 0 +fHsCgOptUdpChk 0 +fHsChkXForSlowSigProp 1 +fHsimVcsParallelDbg 0 +fHsimVcsParallelStrategy 0 +fHsimVcsParallelOpt 0 +fHsimVcsParallelSubLevel 4 +fHsimParallelEblk 0 +fHsimByteCodeParts 1 +fHsimByteCodePartTesting 0 +fHsimByteCodePartAssert 0 +fFgpNovlInComp 0 +fFutEventPRL 0 +fFgpNbaDelay 0 +fHsimDbsFlagsByteArray 0 +fHsimDbsFlagsByteArrayTC 0 +fHsimDbsFlagsThreadArray 0 +fHsimLevelCompaction 0 +fHsimLevelCompactionThreshold 0 +fHsimGateEdgeEventSched 0 +fHsimGateEdgeEventSchedThreshold 0 +fHsimGateEdgeEventSchedSanity 0 +fHsimSelectEdgeEventSched 0 +fHsimSelectEdgeEventSchedNoTempReuse 0 +fHsimSelectEdgeEventSchedThreshold 0 +fHsimMaxComboLevels 0 +fHsimEgschedDynelab 0 +fHsimUdpClkDynelab 0 +fUdpLayoutOnClk 0 +fHsimDiagClk 1 +fDbsPreCheck 0 +fHsimSched0Analysis 0 +fHsimMultiDriverSched0 0 +fHsimLargeIbnSched 0 +fFgpHierarchical 0 +fFgpHierAllElabModAsRoot 0 +fFgpHierPCElabModAsRoot 0 +fFgpAdjustDataLevelOfLatch 1 +fHsimUdpXedgeEval 0 +fFgpRaceCheck 0 +fFgpUnifyClk 0 +fFgpSmallClkTree 0 +fFgpSmallRtlClkTree 4 +fFgpNoRtlUnlink 0 +fFgpNoRtlAuxLevel 0 +fFgpNumPartitions 8 +fFgpMultiSocketCompile 0 +fFgpMultiSocketAfterGrping 0 +fFgpMultiSocketNCuts 1 +fFgpMultiSocketDiag 0 +fFgpMultiSocketRecomputePart 1 +fFgpDataDepOn 0 +fFgpDDIgnore 0 +fFgpXmrDepOn 0 +fFgpTbCbOn 0 +fFgpTbEvOn 1 +fFgpTbNoVSA 0 +fFgpTbEvXmr 0 +fFgpTbEvCgCall 1 +fFgpDisabledLevel 512 +fFgpSched0User 0 +fFgpNoSdDelayedNbas 1 +fFgpTimingFlags 0 +fFgpTcLoadThreshold 0 +fFgpSched0Level 0 +fHsimFgpMultiClock 0 +fFgpScanOptFix 0 +fFgpSched0UdpData 0 +fFgpSanityTest 0 +fFgpSanityTest_Eng 1 +fFgpAlternativeLevelization 0 +fFgpHighFanoutThreshold 1024 +fFgpSplitGroupLevels 1 +fFgpSplitGroupIbn 1 +fFgpSplitGroupGateEdge 1 +fFgpSplitGroupEval 3 +fFgpGroupingPerfDiag 0 +fFgpSplitGroupDiag 0 +fFgpStricDepModDiag 0 +fFgpIPProtect 0 +fFgpIPProtectStrict 0 +fFgpNoVirtualThreads 0 +fFgpLoadBalance0DiagComp 0 +fFgpLoadBalance0CompileTime 1 +fFgpDepositDiag 0 +fFgpEvtDiag.diagOn 0 +fFgpEvtDiag.printAllNodes 0 +fFgpMangleDiagLog 0 +fFgpMultiExclDiag 0 +fFgpSingleExclReason 0 +fHsDoFaninFanoutSanity 0 +fHsFgpNonDbsOva 1 +fFgpParallelTask 1 +fFgpIbnSched 0 +fFgpIbnSchedOpt 0 +fFgpIbnSchedNoLevel 0 +fFgpIbnSchedThreshold 0 +fFgpIbnSchedDyn 0 +fFgpObnSched 0 +fFgpMpStateByte 0 +fFgpTcStateByte 0 +fHsimVirtIntfDynLoadSched 0 +fHsimNetXmrDrvChk 0 +fFgpNoRtimeFgp 0 +fHsFgpGlSched0 0 +fFgpExclReason 0 +fHsimIslandByIslandElab 0 +fHsimIslandByIslandFlat 0 +fHsimIslandByIslandFlat1 0 +fHsimVpdIBIF 0 +fHsimXmrIBIF 0 +fHsimReportTime 0 +fHsimElabJ 0 +fHsimElabJ4SDF 0 +cElabProcs 0 +hf_fHsimElabJ 0 +fHsimElabJOpt 0 +fHsimElabJMMFactor 0 +fHsimOneInstCap 0 +fHsimSchedMinput 0 +fHsimSchedSeqPrim 0 +fHsimSchedRandom 0 +fHsimSchedAll 0 +fHsimSchedSelectFanout 0 +fHsimSchedSelectFanoutDebug 0 +fHsimSchedSelectFanoutRandom 0 +fFgpDynamicReadOn 0 +fHsCgOptAllUc 0 +fHsimNoReconvergenceSched0 0 +fHsimXmrRepl 0 +fZoix 0 +fHsimDfuseNewOpt 0 +fHsimBfuseNewOpt 0 +fFgpMbme 0 +fFgpXmrSched 0 +fHsimClearClkCaps 0 +fFgpHideXmrNodes 0 +fHsimDiagClkConfig 0 +fHsimDiagClkConfigDebug 0 +fHsimDiagClkConfigDumpAll 0 +fHsDiagClkConfigPara 0 +fHsimDiagClkConfigAn 0 +fHsimCanDumpClkConfig 0 +fFgpInitRout 0 +fFgpIgnoreExclSD 0 +fHsimAggrTCOpt 0 +fFgpNewAggrXmrIterFlow 0 +fFgpNoLocalReferer 0 +fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsFgpSchedCgUcLoads 1 +fHsimAdvanceUdpInfer 0 +fFgpIbnSchedIntf 0 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsimCosimGatesProp 0 +fHsSVNettypePerfOpt 0 +fHsCgOptHashFixMap 1 +fHsimLowPowerRetAnalysisInChild 0 +fRetainWithDelayedSig 0 +fHsimChargeDecay 0 +fHsimCongruencyConfigFile 0 +fHsimCongruencyLogFile 0 +fHsimCoverageEnabled 1 +fHsimCoverageOptions 279 +fHsimCoverageDir ./coverage/simv.vdb diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_fegate.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_fegate.db new file mode 100644 index 0000000..3aa373f Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_fegate.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_lvl.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_lvl.db new file mode 100644 index 0000000..0ff36f7 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_lvl.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_name.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_name.db new file mode 100644 index 0000000..fd43680 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_name.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_uds.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_uds.db new file mode 100644 index 0000000..c68634a --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_uds.db @@ -0,0 +1,54 @@ +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 +vcselab_misc_midd.db 1845 +vcselab_misc_mnmn.db 115 +vcselab_misc_hsim_name.db 609 diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_midd.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_midd.db new file mode 100644 index 0000000..34f2943 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_midd.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_mnmn.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_mnmn.db new file mode 100644 index 0000000..76d31fa Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_mnmn.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_partition.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_partition.db new file mode 100644 index 0000000..90d5443 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_partition.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_tCEYNb b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_tCEYNb new file mode 100644 index 0000000..15ddd90 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_tCEYNb differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_vcselabref.db b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_vcselabref.db new file mode 100644 index 0000000..f76dd23 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_vcselabref.db differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_vpdnodenums b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_vpdnodenums new file mode 100644 index 0000000..d81a4dd Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/simv.daidir/vcselab_misc_vpdnodenums differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/ucli.key b/uart_thermometer_digital/sim/therm_chip_top/ucli.key new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/.diagnose.oneSearch b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/.diagnose.oneSearch new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/ToNetlist.log b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/ToNetlist.log new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/compiler.log b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/compiler.log new file mode 100644 index 0000000..703c596 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/compiler.log @@ -0,0 +1,26 @@ +*design* DebussyLib (btIdent Verdi_O-2018.09-SP2) +Command arguments: + +define+verilog + -sverilog + -f filelist_vlg.f + ../../rtl/systemregfile/my_systemregfile.v + ../../rtl/systemregfile/sirv_gnrl_dffs.v + ../../rtl/digital_top.v + ../../rtl/uart/uart_byte_rx.v + ../../rtl/uart/uart_ctrl_sysreg.v + ../../rtl/uart/uart_top_32bit.v + ../../rtl/uart/uart_byte_tx.v + ../../rtl/therm/digital_thermometer.v + ../../rtl/therm/pulse_cnt.v + ./TB.sv + -top + TB + +Highest level modules: +sirv_gnrl_dfflrs +sirv_gnrl_dffl +sirv_gnrl_dffrs +sirv_gnrl_ltch +TB + +Total 0 error(s), 0 warning(s) diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/da_debug.log b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/da_debug.log new file mode 100644 index 0000000..94d3d9c --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/da_debug.log @@ -0,0 +1,5 @@ +##################################################################################################### +# da_debug.log : log primitive debug message of Data Agent (Verdi internal layer to access FSDB). # +# This is for R&D to analyze when there are issues happening when Verdi reading FSDB # +##################################################################################################### +[DA][EVDP][XML]: start update xml in interactive mode at init[DA][EVDP][XML]: start update xml file in interactive mode diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/exe.log b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/exe.log new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas.log b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas.log new file mode 100644 index 0000000..5405db6 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas.log @@ -0,0 +1,11 @@ +Verdi (R) + +Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit) -- Thu Feb 21 04:40:56 PDT 2019 + +Copyright (c) 1999 - 2019 Synopsys, Inc. +This software and the associated documentation are proprietary to Synopsys, Inc. +This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. +All other use, reproduction, or distribution of this software is strictly prohibited. + + +Info: Running in interactive mode. diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas.rc b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas.rc new file mode 100644 index 0000000..be46a57 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas.rc @@ -0,0 +1,1310 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwWarnMsgDlg = 650,407,600,250 +QwUserAskDlg = 798,487,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/verdiLog/novas_autosave.ses +2 = /home/shbyang/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VCS +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -10 20 1920 977 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 1920 392 100 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/shbyang/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = shbyang +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1920 392 100 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses new file mode 100644 index 0000000..a794edf --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses @@ -0,0 +1,85 @@ +@verdi rc file Version 1.0 +[General] +saveDB = TRUE +relativePath = FALSE +saveSingleView = FALSE +saveNWaveWinId = +VerdiVersion = Verdi_O-2018.09-SP2 +[KeyNote] +Line1 = Automatic Backup 0 +Line2 = Save Open Database Information: Yes +Line3 = Path Option: Absolute Paths +Line4 = Windows Option: All Windows +[TestBench] +ConstrViewShow = 0 +InherViewShow = 0 +FSDBMsgShow = 0 +AnnotationShow = 0 +Console = FALSE +powerDumped = 0 +[hb] +postSimFile = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb +syncTime = 21.00083 +viewport = 239 111 1440 723 0 0 366 1918 +activeNode = "TB.u_digital_top" +activeScope = "TB.u_digital_top" +activeFile = "../../rtl/digital_top.v" +interactiveMode = False +viewType = Source +simulatorMode = False +sourceBeginLine = 62 +baMode = False +srcLineNum = True +AutoWrap = True +IdentifyFalseLogic = False +syncSignal = False +traceMode = Hierarchical +showTraceInSchema = True +paMode = False +funcMode = False +powerAwareAnnot = True +amsAnnot = True +traceCrossHier = True +DnDtraceCrossHierOnly = True +traceIncTopPort = False +leadingZero = False +signalPane = False +Scope1 = "TB.u_digital_top" +Scope2 = "TB.u_digital_top.u_uart_ctrl" +Scope3 = "TB.u_digital_top.u_digital_thermometer" +Scope4 = "TB.u_digital_top.u_digital_thermometer.pulse_cnt_inst" +multipleSelection = 1 68 5 0 0 +sdfCheckUndef = FALSE +simFlow = FALSE +[hb.design] +importCmd = "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +invokeDir = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top +[hb.sourceTab.1] +scope = TB.u_digital_top +File = /home/shbyang/Desktop/workplace/therm_design/rtl/digital_top.v +Line = 63 +[nMemoryManager] +WaveformFile = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb +UserActionNum = 0 +nMemWindowNum = 0 +[wave.0] +viewPort = 0 27 1440 265 143 65 +primaryWindow = TRUE +SessionFile = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/verdiLog/novas_autosave.ses.wave.0 +displayGrid = FALSE +hierarchicalName = FALSE +snap = TRUE +displayLeadingZeros = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +highlightGlitchs = FALSE +waveformSyncCursorMarker = FALSE +waveformSyncHorizontalRange = FALSE +waveformSyncVerticalscroll = FALSE +displayErrors = TRUE +displayMsgSymbols = TRUE +showMsgDescriptions = TRUE +autoFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.config b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.config new file mode 100644 index 0000000..d4ab78c --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.config @@ -0,0 +1,55 @@ +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_encode_to_relative_window_id_name=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 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+Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\size=@Size(1440 723) +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_x=239 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_y=111 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_width=1440 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_height=723 diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.png b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.png new file mode 100644 index 0000000..dc24017 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.png differ diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.wave.0 b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.wave.0 new file mode 100644 index 0000000..dd82ae1 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/novas_autosave.ses.wave.0 @@ -0,0 +1,60 @@ +Magic 271485 +Revision Verdi_O-2018.09-SP2 + +; Window Layout +viewPort 0 27 1440 265 143 65 + +; File list: +; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name +openDirFile -d / "" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb" + +; file time scale: +; fileTimeScale ### s|ms|us|ns|ps + +; signal spacing: +signalSpacing 5 + +; windowTimeUnit is used for zoom, cursor & marker +windowTimeUnit 1ms + +; waveform viewport range +zoom 0.000000 61.338412 1m +cursor 21.000830 +marker 0.000000 + +; user define markers +; userMarker time_pos marker_name color linestyle +; visible top row signal index +top 0 +; marker line index +markerPos 4 + +; event list +; addEvent event_name event_expression +; curEvent event_name + + + +COMPLEX_EVENT_BEGIN + + +COMPLEX_EVENT_END + + + +; toolbar current search type +; curSTATUS search_type +curSTATUS ByChange + + +addGroup "G1" +activeDirFile "" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb" +addSignal -h 15 /TB/sig_in +addSignal -h 15 -2COMP -UDEC /TB/u_digital_top/therm_out[23:0] +addSignal -h 15 -holdScope therm_vld +addSignal -h 15 -holdScope w_rden +addGroup "G2" + +; getSignalForm Scope Hierarchy Status +; active file of getSignalForm + diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/pes.bat b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/pes.bat new file mode 100644 index 0000000..7c6e4ac --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/pes.bat @@ -0,0 +1,3 @@ +where +detach +quit diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/turbo.log b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/turbo.log new file mode 100644 index 0000000..68abd0d --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/turbo.log @@ -0,0 +1,3 @@ +Command Line: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -sverilog -f filelist_vlg.f -top TB -ssf wave.fsdb -nologo +uname(Linux cryo1 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64) +au time 2660.219131 50.598536 32.612097 delta 1173549056 1173549056 total 1598640128 1598640128 diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd new file mode 100644 index 0000000..eaa1999 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd @@ -0,0 +1,504 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +debLoadSimResult \ + /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb +wvCreateWindow +verdiWindowResize -win $_Verdi_1 "239" "111" "1440" "723" +wvSetCursor -win $_nWave2 82958001.552000 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sig_in" -line 16 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 3413226200.320256 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 922493567.654123 -snap {("G2" 0)} +wvSetCursor -win $_nWave2 3394776328.967174 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 3320976843.554844 -snap {("G1" 1)} +wvSetWindowTimeUnit -win $_nWave2 1.000000 ms +wvSetCursor -win $_nWave2 1.273041 -snap {("G2" 0)} +wvSetCursor -win $_nWave2 0.313648 -snap {("G2" 0)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvSetCursor -win $_nWave2 2.638332 -snap {("G2" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "uart_rx" -line 14 -pos 1 -win $_nTrace1 +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top" -delim "." +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcHBSelect "TB.u_digital_top.u_uart_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top.u_uart_ctrl" -delim "." +srcHBSelect "TB.u_digital_top.u_uart_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "o_addr" -line 14 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "o_rden" -line 16 -pos 1 -win $_nTrace1 +srcSelect -signal "i_rddata" -line 17 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 6.162257 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 8.948187 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 6.106907 -snap {("G1" 3)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 5.772435 7.069406 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 1.432410 -snap {("G1" 3)} +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top" -delim "." +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 59 -pos 1 -win $_nTrace1 +srcSelect -signal "therm_vld" -line 60 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 59 -pos 1 -win $_nTrace1 +srcSelect -signal "therm_vld" -line 60 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 5.499407 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 5.067429 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 5.183731 -snap {("G1" 2)} +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 4.984357 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 5.947999 -snap {("G1" 4)} +srcHBSelect "TB.u_digital_top.u_digital_thermometer.pulse_cnt_inst" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.u_digital_top.u_digital_thermometer.pulse_cnt_inst" -delim "." +srcHBSelect "TB.u_digital_top.u_digital_thermometer.pulse_cnt_inst" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_out" -line 10 -pos 1 -win $_nTrace1 +srcSelect -signal "vld_out" -line 11 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 5.150502 -snap {("G1" 2)} +wvSelectSignal -win $_nWave2 {( "G1" 6 7 )} +wvSetRadix -win $_nWave2 -format UDec +wvSetCursor -win $_nWave2 5.000971 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 5.183731 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 4.951128 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 5.133887 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 5.967303 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 4.770518 -snap {("G1" 5)} +wvSetCursor -win $_nWave2 4.720652 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 5.900815 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 4.903494 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 4.005906 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 5.019848 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 5.884193 -snap {("G1" 7)} +srcHBSelect "TB.u_digital_top.u_digital_thermometer" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top.u_digital_thermometer" -delim "." +srcHBSelect "TB.u_digital_top.u_digital_thermometer" -win $_nTrace1 +wvSetCursor -win $_nWave2 0.182842 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 5.036470 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 6.183389 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 0.482038 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 5.235935 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 0.764613 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 3.390891 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 5.219313 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 3.390891 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 3.956040 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 2.759254 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 3.424135 -snap {("G1" 2)} +wvSetMarker -win $_nWave2 0.692610 +wvSetCursor -win $_nWave2 1.911532 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 3.457379 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 2.925475 -snap {("G1" 2)} +wvSetMarker -win $_nWave2 0.000000 +wvSetCursor -win $_nWave2 3.357647 -snap {("G1" 2)} +wvSetMarker -win $_nWave2 5.164610 +wvSetCursor -win $_nWave2 3.307781 -snap {("G1" 1)} +wvSetMarker -win $_nWave2 3.474400 +wvSetCursor -win $_nWave2 3.174805 -snap {("G1" 1)} +wvSetMarker -win $_nWave2 5.164590 +wvSetCursor -win $_nWave2 0.781235 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 3.523867 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 0.265952 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 6.000547 -snap {("G1" 4)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wd_cnt_vld" -line 53 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "report_en" -line 54 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wd_cnt_vld" -line 53 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wd_cnt_out" -line 72 -pos 1 -win $_nTrace1 +wvSetCursor -win $_nWave2 7.961945 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 6.017169 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 4.953360 -snap {("G1" 7)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 4.482452 5.992583 +wvZoom -win $_nWave2 4.881898 5.040925 +wvZoom -win $_nWave2 4.989366 5.002685 +wvZoom -win $_nWave2 5.000001 5.001238 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetMarker -win $_nWave2 5.000490 +wvZoom -win $_nWave2 4.929207 5.114040 +wvZoom -win $_nWave2 4.999400 5.005684 +wvZoom -win $_nWave2 5.000312 5.000682 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cur_freq_khz" -line 71 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_scaled" -line 70 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cur_freq_khz" -line 71 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wd_cnt_out" -line 72 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_scaled" -line 70 -pos 1 -win $_nTrace1 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSetCursor -win $_nWave2 3.357204 -snap {("G1" 2)} +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 3.276792 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 5.930391 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 4.684004 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 5.910288 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 6.332451 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 5.930391 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 0.924739 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 3.477823 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 3.256689 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 1.065460 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 5.870082 -snap {("G1" 4)} +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvScrollDown -win $_nWave2 2 +wvSelectSignal -win $_nWave2 {( "G1" 8 )} +wvSetCursor -win $_nWave2 5.970597 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 6.332451 -snap {("G1" 7)} +wvSetMarker -win $_nWave2 6.000510 +wvSetCursor -win $_nWave2 5.930391 -snap {("G1" 7)} +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvSetCursor -win $_nWave2 1.507727 -snap {("G1" 9)} +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvSetCursor -win $_nWave2 0.723709 -snap {("G1" 5)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top" -delim "." +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcHBSelect "TB.u_digital_top.u_uart_ctrl" -win $_nTrace1 +srcHBSelect "TB.u_digital_top.u_system_regfile" -win $_nTrace1 +srcHBSelect "TB.u_digital_top.u_uart_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top.u_uart_ctrl" -delim "." +srcHBSelect "TB.u_digital_top.u_uart_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "o_wrdata" -line 13 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "o_wren" -line 15 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "o_addr" -line 14 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "o_wren" -line 15 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "o_rden" -line 16 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_report_data" -line 19 -pos 1 -win $_nTrace1 +srcSelect -signal "i_report_vld" -line 20 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "uart_tx_go" -line 34 -pos 1 -win $_nTrace1 +srcSelect -signal "uart_tx_data" -line 34 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvSetCursor -win $_nWave2 10.031407 -snap {("G1" 12)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 21.956045 -snap {("G1" 12)} +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 10.082976 -snap {("G1" 12)} +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 8.694740 -snap {("G1" 11)} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "uart_rx_data" -line 24 -pos 1 -win $_nTrace1 +srcSelect -signal "uart_rx_done" -line 25 -pos 1 -win $_nTrace1 +srcSelect -signal "uart_tx_data" -line 26 -pos 1 -win $_nTrace1 +srcSelect -signal "uart_tx_go" -line 27 -pos 1 -win $_nTrace1 +srcSelect -signal "uart_tx_done" -line 28 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +wvSelectSignal -win $_nWave2 {( "G1" 12 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "CLOCK_FREQ" -line 31 -pos 2 -win $_nTrace1 +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top" -delim "." +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcSelect -signal "therm_out" -line 78 -pos 2 -win $_nTrace1 +srcSelect -signal "therm_vld" -line 79 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 9 )} +wvScrollUp -win $_nWave2 8 +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvScrollDown -win $_nWave2 9 +wvSelectSignal -win $_nWave2 {( "G1" 2 3 4 5 6 7 8 9 10 11 12 13 14 )} +wvSelectSignal -win $_nWave2 {( "G1" 2 3 4 5 6 7 8 9 10 11 12 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 3)} +wvSetCursor -win $_nWave2 10.411768 -snap {("G2" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 78 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_vld" -line 79 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 78 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "w_rden" -line 69 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 7.160374 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 4.968423 -snap {("G1" 4)} +wvSetMarker -win $_nWave2 0.000000 +wvSetCursor -win $_nWave2 5.370281 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 5.845203 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 10.192573 -snap {("G1" 4)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9.259728 10.959756 +wvZoom -win $_nWave2 9.971597 10.249297 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSetRadix -win $_nWave2 -2Com +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSetRadix -win $_nWave2 -format UDec +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1.808541 9.874632 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 1.471426 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 8.213234 -snap {("G2" 0)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvSetCursor -win $_nWave2 11.824917 -snap {("G1" 3)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 11.074991 13.914732 +wvZoom -win $_nWave2 11.835552 12.155788 +wvZoom -win $_nWave2 11.911761 11.934862 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 33.622537 36.007920 +wvZoom -win $_nWave2 34.971485 35.052580 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 10.507043 18.401524 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 15.579489 17.595659 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 34.826565 37.340925 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 34.133690 36.575868 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 64.518922 68.380970 +wvZoom -win $_nWave2 66.283423 67.212108 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 13.208266 -snap {("G2" 0)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 2.669357 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 12.154093 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 2.044614 -snap {("G1" 4)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvSetCursor -win $_nWave2 12.267682 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 3.521279 -snap {("G1" 3)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvSetCursor -win $_nWave2 0.965512 -snap {("G1" 4)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvZoom -win $_nWave2 11.018196 17.549601 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 11.814313 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 13.027443 -snap {("G1" 3)} +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 20.709861 -snap {("G1" 3)} +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 11.813324 19.480625 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.u_digital_top.u_digital_thermometer" -win $_nTrace1 +debExit diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd.bak b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd.bak new file mode 100644 index 0000000..676ff88 --- /dev/null +++ b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/verdi.cmd.bak @@ -0,0 +1,61 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +debLoadSimResult \ + /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb +wvCreateWindow +verdiWindowResize -win $_Verdi_1 "239" "111" "1440" "723" +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcHBSelect "TB.Unnamed_\$TB_sv_88" -win $_nTrace1 +srcHBSelect "TB.Unnamed_\$TB_sv_88" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.Unnamed_\$TB_sv_88" -delim "." +srcHBSelect "TB.Unnamed_\$TB_sv_88" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcHBSelect "TB.gen_pulses" -win $_nTrace1 +srcHBSelect "TB.send_byte" -win $_nTrace1 +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top" -delim "." +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_85_fre_k" -line 74 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_neg_40_fre_k" -line 75 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_85_fre_k" -line 74 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_neg_40_fre_k" -line 89 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "report_en" -line 90 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_neg_40_fre_k" -line 89 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "out_mode" -line 87 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rep_gap_us" -line 91 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 92 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 92 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 92 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_vld" -line 93 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.u_digital_top.u_digital_thermometer" -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +verdiWindowResize -win $_Verdi_1 "270" "72" "1440" "723" diff --git a/uart_thermometer_digital/sim/therm_chip_top/verdiLog/verdi_perf_err.log b/uart_thermometer_digital/sim/therm_chip_top/verdiLog/verdi_perf_err.log new file mode 100644 index 0000000..e69de29 diff --git a/uart_thermometer_digital/sim/therm_chip_top/wave.fsdb b/uart_thermometer_digital/sim/therm_chip_top/wave.fsdb new file mode 100644 index 0000000..382a534 Binary files /dev/null and b/uart_thermometer_digital/sim/therm_chip_top/wave.fsdb differ diff --git a/tb/TB_top.sv b/uart_thermometer_digital/tb/TB_top.sv similarity index 100% rename from tb/TB_top.sv rename to uart_thermometer_digital/tb/TB_top.sv diff --git a/tb/tb_diginal_top.v b/uart_thermometer_digital/tb/tb_diginal_top.v similarity index 100% rename from tb/tb_diginal_top.v rename to uart_thermometer_digital/tb/tb_diginal_top.v diff --git a/tb/tb_digital_thermometer.sv b/uart_thermometer_digital/tb/tb_digital_thermometer.sv similarity index 100% rename from tb/tb_digital_thermometer.sv rename to uart_thermometer_digital/tb/tb_digital_thermometer.sv diff --git a/tb/tb_pulse_cnt.sv b/uart_thermometer_digital/tb/tb_pulse_cnt.sv similarity index 100% rename from tb/tb_pulse_cnt.sv rename to uart_thermometer_digital/tb/tb_pulse_cnt.sv diff --git a/tb/tb_uart_ctrl_sysreg.v b/uart_thermometer_digital/tb/tb_uart_ctrl_sysreg.v similarity index 100% rename from tb/tb_uart_ctrl_sysreg.v rename to uart_thermometer_digital/tb/tb_uart_ctrl_sysreg.v diff --git a/tb/tb_uart_top_32bit.v b/uart_thermometer_digital/tb/tb_uart_top_32bit.v similarity index 100% rename from tb/tb_uart_top_32bit.v rename to uart_thermometer_digital/tb/tb_uart_top_32bit.v diff --git a/tb/uart_byte_rx_tb.v b/uart_thermometer_digital/tb/uart_byte_rx_tb.v similarity index 100% rename from tb/uart_byte_rx_tb.v rename to uart_thermometer_digital/tb/uart_byte_rx_tb.v diff --git a/tb/uart_byte_tx_tb.v b/uart_thermometer_digital/tb/uart_byte_tx_tb.v similarity index 100% rename from tb/uart_byte_tx_tb.v rename to uart_thermometer_digital/tb/uart_byte_tx_tb.v