串口版本太复杂，新增简单的spi版本—基本仿真无误
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/04/03 22:01:15
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// Design Name:
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// Module Name: digital_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module digital_top(
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input clk,
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input rst_n,
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//spi_slave
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input sclk,
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input [4:0]cfgid,
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input csn,
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input mosi,
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output miso,
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output oen,
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//pulse_counter
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input sig_in
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);
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wire [31:0] wrdata;
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wire [24:0] addr;
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wire wren;
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wire rden;
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wire [31:0]rddata;
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wire [23:0] win_us;
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wire cnt_vld;
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wire [23:0]cnt_out;
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// 实例化 DUT
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spi_sys u_spi_sys (
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.clk (clk ),
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.rst_n (rst_n ),
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.cfgid (cfgid ),
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.sclk (sclk ),
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.csn (csn ),
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.mosi (mosi ),
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.miso (miso ),
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.oen (oen ),
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.wrdata (wrdata ),
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.addr (addr ),
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.wren (wren ),
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.rden (rden ),
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.rddata (rddata )
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);
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system_regfile u_system_regfile (
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.clk (clk),
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.rst_n (rst_n),
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.wrdata (wrdata),
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.wren (wren),
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.rwaddr (addr),
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.rden (rden),
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.rddata (rddata),
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// digital_thermometer
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.win_us(win_us),
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.pulse_cnt_out(cnt_out),
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.pules_cnt_vld(cnt_vld)
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);
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pulse_cnt #(
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.CLK_FREQ(50_000_000)
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) u_pulse_cnt (
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.clk (clk),
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.rst_n (rst_n),
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.sig_in (sig_in),
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.win_us (win_us),
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.cnt_out(cnt_out),
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.vld_out(cnt_vld)
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);
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endmodule
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@ -0,0 +1,292 @@
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : spi_sys.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-04-13 PWY SPI BUS for System
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// 0.2 2024-06-24 PWY {spi_dout[31:0],1'b0} -> {spi_dout[30:0],1'b0}
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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//-----------------------------Spi Frame-------------------------------------------------------------------------------------
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////MSB------------->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>..............................................>>>>>>>>------->LSB
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///|<-----------MSB 32 bits------------------->||<---------Second 32-bit---->||<-------x 32-bit---->||<-------n 32-bit---->|
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// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
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// | 31 || 30:6 || 5:1 || 0 || 31:0 || ...... || 31:0 |
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// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
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// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
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// | wnr || addr[24:0] || CHIPID ||resv || data[31:0] || ...... || data[31:0] |
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// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
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//-----------------------------Spi Frame-------------------------------------------------------------------------------------
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module spi_sys (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//cfg ID
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,input [4 :0] cfgid //ID number for the entire chip
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//spi port
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,input sclk // Spi Clock
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,input csn // Spi Chip Select active low
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,input mosi // Spi Mosi
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,output miso // Spi Miso
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,output oen // Spi Miso output enable
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,output [31:0] wrdata //write data to sram
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,output [24:0] addr //sram address
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,output wren //write enable sram
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,output rden //rden enable sram
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,input [31:0] rddata //read data from sram
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);
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localparam IDLE = 2'b00,
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RECVCMD = 2'b01,
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WRITE = 2'b10,
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READ = 2'b11;
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//-----------------------------------------------------------------------
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//SPI module reset processing
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//-----------------------------------------------------------------------
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//spi_rstn
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//wire spi_rstn;
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//assign spi_rstn = rst_n & (~csn);
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//////////////////////////////////////////////////////////////////////////
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//capture the sck
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//////////////////////////////////////////////////////////////////////////
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wire [2:0] sclk_reg;
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//sync sclk to the main clock using a 3-bits shift register
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sirv_gnrl_dffrs #(3) sclk_reg_dffrs ({sclk_reg[1:0],sclk}, sclk_reg, clk, rst_n);
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//sclk's rising edges
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wire sclk_p = (sclk_reg[2:1] == 2'b01);
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//sclk's falling edges
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//assign sclk_n = (sclk_reg[2:1] == 2'b10);
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//////////////////////////////////////////////////////////////////////////
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//capture the csn
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//////////////////////////////////////////////////////////////////////////
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wire [2:0] csn_reg;
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//sync csn to the main clock using a 2-bits shift register
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sirv_gnrl_dffrs #(3) csn_reg_dffrs ({csn_reg[1:0],csn}, csn_reg, clk, rst_n);
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// csn is active low
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wire csn_active = ~csn_reg[1];
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//csn's rising edges
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wire csn_p = (csn_reg[2:1] == 2'b01);
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//csn's falling edges
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wire csn_n = (csn_reg[2:1] == 2'b10);
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//////////////////////////////////////////////////////////////////////////
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//capture the mosi
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//////////////////////////////////////////////////////////////////////////
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wire [1:0] mosi_reg;
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//sync mosi to the main clock using a 2-bits shift register
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sirv_gnrl_dffr #(2) mosi_reg_dffr ({mosi_reg[0],mosi}, mosi_reg, clk, rst_n);
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//mosi_data
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wire mosi_data = mosi_reg[1];
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//////////////////////////////////////////////////////////////////////////
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//cnt
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//////////////////////////////////////////////////////////////////////////
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wire [4:0] cnt_c;
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//add_cnt
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wire add_cnt = sclk_p && csn_active;
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//end_cnt
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wire end_cnt = (add_cnt && (cnt_c == 5'd31)) | csn_p;
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wire [4:0] cnt_n = end_cnt ? 5'h0 :
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add_cnt ? cnt_c + 5'b1 :
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cnt_c ;
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sirv_gnrl_dffr #(5) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
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///////////////////////////////////////////////////////////////////////
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//SPI data sample
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///////////////////////////////////////////////////////////////////////
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generate
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genvar i;
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wire [31:0] recv_vld ;
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wire [31:0] spi_din ;
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for(i=0;i<32;i=i+1) begin: spi_sys_recv
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assign recv_vld[i] = add_cnt & (cnt_c == i );
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sirv_gnrl_dfflr #(1) spi_din_dfflr (recv_vld[i], mosi_data, spi_din[31-i], clk, rst_n);
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end
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endgenerate
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wire [1:0] state_c;
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wire [1:0] state_n;
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///////////////////////////////////////////////////////////////////////
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//init_addr capture
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///////////////////////////////////////////////////////////////////////
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wire [24:0] initaddr;
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wire initaddr_vld = (state_c == RECVCMD ) & add_cnt && (cnt_c == 5'd26);
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wire [1:0] initaddr_vld_r;
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sirv_gnrl_dffr #(2) initaddr_vld_r_dffr ({initaddr_vld_r[0],initaddr_vld}, initaddr_vld_r, clk, rst_n);
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sirv_gnrl_dfflr #(25) initaddr_dfflr (initaddr_vld_r[0], spi_din[30:6], initaddr, clk, rst_n);
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///////////////////////////////////////////////////////////////////////
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//CMD capture
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///////////////////////////////////////////////////////////////////////
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wire cmd ;
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sirv_gnrl_dfflr #(1) cmd_dfflr ( initaddr_vld_r[0], spi_din[31], cmd, clk, rst_n);
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///////////////////////////////////////////////////////////////////////
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//CHIPID capture
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///////////////////////////////////////////////////////////////////////
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wire [4:0] chipid;
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wire [1:0] chipid_vld_r;
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wire chipid_vld = (state_c == RECVCMD ) & add_cnt & (cnt_c == 5'd30);
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//register cmd_vld to align it with cmd
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sirv_gnrl_dffr #(2) chipid_vld_r_dffr ({chipid_vld_r[0],chipid_vld}, chipid_vld_r, clk, rst_n);
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sirv_gnrl_dfflr #(5) chipid_dfflr (chipid_vld_r[0], spi_din[5:1], chipid, clk, rst_n);
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///////////////////////////////////////////////////////////////////////
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//ID matching determination
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///////////////////////////////////////////////////////////////////////
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wire chipid_match = (chipid == cfgid);
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wire chipid_dismatch = (chipid != cfgid);
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///////////////////////////////////////////////////////////////////////
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//SPI Module State Machine
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///////////////////////////////////////////////////////////////////////
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//Generating jump conditions for state machines
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wire ilde2recvcmd = (state_c == IDLE ) && csn_active && csn_n ;
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wire recvcmd2ilde = (state_c == RECVCMD ) && chipid_dismatch & end_cnt;
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wire recvcmd2write = (state_c == RECVCMD ) && chipid_match && ~cmd & end_cnt;
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wire recvcmd2read = (state_c == RECVCMD ) && chipid_match && cmd & end_cnt;
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wire write2idle = (state_c == WRITE ) && csn_p;
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wire read2idle = (state_c == READ ) && csn_p;
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//The first section of the state machine
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//state_c
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sirv_gnrl_dffr #(2) state_c_dffr (state_n, state_c, clk, rst_n);
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//state_n
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assign state_n = ((state_c == IDLE ) && ilde2recvcmd ) ? RECVCMD :
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((state_c == RECVCMD ) && recvcmd2ilde ) ? IDLE :
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((state_c == RECVCMD ) && recvcmd2write ) ? WRITE :
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((state_c == RECVCMD ) && recvcmd2read ) ? READ :
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((state_c == WRITE ) && write2idle ) ? IDLE :
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((state_c == READ ) && read2idle ) ? IDLE :
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state_c ;
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///////////////////////////////////////////////////////////////////////////////////////////////////////
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//Address generation for read and write operations
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//The address to be used for updating in the next
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//27 clock cycles in the read-write state
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///////////////////////////////////////////////////////////////////////////////////////////////////////
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wire second_falling;
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wire second_falling_w = (state_c == WRITE);
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sirv_gnrl_dfflr #(1) second_falling_dfflr (end_cnt ,second_falling_w, second_falling, clk, rst_n);
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wire addr_update = ((state_c == READ) | ((state_c == WRITE) & second_falling)) & add_cnt & (cnt_c == 5'd27);
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wire [24:0] addr_c;
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wire [24:0] addr_n = ilde2recvcmd ? 25'd0 :
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initaddr_vld_r[1] ? initaddr :
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addr_update ? addr_c + 25'd4 :
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addr_c ;
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sirv_gnrl_dffr #(25) addr_c_dffr (addr_n, addr_c, clk, rst_n);
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assign addr = addr_c;
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///////////////////////////////////////////////////////////////////////////////////////////////////////
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//Write data and write signals generation
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///////////////////////////////////////////////////////////////////////////////////////////////////////
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wire wren_r;
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wire wren_w = (state_c == WRITE) & add_cnt & (cnt_c == 5'd31);
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//wdata
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sirv_gnrl_dfflr #(32) wrdata_dfflr (wren_r, spi_din[31:0], wrdata, clk, rst_n);
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//wren_r
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sirv_gnrl_dffr #(1) wren_r_dffr (wren_w, wren_r, clk, rst_n);
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//wren
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sirv_gnrl_dffr #(1) wren_dffr (wren_r, wren, clk, rst_n);
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///////////////////////////////////////////////////////////////////////////////////////////////////////
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//read signals generation
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///////////////////////////////////////////////////////////////////////////////////////////////////////
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wire rden_w = chipid_match & cmd & add_cnt & (cnt_c == 5'd28);
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sirv_gnrl_dffr #(1) rden_dffr (rden_w, rden, clk, rst_n);
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||||
//Read data register
|
||||
wire rddata_vld = cmd & add_cnt & (cnt_c == 5'd30);
|
||||
wire [31:0] rddata_reg;
|
||||
sirv_gnrl_dfflr #(32) rddata_reg_dfflr (rddata_vld, rddata[31:0], rddata_reg, clk, rst_n);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI send data update
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [31:0] spi_dout ;
|
||||
wire update_flag = cmd & add_cnt & (cnt_c == 5'd31);
|
||||
|
||||
wire [31:0] rddata_sr = update_flag ? rddata_reg[31:0] :
|
||||
((state_c == READ) & add_cnt) ? {spi_dout[30:0],1'b0} : //M 2024-06-24
|
||||
spi_dout ;
|
||||
|
||||
sirv_gnrl_dffr #(32) spi_dout_dffr (rddata_sr, spi_dout, clk, rst_n);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI send data
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
assign miso = spi_dout[31];
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI output enable
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dffrs #(1) oen_dffr (~(state_c == READ), oen, clk, rst_n);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -1,342 +1,342 @@
|
|||
/*
|
||||
Copyright 2018-2020 Nuclei System Technology, Inc.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//=====================================================================
|
||||
//
|
||||
// Designer : Bob Hu
|
||||
//
|
||||
// Description:
|
||||
// All of the general DFF and Latch modules
|
||||
//
|
||||
// ====================================================================
|
||||
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
`define DISABLE_SV_ASSERTION
|
||||
`define dly #0.2
|
||||
module sirv_gnrl_dfflrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is input
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflrd # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
input [DW-1:0] init,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= init;
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable, no reset
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffl # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : DFFL_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module for general latch
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_ltch # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
//input test_mode,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @ *
|
||||
begin : LTCH_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= dnxt;
|
||||
end
|
||||
|
||||
//assign qout = test_mode ? dnxt : qout_r;
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
always_comb
|
||||
begin
|
||||
CHECK_THE_X_VALUE:
|
||||
assert (lden !== 1'bx)
|
||||
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
|
||||
end
|
||||
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// module sirv_gnrl_edffr #(parameter type T = logic) (
|
||||
// input T dnxt,
|
||||
// output T qout,
|
||||
// input clk, rst_n
|
||||
// );
|
||||
|
||||
// T qout_r;
|
||||
|
||||
// always_ff @(posedge clk or negedge rst_n) begin
|
||||
// if (!rst_n) qout_r <= T'('0);
|
||||
// else qout_r <= `dly dnxt;
|
||||
// end
|
||||
// assign qout = qout_r;
|
||||
// endmodule
|
||||
|
||||
/*
|
||||
Copyright 2018-2020 Nuclei System Technology, Inc.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//=====================================================================
|
||||
//
|
||||
// Designer : Bob Hu
|
||||
//
|
||||
// Description:
|
||||
// All of the general DFF and Latch modules
|
||||
//
|
||||
// ====================================================================
|
||||
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
`define DISABLE_SV_ASSERTION
|
||||
`define dly #0.2
|
||||
module sirv_gnrl_dfflrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is input
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflrd # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
input [DW-1:0] init,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= init;
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable, no reset
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffl # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : DFFL_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module for general latch
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_ltch # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
//input test_mode,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @ *
|
||||
begin : LTCH_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= dnxt;
|
||||
end
|
||||
|
||||
//assign qout = test_mode ? dnxt : qout_r;
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
always_comb
|
||||
begin
|
||||
CHECK_THE_X_VALUE:
|
||||
assert (lden !== 1'bx)
|
||||
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
|
||||
end
|
||||
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// module sirv_gnrl_edffr #(parameter type T = logic) (
|
||||
// input T dnxt,
|
||||
// output T qout,
|
||||
// input clk, rst_n
|
||||
// );
|
||||
|
||||
// T qout_r;
|
||||
|
||||
// always_ff @(posedge clk or negedge rst_n) begin
|
||||
// if (!rst_n) qout_r <= T'('0);
|
||||
// else qout_r <= `dly dnxt;
|
||||
// end
|
||||
// assign qout = qout_r;
|
||||
// endmodule
|
||||
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Add a new register:
|
||||
|
||||
// SECTION A: Add localparam ADDR_NEW = 16'hXX;.
|
||||
|
||||
// SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;.
|
||||
|
||||
// SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);.
|
||||
|
||||
// SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);.
|
||||
|
||||
// SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block.
|
||||
|
||||
// SECTION G: Map reg_new to the module's output ports.
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module system_regfile (
|
||||
// [BLOCK 0] System and Bus Interface
|
||||
input clk,
|
||||
input rst_n,
|
||||
input [31:0] wrdata,
|
||||
input wren,
|
||||
input [24:0] rwaddr,
|
||||
input rden,
|
||||
output [31:0] rddata,
|
||||
|
||||
output [23:0]win_us,
|
||||
input [23:0]pulse_cnt_out,
|
||||
input pules_cnt_vld
|
||||
|
||||
);
|
||||
|
||||
// =============================================================================
|
||||
// [SECTION A] Address Offset Definition (Localparams)
|
||||
// =============================================================================
|
||||
localparam TESTR = 16'h00, DATER = 16'h04;
|
||||
localparam WIN_TIME_R =16'h08 ;
|
||||
localparam RESULT_R =16'h0c ;
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// [SECTION B] Internal Wire Declaration (Wires)
|
||||
// =============================================================================
|
||||
|
||||
// Register selection signals (Enable Wires)
|
||||
wire sel_testr, sel_dater;
|
||||
wire sel_win_time, sel_result;
|
||||
|
||||
// Write enable signals (Write Enable Wires)
|
||||
wire we_testr, we_dater;
|
||||
wire we_win_time;
|
||||
|
||||
|
||||
// Register storage wires (Storage Wires)
|
||||
wire [31:0] testr, dater;
|
||||
wire [23:0] win_time_r, result_r;
|
||||
// =============================================================================
|
||||
// [SECTION C] Decoding Logic (Decoding)
|
||||
// =============================================================================
|
||||
assign sel_testr = (rwaddr[15:0] == TESTR );
|
||||
assign sel_dater = (rwaddr[15:0] == DATER );
|
||||
assign sel_win_time = (rwaddr[15:0] == WIN_TIME_R );
|
||||
assign sel_result = (rwaddr[15:0] == RESULT_R );
|
||||
|
||||
// Write enable allocation
|
||||
assign we_testr = sel_testr & wren;
|
||||
assign we_dater = sel_dater & wren;
|
||||
assign we_win_time = sel_win_time & wren;
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// [SECTION D] Register Instantiation (Storage Implementation)
|
||||
// =============================================================================
|
||||
|
||||
// --- General and Test Registers ---
|
||||
sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n);
|
||||
sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n);
|
||||
|
||||
// --- Thermometer Functional Registers ---
|
||||
sirv_gnrl_dfflrd #(24) win_time_dff (32'h00_03E8, we_win_time, wrdata, win_time_r, clk, rst_n);
|
||||
|
||||
sirv_gnrl_dfflr #(24) result_dff (pules_cnt_vld,pulse_cnt_out,result_r, clk, rst_n);
|
||||
|
||||
// =============================================================================
|
||||
// [SECTION E] Special Business Logic (Business Logic)
|
||||
// =============================================================================
|
||||
|
||||
// LVDS Real-time status register
|
||||
// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n);
|
||||
|
||||
// =============================================================================
|
||||
// [SECTION F] Readback Logic (Readback Mux)
|
||||
// =============================================================================
|
||||
reg [31:0] rddata_reg;
|
||||
always @(*) begin
|
||||
rddata_reg = 32'b0;
|
||||
if (sel_testr) rddata_reg = testr;
|
||||
else if (sel_dater) rddata_reg = dater;
|
||||
else if (sel_win_time) rddata_reg = {8'b0,win_time_r};
|
||||
else if (sel_result) rddata_reg = {8'b0,result_r};
|
||||
end
|
||||
|
||||
sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n);
|
||||
|
||||
// =============================================================================
|
||||
// [SECTION G] Output Mapping (Output Assignments)
|
||||
// =============================================================================
|
||||
assign win_us = win_time_r;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -18,10 +18,10 @@ module TB();
|
|||
// Clock Generation
|
||||
initial clk = 0;
|
||||
always #(CLK_PERIOD/2) clk = ~clk;
|
||||
initial begin
|
||||
$fsdbDumpfile("wave.fsdb");
|
||||
$fsdbDumpvars();
|
||||
end
|
||||
// initial begin
|
||||
// $fsdbDumpfile("wave.fsdb");
|
||||
// $fsdbDumpvars();
|
||||
// end
|
||||
// ==========================================
|
||||
// DUT Instantiation
|
||||
// ==========================================
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_131020_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_131039_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_131040_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_14790_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_14816_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_26119_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_30584_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_30603_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_34047_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_34065_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_37423_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_37441_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_39101_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_39120_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_40330_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_40348_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_41475_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_41494_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_42301_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_42320_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_43406_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_43443_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_45855_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_45891_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_50099_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_50120_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_52045_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_52081_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_53444_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_53462_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_54606_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_54624_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_56094_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_56112_archive_1.so
|
||||
|
|
@ -0,0 +1 @@
|
|||
.//../simv.daidir//_57246_archive_1.so
|
||||
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Reference in New Issue