修改了spi温度计模块:win_us ->win_time(clk)

spi_thermometer_digital/rtl/digital_top.v

@@ -40,7 +40,7 @@ wire        wren;
 wire        rden;        
 wire  [31:0]rddata;      
 
-wire  [23:0] win_us;
+wire  [31:0] win_time;
 wire  cnt_vld;
 wire  [23:0]cnt_out;
 
@@ -71,7 +71,7 @@ wire  [23:0]cnt_out;
         .rden   (rden),
         .rddata (rddata),
         // digital_thermometer    
-        .win_us(win_us),
+        .win_time(win_time),
         .pulse_cnt_out(cnt_out),
         .pules_cnt_vld(cnt_vld)
     );
@@ -83,7 +83,7 @@ wire  [23:0]cnt_out;
         .clk    (clk),
         .rst_n  (rst_n),
         .sig_in (sig_in),
-        .win_us (win_us),
+        .win_time (win_time),
         .cnt_out(cnt_out),
         .vld_out(cnt_vld)
     );

spi_thermometer_digital/rtl/systemregfile/systemregfile.v

@@ -24,7 +24,7 @@ module system_regfile (
     input           rden,            
     output [31:0]   rddata,
 
-    output [23:0]win_us,
+    output [31:0] win_time,
     input [23:0]pulse_cnt_out,
     input pules_cnt_vld
 
@@ -52,8 +52,8 @@ module system_regfile (
 
 
 // Register storage wires (Storage Wires)
- wire [31:0] testr, dater;
+ wire [31:0] testr, dater , win_time_r;
- wire [23:0]  win_time_r, result_r;
+ wire [23:0]   result_r;
 // =============================================================================
 // [SECTION C] Decoding Logic (Decoding)
 // =============================================================================
@@ -77,7 +77,7 @@ sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, c
 sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n);
 
 // --- Thermometer Functional Registers ---
-sirv_gnrl_dfflrd #(24) win_time_dff (32'h00_03E8, we_win_time, wrdata, win_time_r, clk, rst_n);
+sirv_gnrl_dfflrd #(32) win_time_dff (32'h0000_C350, we_win_time, wrdata, win_time_r, clk, rst_n);
 
 sirv_gnrl_dfflr #(24) result_dff (pules_cnt_vld,pulse_cnt_out,result_r, clk, rst_n);
 
@@ -96,7 +96,7 @@ always @(*) begin
     rddata_reg = 32'b0;
     if      (sel_testr)       rddata_reg = testr;
     else if (sel_dater)       rddata_reg = dater;
-    else if (sel_win_time)    rddata_reg = {8'b0,win_time_r};
+    else if (sel_win_time)    rddata_reg = win_time_r;
     else if (sel_result)      rddata_reg = {8'b0,result_r};
 end
 
@@ -105,7 +105,7 @@ end
 // =============================================================================
 // [SECTION G] Output Mapping (Output Assignments)
 // =============================================================================
-    assign win_us            = win_time_r;
+    assign win_time            = win_time_r;
 
 
 endmodule

spi_thermometer_digital/rtl/therm/pulse_cnt.v

@@ -6,7 +6,7 @@ module pulse_cnt #(
     input  wire        clk,                  
     input  wire        rst_n,                
     input  wire        sig_in,               
-    input  wire [23:0] win_us,               
+    input  wire [31:0] win_time,               
     output reg  [23:0] cnt_out,             
     output reg         vld_out               
 );
@@ -40,7 +40,7 @@ module pulse_cnt #(
 
         end else begin
             vld_out <= 1'b0;  
-            target_cnt <= ( {40'd0, win_us} * CLK_FREQ) / 1_000_000 ;                 
+            target_cnt <= win_time ;                 
             // Window count end condition: current count reaches target_cnt
             if (window_cnt >= target_cnt) begin
                 cnt_out <= pulse_cnt;

spi_thermometer_digital/tb/tb_diginal_top.sv

@@ -54,11 +54,11 @@ module tb_digital_top();
             #(CLK_PERIOD * 10);
             spi_read(25'h0c, 5'h00);
             #(CLK_PERIOD * 10);
-            spi_write(25'h08, 5'h00, 32'h2);
+            spi_write(25'h08, 5'h00, 32'h61a8);
             end
 
             begin
-                gen_pulses(1000,5);
+                gen_pulses(400,5);
             end
         join
 

spi_thermometer_digital/tb/tb_diginal_top.v

@@ -1,119 +0,0 @@
-`timescale 1ns / 1ps
-
-module tb_digital_top();
-
-    // 参数定义
-    parameter CLK_PERIOD = 10;      // 100MHz 系统时钟
-    parameter SCLK_PERIOD = 100;    // 10MHz SPI时钟 (必须比系统时钟慢)
-
-    // 信号声明
-    logic clk;
-    logic rst_n;
-    logic [4:0] cfgid;
-    
-    logic sclk;
-    logic csn;
-    logic mosi;
-    logic miso;
-    logic oen;
-
-
-    // 实例化 DUT
-    digital_top u_digital_top (
-        .clk     (clk    ),
-        .rst_n   (rst_n  ),
-        .cfgid   (cfgid  ),
-        .sclk    (sclk   ),
-        .csn     (csn    ),
-        .mosi    (mosi   ),
-        .miso    (miso   ),
-        .oen     (oen    ),
-        .sig_in  (       )
-    );
-
-    // 系统时钟产生
-    initial begin
-        clk = 0;
-        forever #(CLK_PERIOD/2) clk = ~clk;
-    end
-
-    // 初始复位与赋值
-    initial begin
-        rst_n = 0;
-        sclk  = 0;
-        csn   = 1;
-        mosi  = 0;
-        cfgid = 5'h0A; // 设定芯片ID为 10
-
-        #(CLK_PERIOD * 10);
-        rst_n = 1;
-        #(CLK_PERIOD * 10);
-
-        // --- 开始测试 ---
-        
-        // 1. 测试写操作: 写入 0x12345678 到 地址 0x100
-        spi_write(25'h100, 5'h0A, 32'h12345678);
-        
-        #(SCLK_PERIOD * 5);
-
-        // 2. 测试读操作: 从地址 0x100 读取 (验证读使能和地址)
-        spi_read(25'h222, 5'h0A);
-
-        #(SCLK_PERIOD * 20);
-        $display("Test Bench Finished.");
-        $finish;
-    end
-
-    // ---------------------------------------------------------
-    // Task: SPI 发送/接收 32位数据
-    // ---------------------------------------------------------
-    task spi_xfer_32(input [31:0] data_in, output [31:0] data_out);
-        for (int i = 31; i >= 0; i--) begin
-            mosi = data_in[i];      // MSB First
-            #(SCLK_PERIOD/2);
-            sclk = 1;               // 上升沿，DUT采样
-            #(SCLK_PERIOD/2);
-            data_out[i] = miso;     // 采样从机发回的数据
-            sclk = 0;
-        end
-    endtask
-
-    // ---------------------------------------------------------
-    // Task: 写操作 (wnr=0)
-    // ---------------------------------------------------------
-    task spi_write(input [24:0] target_addr, input [4:0] id, input [31:0] data);
-        logic [31:0] header;
-        logic [31:0] dummy;
-        
-        header = {1'b0, target_addr, id, 1'b0}; // 构造命令帧
-        
-        $display("[WRITE] Addr: %h, Data: %h", target_addr, data);
-        
-        csn = 0;
-        spi_xfer_32(header, dummy); // 发送命令
-        spi_xfer_32(data,   dummy); // 发送数据
-        csn = 1;
-        mosi = 0;
-    endtask
-
-    // ---------------------------------------------------------
-    // Task: 读操作 (wnr=1)
-    // ---------------------------------------------------------
-    task spi_read(input [24:0] target_addr, input [4:0] id);
-        logic [31:0] header;
-        logic [31:0] read_val;
-        
-        header = {1'b1, target_addr, id, 1'b0}; // 构造命令帧 (wnr=1)
-        
-        $display("[READ]  Addr: %h", target_addr);
-        
-        csn = 0;
-        spi_xfer_32(header, read_val); // 发送命令帧，此时读回的可能是无用数据
-        spi_xfer_32(32'h0,  read_val); // 发送Dummy，接收真正的读数据
-        csn = 1;
-        mosi = 0;
-        
-        $display("[READ]  Result: %h", read_val);
-    endtask
-
-endmodule