修改了spi温度计模块:win_us ->win_time(clk)
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7d227dad2e
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5761fb9a62
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@ -40,7 +40,7 @@ wire wren;
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wire rden;
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wire [31:0]rddata;
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wire [23:0] win_us;
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wire [31:0] win_time;
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wire cnt_vld;
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wire [23:0]cnt_out;
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@ -71,7 +71,7 @@ wire [23:0]cnt_out;
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.rden (rden),
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.rddata (rddata),
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// digital_thermometer
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.win_us(win_us),
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.win_time(win_time),
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.pulse_cnt_out(cnt_out),
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.pules_cnt_vld(cnt_vld)
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);
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@ -83,7 +83,7 @@ wire [23:0]cnt_out;
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.clk (clk),
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.rst_n (rst_n),
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.sig_in (sig_in),
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.win_us (win_us),
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.win_time (win_time),
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.cnt_out(cnt_out),
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.vld_out(cnt_vld)
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);
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@ -24,7 +24,7 @@ module system_regfile (
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input rden,
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output [31:0] rddata,
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output [23:0]win_us,
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output [31:0] win_time,
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input [23:0]pulse_cnt_out,
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input pules_cnt_vld
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@ -52,8 +52,8 @@ module system_regfile (
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// Register storage wires (Storage Wires)
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wire [31:0] testr, dater;
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wire [23:0] win_time_r, result_r;
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wire [31:0] testr, dater , win_time_r;
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wire [23:0] result_r;
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// =============================================================================
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// [SECTION C] Decoding Logic (Decoding)
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// =============================================================================
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@ -77,7 +77,7 @@ sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, c
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sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n);
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// --- Thermometer Functional Registers ---
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sirv_gnrl_dfflrd #(24) win_time_dff (32'h00_03E8, we_win_time, wrdata, win_time_r, clk, rst_n);
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sirv_gnrl_dfflrd #(32) win_time_dff (32'h0000_C350, we_win_time, wrdata, win_time_r, clk, rst_n);
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sirv_gnrl_dfflr #(24) result_dff (pules_cnt_vld,pulse_cnt_out,result_r, clk, rst_n);
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@ -96,7 +96,7 @@ always @(*) begin
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rddata_reg = 32'b0;
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if (sel_testr) rddata_reg = testr;
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else if (sel_dater) rddata_reg = dater;
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else if (sel_win_time) rddata_reg = {8'b0,win_time_r};
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else if (sel_win_time) rddata_reg = win_time_r;
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else if (sel_result) rddata_reg = {8'b0,result_r};
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end
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@ -105,7 +105,7 @@ end
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// =============================================================================
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// [SECTION G] Output Mapping (Output Assignments)
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// =============================================================================
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assign win_us = win_time_r;
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assign win_time = win_time_r;
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endmodule
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@ -6,7 +6,7 @@ module pulse_cnt #(
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input wire clk,
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input wire rst_n,
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input wire sig_in,
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input wire [23:0] win_us,
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input wire [31:0] win_time,
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output reg [23:0] cnt_out,
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output reg vld_out
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);
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@ -40,7 +40,7 @@ module pulse_cnt #(
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end else begin
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vld_out <= 1'b0;
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target_cnt <= ( {40'd0, win_us} * CLK_FREQ) / 1_000_000 ;
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target_cnt <= win_time ;
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// Window count end condition: current count reaches target_cnt
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if (window_cnt >= target_cnt) begin
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cnt_out <= pulse_cnt;
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@ -54,11 +54,11 @@ module tb_digital_top();
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#(CLK_PERIOD * 10);
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spi_read(25'h0c, 5'h00);
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#(CLK_PERIOD * 10);
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spi_write(25'h08, 5'h00, 32'h2);
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spi_write(25'h08, 5'h00, 32'h61a8);
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end
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begin
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gen_pulses(1000,5);
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gen_pulses(400,5);
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end
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join
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@ -1,119 +0,0 @@
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`timescale 1ns / 1ps
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module tb_digital_top();
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// 参数定义
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parameter CLK_PERIOD = 10; // 100MHz 系统时钟
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parameter SCLK_PERIOD = 100; // 10MHz SPI时钟 (必须比系统时钟慢)
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// 信号声明
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logic clk;
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logic rst_n;
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logic [4:0] cfgid;
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logic sclk;
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logic csn;
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logic mosi;
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logic miso;
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logic oen;
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// 实例化 DUT
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digital_top u_digital_top (
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.clk (clk ),
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.rst_n (rst_n ),
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.cfgid (cfgid ),
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.sclk (sclk ),
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.csn (csn ),
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.mosi (mosi ),
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.miso (miso ),
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.oen (oen ),
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.sig_in ( )
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);
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// 系统时钟产生
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initial begin
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clk = 0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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// 初始复位与赋值
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initial begin
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rst_n = 0;
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sclk = 0;
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csn = 1;
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mosi = 0;
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cfgid = 5'h0A; // 设定芯片ID为 10
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#(CLK_PERIOD * 10);
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rst_n = 1;
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#(CLK_PERIOD * 10);
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// --- 开始测试 ---
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// 1. 测试写操作: 写入 0x12345678 到 地址 0x100
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spi_write(25'h100, 5'h0A, 32'h12345678);
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#(SCLK_PERIOD * 5);
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// 2. 测试读操作: 从地址 0x100 读取 (验证读使能和地址)
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spi_read(25'h222, 5'h0A);
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#(SCLK_PERIOD * 20);
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$display("Test Bench Finished.");
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$finish;
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end
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// ---------------------------------------------------------
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// Task: SPI 发送/接收 32位数据
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// ---------------------------------------------------------
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task spi_xfer_32(input [31:0] data_in, output [31:0] data_out);
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for (int i = 31; i >= 0; i--) begin
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mosi = data_in[i]; // MSB First
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#(SCLK_PERIOD/2);
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sclk = 1; // 上升沿，DUT采样
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#(SCLK_PERIOD/2);
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data_out[i] = miso; // 采样从机发回的数据
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sclk = 0;
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end
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endtask
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// ---------------------------------------------------------
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// Task: 写操作 (wnr=0)
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// ---------------------------------------------------------
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task spi_write(input [24:0] target_addr, input [4:0] id, input [31:0] data);
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logic [31:0] header;
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logic [31:0] dummy;
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header = {1'b0, target_addr, id, 1'b0}; // 构造命令帧
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$display("[WRITE] Addr: %h, Data: %h", target_addr, data);
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csn = 0;
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spi_xfer_32(header, dummy); // 发送命令
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spi_xfer_32(data, dummy); // 发送数据
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csn = 1;
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mosi = 0;
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endtask
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// ---------------------------------------------------------
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// Task: 读操作 (wnr=1)
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// ---------------------------------------------------------
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task spi_read(input [24:0] target_addr, input [4:0] id);
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logic [31:0] header;
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logic [31:0] read_val;
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header = {1'b1, target_addr, id, 1'b0}; // 构造命令帧 (wnr=1)
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$display("[READ] Addr: %h", target_addr);
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csn = 0;
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spi_xfer_32(header, read_val); // 发送命令帧，此时读回的可能是无用数据
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spi_xfer_32(32'h0, read_val); // 发送Dummy，接收真正的读数据
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csn = 1;
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mosi = 0;
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$display("[READ] Result: %h", read_val);
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endtask
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endmodule
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