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organize the table + translate

This commit is contained in:
yangshenbo 2026-04-07 09:50:35 +08:00
parent 35f9c31fe0
commit 3368b7c023
156 changed files with 11739 additions and 652 deletions
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10
rtl/digital_top.v
View File

@ -28,11 +28,11 @@ module digital_top(
input sig_in input sig_in
); );
wire [31:0] w_wrdata; // DUT -> SRAM 写数据 wire [31:0] w_wrdata;
wire [24:0] w_addr; // DUT -> SRAM 地址 wire [24:0] w_addr;
wire w_wren; // 写使能 wire w_wren;
wire w_rden; // 读使能 wire w_rden;
wire [31:0] w_rddata; // SRAM -> DUT 读数据 wire [31:0] w_rddata;
wire [23:0] win_us; wire [23:0] win_us;
wire [1:0] out_mode; wire [1:0] out_mode;

266
rtl/systemregfile/my_systemregfile.v
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@ -1,134 +1,134 @@
//+FHDR-------------------------------------------------------------------------------------------------------- //+FHDR--------------------------------------------------------------------------------------------------------
// 增加一个新寄存器： // Add a new register:
// SECTION A: 添加 localparam ADDR_NEW = 16'hXX;。 // SECTION A: Add localparam ADDR_NEW = 16'hXX;.
// SECTION B: 声明 wire sel_new, we_new, [31:0] reg_new;。 // SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;.
// SECTION C: 增加译码逻辑：assign sel_new = (reg_idx == ADDR_NEW >> 2);。 // SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);.
// SECTION D: 调用底层库，例如 sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);。 // SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);.
// SECTION F: 在 always 块中加入 else if (sel_new) rddata_reg = reg_new;。 // SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block.
// SECTION G: 将 reg_new 映射给模块的输出端口。 // SECTION G: Map reg_new to the module's output ports.
//-FHDR-------------------------------------------------------------------------------------------------------- //-FHDR--------------------------------------------------------------------------------------------------------
module system_regfile ( module system_regfile (
// [BLOCK 0] 系统与总线接口 // [BLOCK 0] System and Bus Interface
input clk, input clk,
input rst_n, input rst_n,
input [31:0] wrdata, input [31:0] wrdata,
input wren, input wren,
input [24:0] rwaddr, input [24:0] rwaddr,
input rden, input rden,
output [31:0] rddata, output [31:0] rddata,
output [23:0]win_us, output [23:0]win_us,
output [1:0]out_mode, //0输出对应温度， 1输出对应的频率，2单位窗口输出脉冲的个数 output [1:0]out_mode, //0: output temperature, 1: output frequency, 2: output pulse count per window
output [15:0]temp_85_fre_k, //85°对应的频率,默认为600khz output [15:0]temp_85_fre_k, //Frequency at 85¡ãC, default 600khz
output [15:0]temp_neg_40_fre_k , //-40对应的频率，默认为160khz,单位khz output [15:0]temp_neg_40_fre_k , //Frequency at -40¡ãC, default 160khz, unit khz
output report_en, output report_en,
output [23:0]rep_gap_us, //最小位win_us 小于就不上报了 output [23:0]rep_gap_us, //Minimum interval (us), no reporting if smaller than win_us
input [23:0]therm_out, input [23:0]therm_out,
input therm_vld input therm_vld
); );
// ============================================================================= // =============================================================================
// [SECTION A] 地址偏移定义 (Localparams) // [SECTION A] Address Offset Definition (Localparams)
// ============================================================================= // =============================================================================
localparam TESTR = 16'h00, DATER = 16'h04; localparam TESTR = 16'h00, DATER = 16'h04;
localparam WIN_MODE_R = 16'h08; // 配置窗口时间与输出模式 localparam WIN_MODE_R = 16'h08; // Configure window time and output mode
localparam CALIB_R = 16'h0C; // 标定参数寄存器 localparam CALIB_R = 16'h0C; // Calibration parameter register
localparam REPORT_R = 16'h10; // 上报使能与间隔 localparam REPORT_R = 16'h10; // Report enable and interval
localparam RESULT_R = 16'h14; // 状态与结果寄存器 (只读) localparam RESULT_R = 16'h14; // Status and result register (Read-only)
// ============================================================================= // =============================================================================
// [SECTION B] 内部连线声明 (Wires) // [SECTION B] Internal Wire Declaration (Wires)
// ============================================================================= // =============================================================================
// 寄存器选择信号 (Enable Wires) // Register selection signals (Enable Wires)
wire sel_testr, sel_dater; wire sel_testr, sel_dater;
wire sel_win_mode, sel_calib, sel_report, sel_result; wire sel_win_mode, sel_calib, sel_report, sel_result;
// 写使能信号 (Write Enable Wires) // Write enable signals (Write Enable Wires)
wire we_testr, we_dater; wire we_testr, we_dater;
wire we_win_mode, we_calib, we_report; wire we_win_mode, we_calib, we_report;
// 寄存器存储连线 (Storage Wires) // Register storage wires (Storage Wires)
wire [31:0] testr, dater; wire [31:0] testr, dater;
wire [31:0] win_mode_r, calib_r, report_r, result_r; wire [31:0] win_mode_r, calib_r, report_r, result_r;
// ============================================================================= // =============================================================================
// [SECTION C] 译码逻辑 (Decoding) // [SECTION C] Decoding Logic (Decoding)
// ============================================================================= // =============================================================================
assign sel_testr = (rwaddr[15:0] == TESTR ); assign sel_testr = (rwaddr[15:0] == TESTR );
assign sel_dater = (rwaddr[15:0] == DATER ); assign sel_dater = (rwaddr[15:0] == DATER );
assign sel_win_mode = (rwaddr[15:0] == WIN_MODE_R ); assign sel_win_mode = (rwaddr[15:0] == WIN_MODE_R );
assign sel_calib = (rwaddr[15:0] == CALIB_R ); assign sel_calib = (rwaddr[15:0] == CALIB_R );
assign sel_report = (rwaddr[15:0] == REPORT_R ); assign sel_report = (rwaddr[15:0] == REPORT_R );
assign sel_result = (rwaddr[15:0] == RESULT_R ); assign sel_result = (rwaddr[15:0] == RESULT_R );
// 写使能分配 // Write enable allocation
assign we_testr = sel_testr & wren; assign we_testr = sel_testr & wren;
assign we_dater = sel_dater & wren; assign we_dater = sel_dater & wren;
assign we_win_mode = sel_win_mode & wren; assign we_win_mode = sel_win_mode & wren;
assign we_calib = sel_calib & wren; assign we_calib = sel_calib & wren;
assign we_report = sel_report & wren; assign we_report = sel_report & wren;
// ============================================================================= // =============================================================================
// [SECTION D] 寄存器实例化 (Storage Implementation) // [SECTION D] Register Instantiation (Storage Implementation)
// ============================================================================= // =============================================================================
// --- 通用与测试寄存器 --- // --- General and Test Registers ---
sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n); sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n);
sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n); sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n);
// --- 温度计业务寄存器 --- // --- Thermometer Functional Registers ---
// win_mode_r: [25:24] out_mode, [23:0] win_us (默认窗口 1000us) // win_mode_r: [25:24] out_mode, [23:0] win_us (Default window 1000us)
sirv_gnrl_dfflrd #(32) win_mode_dff (32'h0000_03E8, we_win_mode, wrdata, win_mode_r, clk, rst_n); sirv_gnrl_dfflrd #(32) win_mode_dff (32'h0000_03E8, we_win_mode, wrdata, win_mode_r, clk, rst_n);
// calib_r: [31:16] 85度频率(默认600k), [15:0] -40度频率(默认160k) // calib_r: [31:16] Frequency at 85¡ãC (default 600k), [15:0] Frequency at -40¡ãC (default 160k)
sirv_gnrl_dfflrd #(32) calib_dff (32'h0258_00A0, we_calib, wrdata, calib_r, clk, rst_n); sirv_gnrl_dfflrd #(32) calib_dff (32'h0258_00A0, we_calib, wrdata, calib_r, clk, rst_n);
// report_r: [31] report_en, [23:0] rep_gap_us (默认间隔 50ms) // report_r: [31] report_en, [23:0] rep_gap_us (Default interval 50ms)
sirv_gnrl_dfflrd #(32) report_dff (32'h0000_C350, we_report, wrdata, report_r, clk, rst_n); sirv_gnrl_dfflrd #(32) report_dff (32'h0000_C350, we_report, wrdata, report_r, clk, rst_n);
sirv_gnrl_dffr #(32) result_dff ({8'b0,therm_out},result_r, clk, rst_n); sirv_gnrl_dffr #(32) result_dff ({8'b0,therm_out},result_r, clk, rst_n);
// ============================================================================= // =============================================================================
// [SECTION E] 特殊业务逻辑 (Business Logic) // [SECTION E] Special Business Logic (Business Logic)
// ============================================================================= // =============================================================================
// LVDS 实时状态寄存器 // LVDS Real-time status register
// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n); // sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n);
// ============================================================================= // =============================================================================
// [SECTION F] 读回逻辑 (Readback Mux) // [SECTION F] Readback Logic (Readback Mux)
// ============================================================================= // =============================================================================
reg [31:0] rddata_reg; reg [31:0] rddata_reg;
always @(*) begin always @(*) begin
rddata_reg = 32'b0; rddata_reg = 32'b0;
if (sel_testr) rddata_reg = testr; if (sel_testr) rddata_reg = testr;
else if (sel_dater) rddata_reg = dater; else if (sel_dater) rddata_reg = dater;
else if (sel_win_mode) rddata_reg = win_mode_r; else if (sel_win_mode) rddata_reg = win_mode_r;
else if (sel_calib) rddata_reg = calib_r; else if (sel_calib) rddata_reg = calib_r;
else if (sel_report) rddata_reg = report_r; else if (sel_report) rddata_reg = report_r;
else if (sel_result) rddata_reg = result_r; else if (sel_result) rddata_reg = result_r;
end end
sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n); sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n);
// ============================================================================= // =============================================================================
// [SECTION G] 输出映射 (Output Assignments) // [SECTION G] Output Mapping (Output Assignments)
// ============================================================================= // =============================================================================
assign win_us = win_mode_r[23:0]; assign win_us = win_mode_r[23:0];
assign out_mode = win_mode_r[25:24]; assign out_mode = win_mode_r[25:24];
assign temp_85_fre_k = calib_r[31:16]; assign temp_85_fre_k = calib_r[31:16];
assign temp_neg_40_fre_k = calib_r[15:0]; assign temp_neg_40_fre_k = calib_r[15:0];
assign report_en = report_r[31]; assign report_en = report_r[31];
assign rep_gap_us = report_r[23:0]; assign rep_gap_us = report_r[23:0];
endmodule endmodule

684
rtl/systemregfile/sirv_gnrl_dffs.v
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@ -1,342 +1,342 @@
/* /*
Copyright 2018-2020 Nuclei System Technology, Inc. Copyright 2018-2020 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
You may obtain a copy of the License at You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0 http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and See the License for the specific language governing permissions and
limitations under the License. limitations under the License.
*/ */
//===================================================================== //=====================================================================
// //
// Designer : Bob Hu // Designer : Bob Hu
// //
// Description: // Description:
// All of the general DFF and Latch modules // All of the general DFF and Latch modules
// //
// ==================================================================== // ====================================================================
// //
// //
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1 // Default reset value is 1
// //
// =========================================================================== // ===========================================================================
`define DISABLE_SV_ASSERTION `define DISABLE_SV_ASSERTION
`define dly #0.2 `define dly #0.2
module sirv_gnrl_dfflrs # ( module sirv_gnrl_dfflrs # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC begin : DFFLRS_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b1}}; qout_r <= {DW{1'b1}};
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0 // Default reset value is 0
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dfflr # ( module sirv_gnrl_dfflr # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC begin : DFFLR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b0}}; qout_r <= {DW{1'b0}};
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is input // Default reset value is input
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dfflrd # ( module sirv_gnrl_dfflrd # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] init, input [DW-1:0] init,
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC begin : DFFLR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= init; qout_r <= init;
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable, no reset // Verilog module sirv_gnrl DFF with Load-enable, no reset
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffl # ( module sirv_gnrl_dffl # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk input clk
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk) always @(posedge clk)
begin : DFFL_PROC begin : DFFL_PROC
if (lden == 1'b1) if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable // Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1 // Default reset value is 1
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffrs # ( module sirv_gnrl_dffrs # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC begin : DFFRS_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b1}}; qout_r <= {DW{1'b1}};
else else
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable // Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0 // Default reset value is 0
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffr # ( module sirv_gnrl_dffr # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFR_PROC begin : DFFR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b0}}; qout_r <= {DW{1'b0}};
else else
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module for general latch // Verilog module for general latch
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_ltch # ( module sirv_gnrl_ltch # (
parameter DW = 32 parameter DW = 32
) ( ) (
//input test_mode, //input test_mode,
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout output [DW-1:0] qout
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @ * always @ *
begin : LTCH_PROC begin : LTCH_PROC
if (lden == 1'b1) if (lden == 1'b1)
qout_r <= dnxt; qout_r <= dnxt;
end end
//assign qout = test_mode ? dnxt : qout_r; //assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
always_comb always_comb
begin begin
CHECK_THE_X_VALUE: CHECK_THE_X_VALUE:
assert (lden !== 1'bx) assert (lden !== 1'bx)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
end end
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// module sirv_gnrl_edffr #(parameter type T = logic) ( // module sirv_gnrl_edffr #(parameter type T = logic) (
// input T dnxt, // input T dnxt,
// output T qout, // output T qout,
// input clk, rst_n // input clk, rst_n
// ); // );
// T qout_r; // T qout_r;
// always_ff @(posedge clk or negedge rst_n) begin // always_ff @(posedge clk or negedge rst_n) begin
// if (!rst_n) qout_r <= T'('0); // if (!rst_n) qout_r <= T'('0);
// else qout_r <= `dly dnxt; // else qout_r <= `dly dnxt;
// end // end
// assign qout = qout_r; // assign qout = qout_r;
// endmodule // endmodule

32
rtl/digital_thermometer.v → rtl/therm/digital_thermometer.v
View File

@ -11,11 +11,11 @@ module digital_thermometer(
input rst_n, input rst_n,
input sig_in, input sig_in,
input [23:0]win_us, input [23:0]win_us,
input [1:0]out_mode, //0输出对应温度， 1输出对应的频率，2单位窗口输出脉冲的个数 input [1:0]out_mode, //0: output temperature, 1: output frequency, 2: output pulse count per window
input [15:0]temp_85_fre_k, //85°对应的频率,默认为600khz input [15:0]temp_85_fre_k, //Frequency at 85¡ãC, default 600khz
input [15:0]temp_neg_40_fre_k , //-40对应的频率，默认为160khz,单位khz input [15:0]temp_neg_40_fre_k , //Frequency at -40¡ãC, default 160khz, unit khz
input report_en, //主动上报使能 input report_en, //Auto report enable
input [23:0]rep_gap_us, //最小位win_us input [23:0]rep_gap_us, //Minimum report gap (us)
output reg [23:0]therm_out, output reg [23:0]therm_out,
output reg therm_vld output reg therm_vld
); );
@ -23,28 +23,28 @@ module digital_thermometer(
wire [23:0] wd_cnt_out; wire [23:0] wd_cnt_out;
wire wd_cnt_vld; wire wd_cnt_vld;
reg [23:0] gap_cnt; // 上报间隔计数器 reg [23:0] gap_cnt; // Report interval counter
wire [23:0] cur_freq_khz; wire [23:0] cur_freq_khz;
reg signed [23:0] temp_scaled; reg signed [23:0] temp_scaled;
assign cur_freq_khz = (wd_cnt_out * 1000) / win_us; assign cur_freq_khz = (wd_cnt_out * 1000) / win_us;
//我们将温度结果放大100倍 //Scale temperature result by 100 times
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
temp_scaled <= 0; temp_scaled <= 0;
end else if (wd_cnt_vld) begin end else if (wd_cnt_vld) begin
// 如果当前频率低于或等于 -40度对应的标定频率，直接输出 -4000 //If current frequency <= calibrated frequency at -40¡ãC, output -4000 directly
if (cur_freq_khz <= temp_neg_40_fre_k) begin if (cur_freq_khz <= temp_neg_40_fre_k) begin
temp_scaled <= -32'sd4000; temp_scaled <= -32'sd4000;
end end
else begin else begin
// 只有在频率大于下限时，才进行插值计算，避免减法溢出 //Calculate interpolation only when frequency > lower limit to avoid subtraction overflow
temp_scaled <= ((cur_freq_khz - temp_neg_40_fre_k) * 12500) / (temp_85_fre_k - temp_neg_40_fre_k) - 4000; temp_scaled <= ((cur_freq_khz - temp_neg_40_fre_k) * 12500) / (temp_85_fre_k - temp_neg_40_fre_k) - 4000;
end end
end end
end end
// 上报逻辑与输出选择 // Report logic and output selection
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
gap_cnt <= 0; gap_cnt <= 0;
@ -65,11 +65,11 @@ module digital_thermometer(
therm_vld <= 1'b0; therm_vld <= 1'b0;
end end
// 模式切换输出 //Output mode switching
case (out_mode) case (out_mode)
2'd0: therm_out <= temp_scaled; // 输出放大100倍的温度 2'd0: therm_out <= temp_scaled; //Output temperature scaled by 100
2'd1: therm_out <= cur_freq_khz; // 输出频率(kHz) 2'd1: therm_out <= cur_freq_khz; //Output frequency (kHz)
2'd2: therm_out <= wd_cnt_out; // 输出原始脉冲计数值 2'd2: therm_out <= wd_cnt_out; //Output raw pulse count
default: therm_out <= temp_scaled; default: therm_out <= temp_scaled;
endcase endcase
end end
@ -79,7 +79,7 @@ module digital_thermometer(
end end
// 实例化被测模块 //Instantiate sub-module
pulse_cnt #( pulse_cnt #(
.CLK_FREQ(50_000_000) .CLK_FREQ(50_000_000)
) pulse_cnt_inst ( ) pulse_cnt_inst (
@ -91,4 +91,4 @@ module digital_thermometer(
.vld_out(wd_cnt_vld) .vld_out(wd_cnt_vld)
); );
endmodule endmodule

15
rtl/pulse_cnt.v → rtl/therm/pulse_cnt.v
View File

@ -12,14 +12,13 @@ module pulse_cnt #(
); );
reg [31:0] window_cnt; // 当前时钟周期计数 reg [31:0] window_cnt; // Current clock cycle count
reg [31:0] target_cnt; // 当前窗口所需时钟周期数 reg [31:0] target_cnt; // Required clock cycles for current measurement window
// 脉冲计数（宽度与输出一致，防止溢出） // Pulse counter (width matches output to prevent overflow)
reg [23:0] pulse_cnt; reg [23:0] pulse_cnt;
// 标志：是否正在计算新的 target_cnt（避免组合逻辑环路）
reg calc_done;
reg sig_sync1, sig_sync2, sig_sync3; reg sig_sync1, sig_sync2, sig_sync3;
wire sig_rise = sig_sync2 & ~sig_sync3; wire sig_rise = sig_sync2 & ~sig_sync3;
@ -30,7 +29,7 @@ module pulse_cnt #(
sig_sync3 <= sig_sync2; sig_sync3 <= sig_sync2;
end end
// 主控制逻辑 // Main control logic
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
window_cnt <= 0; window_cnt <= 0;
@ -42,11 +41,11 @@ module pulse_cnt #(
end else begin end else begin
vld_out <= 1'b0; vld_out <= 1'b0;
target_cnt <= ( {40'd0, win_us} * CLK_FREQ) / 1_000_000 ; target_cnt <= ( {40'd0, win_us} * CLK_FREQ) / 1_000_000 ;
// 窗口计数结束条件：当前计数值到达 target_cnt // Window count end condition: current count reaches target_cnt
if (window_cnt >= target_cnt) begin if (window_cnt >= target_cnt) begin
cnt_out <= pulse_cnt; cnt_out <= pulse_cnt;
vld_out <= 1'b1; vld_out <= 1'b1;
// 复位窗口计数器与脉冲计数器，并触发重新计算目标值 // Reset window counter and pulse counter, trigger target value recalculation
window_cnt <= 0; window_cnt <= 0;
pulse_cnt <= 0; pulse_cnt <= 0;
end else begin end else begin

0
rtl/uart_byte_rx.v → rtl/uart/uart_byte_rx.v
View File

0
rtl/uart_byte_tx.v → rtl/uart/uart_byte_tx.v
View File

52
rtl/uart_ctrl_sysreg.v → rtl/uart/uart_ctrl_sysreg.v
View File

@ -6,16 +6,16 @@ module uart_ctrl_sysreg #(
)( )(
input clk input clk
,input rst_n ,input rst_n
// 串口接口 // UART Interface
,input uart_rx ,input uart_rx
,output uart_tx ,output uart_tx
//5口 // Register File Interface
,output reg [31:0] o_wrdata //write data to sram ,output reg [31:0] o_wrdata //write data to register file
,output reg [24:0] o_addr //sram address ,output reg [24:0] o_addr //register file address
,output reg o_wren //write enable sram ,output reg o_wren //write enable to register file
,output reg o_rden //rden enable sram ,output reg o_rden //read enable to register file
,input [31:0] i_rddata //read data from sram ,input [31:0] i_rddata //read data from register file
//主动上报机制 // Auto-Report Mechanism
,input [23:0] i_report_data ,input [23:0] i_report_data
,input i_report_vld ,input i_report_vld
); );
@ -37,12 +37,12 @@ module uart_ctrl_sysreg #(
); );
// 协议解析寄存器 // Protocol parsing registers
reg [63:0] cmd_reg; reg [63:0] cmd_reg;
reg [31:0]wr_data_buff; reg [31:0] wr_data_buff;
reg [19:0] data_bytes_len; reg [19:0] data_bytes_len;
// 状态机定义 // State machine definition
reg [2:0] state; reg [2:0] state;
localparam S_IDLE = 3'd0, localparam S_IDLE = 3'd0,
S_RX_CMD_L = 3'd1, S_RX_CMD_L = 3'd1,
@ -50,14 +50,14 @@ module uart_ctrl_sysreg #(
S_WAIT_RD = 3'd3, S_WAIT_RD = 3'd3,
S_RD_DATA = 3'd4, S_RD_DATA = 3'd4,
S_WR_DATA = 3'd5, S_WR_DATA = 3'd5,
S_REPORT = 3'd6; //主动上报状态 S_REPORT = 3'd6; // Auto-report state
// --- 主动上报数据先锁存着 --- // Latch auto-report data
reg [23:0] report_data_latch; reg [23:0] report_data_latch;
reg report_pending; reg report_pending;
// 捕捉上报脉冲：如果当前忙，先存起来 // Capture report pulse: store if busy
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin if(!rst_n) begin
report_pending <= 1'b0; report_pending <= 1'b0;
@ -66,7 +66,7 @@ module uart_ctrl_sysreg #(
report_pending <= 1'b1; report_pending <= 1'b1;
report_data_latch <= i_report_data; report_data_latch <= i_report_data;
end else if(state == S_REPORT) begin end else if(state == S_REPORT) begin
report_pending <= 1'b0; // 进入上报状态后清除标志 report_pending <= 1'b0; // Clear flag after entering report state
end end
end end
@ -83,7 +83,7 @@ module uart_ctrl_sysreg #(
end end
else begin else begin
case(state) case(state)
S_IDLE : begin //0 S_IDLE : begin // IDLE state
uart_tx_go <= 1'b0; uart_tx_go <= 1'b0;
if(uart_rx_done) begin if(uart_rx_done) begin
cmd_reg[63:32] <= uart_rx_data; cmd_reg[63:32] <= uart_rx_data;
@ -93,33 +93,33 @@ module uart_ctrl_sysreg #(
state <= S_REPORT; state <= S_REPORT;
end end
end end
S_RX_CMD_L : begin //1 S_RX_CMD_L : begin // Receive lower command word
if(uart_rx_done)begin if(uart_rx_done)begin
cmd_reg[31:0] <= uart_rx_data; cmd_reg[31:0] <= uart_rx_data;
state <= S_PARSE; state <= S_PARSE;
end end
end end
S_PARSE : begin //2 S_PARSE : begin // Parse command
o_addr <= cmd_reg[56:32]; o_addr <= cmd_reg[56:32];
data_bytes_len <= cmd_reg[19:0]; data_bytes_len <= cmd_reg[19:0];
if(cmd_reg[63] == 1'b1) begin //读指令 if(cmd_reg[63] == 1'b1) begin // Read command
o_rden <= 1'b1; o_rden <= 1'b1;
state <= S_WAIT_RD; state <= S_WAIT_RD;
end end
else begin //写指令 else begin // Write command
state <= S_WR_DATA; state <= S_WR_DATA;
end end
end end
S_WAIT_RD : begin //3 S_WAIT_RD : begin // Wait for read data ready
o_rden <= 1'b0; o_rden <= 1'b0;
state <= S_RD_DATA; state <= S_RD_DATA;
end end
S_RD_DATA :begin //4 S_RD_DATA :begin // Transmit read data
uart_tx_data <= i_rddata; uart_tx_data <= i_rddata;
uart_tx_go <= 1'b1; uart_tx_go <= 1'b1;
state <= S_IDLE; state <= S_IDLE;
end end
S_WR_DATA : begin //5 S_WR_DATA : begin // Receive and write data
o_wren <= 1'b0; o_wren <= 1'b0;
if(data_bytes_len != 0)begin if(data_bytes_len != 0)begin
if(uart_rx_done) begin if(uart_rx_done) begin
@ -132,8 +132,8 @@ module uart_ctrl_sysreg #(
state <= S_IDLE; state <= S_IDLE;
end end
end end
S_REPORT : begin //6 S_REPORT : begin // Auto-report data
// 构造上报数据包，例如：[8'hAA (帧头) + 24'bit温度数据] // Construct report packet: [8'hAA (header) + 24bit sensor data]
uart_tx_data <= {8'hAA, report_data_latch}; uart_tx_data <= {8'hAA, report_data_latch};
uart_tx_go <= 1'b1; uart_tx_go <= 1'b1;
state <= S_IDLE; state <= S_IDLE;
@ -148,6 +148,4 @@ module uart_ctrl_sysreg #(
endmodule endmodule

52
rtl/uart_top_32bit.v → rtl/uart/uart_top_32bit.v
View File

@ -16,19 +16,19 @@ module uart_top_32bit #(
input Clk, input Clk,
input Reset_n, input Reset_n,
// 32位发送接口 // 32-bit Transmit Interface
input Send_Go32, // 32位发送启动脉冲 input Send_Go32, // 32-bit transmit start pulse
input [31:0] Tx_Data32, // 待发送的32位数据 input [31:0] Tx_Data32, // 32-bit data to transmit
output Tx_Done32, // 32位发送完成标志 output Tx_Done32, // 32-bit transmit done flag
output uart_tx, // 物理引脚TX output uart_tx, // Physical TX pin
// 32位接收接口 // 32-bit Receive Interface
input uart_rx, // 物理引脚RX input uart_rx, // Physical RX pin
output reg Rx_Done32, // 32位接收完成标志 output reg Rx_Done32, // 32-bit receive done flag
output reg [31:0] Rx_Data32 // 接收到的32位数据 output reg [31:0] Rx_Data32 // 32-bit received data
); );
// --- 内部连线 --- // --- Internal Wires ---
wire byte_tx_go; wire byte_tx_go;
wire [7:0] byte_tx_data; wire [7:0] byte_tx_data;
wire byte_tx_done; wire byte_tx_done;
@ -37,7 +37,7 @@ module uart_top_32bit #(
wire [7:0] byte_rx_data; wire [7:0] byte_rx_data;
// ============================================================ // ============================================================
// 1. 发送逻辑控制 (32-bit to 4x8-bit) // 1. Transmit Control Logic (32-bit to 4x8-bit)
// ============================================================ // ============================================================
reg [3:0] tx_state; reg [3:0] tx_state;
reg [31:0] tx_data_buffer; reg [31:0] tx_data_buffer;
@ -54,26 +54,26 @@ module uart_top_32bit #(
tx_data_buffer <= 0; tx_data_buffer <= 0;
end else begin end else begin
case (tx_state) case (tx_state)
0: begin // 等待发送触发 0: begin // Wait for transmit trigger
if (Send_Go32) begin if (Send_Go32) begin
tx_data_buffer <= Tx_Data32; tx_data_buffer <= Tx_Data32;
tx_state <= 1; tx_state <= 1;
end end
end end
1, 2, 3, 4: begin // 依次发送字节0, 1, 2, 3 1, 2, 3, 4: begin // Send byte 0, 1, 2, 3 sequentially
byte_tx_data_reg <= tx_data_buffer[31:24]; // 优先发高位置(大端) byte_tx_data_reg <= tx_data_buffer[31:24]; // Send high byte first (Big-endian)
byte_tx_go_reg <= 1; byte_tx_go_reg <= 1;
tx_state <= tx_state + 4; // 跳转到等待状态 (利用加法偏移) tx_state <= tx_state + 4; // Jump to wait state
end end
// 状态 5, 6, 7, 8 用于等待 byte_tx_done // States 5, 6, 7, 8: Wait for byte_tx_done
5, 6, 7, 8: begin 5, 6, 7, 8: begin
byte_tx_go_reg <= 0; byte_tx_go_reg <= 0;
if (byte_tx_done) begin if (byte_tx_done) begin
tx_data_buffer <= tx_data_buffer << 8; // 移位，准备下一字节 tx_data_buffer <= tx_data_buffer << 8; // Shift for next byte
if (tx_state == 8) tx_state <= 0; // 发完4个 if (tx_state == 8) tx_state <= 0; // 4 bytes sent
else tx_state <= tx_state - 3; // 回到下一个发送状态 else tx_state <= tx_state - 3; // Return to next send state
end end
end end
endcase endcase
@ -83,7 +83,7 @@ module uart_top_32bit #(
assign Tx_Done32 = (tx_state == 8 && byte_tx_done); assign Tx_Done32 = (tx_state == 8 && byte_tx_done);
// ============================================================ // ============================================================
// 2. 接收逻辑控制 (4x8-bit to 32-bit) // 2. Receive Control Logic (4x8-bit to 32-bit)
// ============================================================ // ============================================================
reg [1:0] rx_cnt; reg [1:0] rx_cnt;
reg [31:0] rx_data_buffer; reg [31:0] rx_data_buffer;
@ -97,7 +97,7 @@ module uart_top_32bit #(
end else begin end else begin
rx_done32_reg <= 0; rx_done32_reg <= 0;
if (byte_rx_done) begin if (byte_rx_done) begin
// 拼接数据 (大端模式) // Concatenate data (Big-endian mode)
case(rx_cnt) case(rx_cnt)
0: rx_data_buffer[31:24] <= byte_rx_data; 0: rx_data_buffer[31:24] <= byte_rx_data;
1: rx_data_buffer[23:16] <= byte_rx_data; 1: rx_data_buffer[23:16] <= byte_rx_data;
@ -116,7 +116,7 @@ module uart_top_32bit #(
end end
always @(posedge Clk or Reset_n) begin always @(posedge Clk or negedge Reset_n) begin
if(!Reset_n) begin if(!Reset_n) begin
Rx_Data32 <= 1'b0; Rx_Data32 <= 1'b0;
Rx_Done32 <= 1'b0; Rx_Done32 <= 1'b0;
@ -132,10 +132,10 @@ module uart_top_32bit #(
end end
// ============================================================ // ============================================================
// 3. 模块实例化 // 3. Module Instantiation
// ============================================================ // ============================================================
// 实例化发送字节模块 // Instantiate byte transmit module
uart_byte_tx #( uart_byte_tx #(
.BAUD(BAUD), .BAUD(BAUD),
.CLOCK_FREQ(CLOCK_FREQ) .CLOCK_FREQ(CLOCK_FREQ)
@ -148,7 +148,7 @@ module uart_top_32bit #(
.Tx_Done(byte_tx_done) .Tx_Done(byte_tx_done)
); );
// 实例化接收字节模块 // Instantiate byte receive module
uart_byte_rx #( uart_byte_rx #(
.BAUD(BAUD), .BAUD(BAUD),
.CLOCK_FREQ(CLOCK_FREQ) .CLOCK_FREQ(CLOCK_FREQ)
@ -160,4 +160,4 @@ module uart_top_32bit #(
.Rx_Data(byte_rx_data) .Rx_Data(byte_rx_data)
); );
endmodule endmodule

74
sim/therm_chip_top/Makefile Normal file
View File

@ -0,0 +1,74 @@
WAVE ?= 0
SIM = RTL
folder = simv
ifeq ($(WAVE),1)
WAVE_OPTS = -debug_access+all -debug_region+cell+encrypt -P $(NOVAS_HOME)/share/PLI/VCS/linux64/novas_new_dumper.tab $(NOVAS_HOME)/share/PLI/VCS/linux64/pli.a +define+DUMP_FSDB
WAVE_SIM_OPTS = -fsdbDumpfile=sim.fsdb
else
WAVE_OPTS = -debug_access+pp
endif
ifeq ($(SIM),PostPr)
VCS = vcs -full64 -sverilog -Mupdate +lint=TFIPC-L +v2k +warn=noSDFCOM_IWSBA,noNTCDNC -notice +mindelays +tchk+edge+warn +neg_tchk -negdelay +overlap +sdfverbose -sdfretain +optconfigfile+notimingcheck.cfg -override_timescale=1ns/1ps -debug_access+all $(WAVE_OPTS) -lca -q -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb |tee
else
VCS = vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k $(WAVE_OPTS) -lca -q -timescale=1ns/1ps +nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb
endif
ifeq ($(SIM),PostPr)
post_dir = ./data_PostPr
else
post_dir = ./data_PostSyn
endif
ifeq ($(SIM),PostSyn)
FileList = filelist_syn.f
else
ifeq ($(SIM),PostPr)
FileList = filelist_pr.f
else
FileList = filelist_vlg.f
endif
endif
SIMV = ./simv sync:busywait $(WAVE_SIM_OPTS) -l |tee sim.log
all:comp run dbg
rsim: comp run
comp:
# ${VCS} -f $(FileList) +incdir+./../../rtl/define +incdir+./../../rtl/qubitmcu +incdir+./../../model
${VCS} -f $(FileList)
run:
${SIMV}
dbg:
verdi -sverilog -f $(FileList) -top TB -ssf *.fsdb -nologo &
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *fsdb* *.dat *.daidir *.vdb *~
compare:
./compare_files.csh ${post_dir} ./data_RTL ./compare.txt
regress:
./regress.csh $(SIM)
rmwork:
rm -rf ./work*
rmdata:
rm -rf ./data*
cov:
verdi -cov -covdir coverage/merged.vdb &
cov_d:
dve -full64 -covdir coverage/*.vdb &
merge:
urg -full64 -dbname coverage/merged.vdb -flex_merge union -dir coverage/simv.vdb -parallel -maxjobs 64&
merge_i:
urg -full64 -flex_merge union -dir coverage/merged.vdb -dir coverage/$(folder) -dbname coverage/merged.vdb -parallel -maxjobs 64&

224
sim/therm_chip_top/TB.sv Normal file
View File

@ -0,0 +1,224 @@
`timescale 1ns / 1ps
module TB();
// ==========================================
// Parameters & Signal Definitions
// ==========================================
parameter CLK_PERIOD = 20; // 50MHz
parameter BAUD = 115200;
localparam BIT_TIME = 1_000_000_000 / BAUD;
reg clk;
reg rst_n;
reg uart_rx; // DUT RX
wire uart_tx; // DUT TX
reg sig_in;
// Clock Generation
initial clk = 0;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$fsdbDumpfile("wave.fsdb");
$fsdbDumpvars();
end
// ==========================================
// DUT Instantiation
// ==========================================
digital_top u_digital_top(
.clk (clk),
.rst_n (rst_n),
.uart_rx (uart_rx),
.uart_tx (uart_tx),
.sig_in (sig_in)
);
// // ==========================================
// // TX Driver: Read from case.txt
// // ==========================================
// initial begin
// int file_h;
// int status;
// logic [63:0] val;
// // Initialize signals
// rst_n = 0;
// uart_rx = 1;
// #(CLK_PERIOD * 10);
// rst_n = 1;
// file_h = $fopen("case.txt", "r");
// if (!file_h) begin
// $display("[TX ERROR] Cannot open case.txt");
// $finish;
// end
// $display("[TX] Starting transmission...");
// while (!$feof(file_h)) begin
// // Read hex data per line
// status = $fscanf(file_h, "%h\n", val);
// if (status == 1) begin
// if (val > 64'hFFFF_FFFF) begin
// $display("[%t] TX CMD: %h", $time, val);
// send_data(val, 64);
// end else begin
// $display("[%t] TX DATA: %h", $time, val[31:0]);
// send_data(val[31:0], 32);
// end
// #(BIT_TIME * 5); // Frame gap
// }
// end
// $fclose(file_h);
// $display("[TX] All cases sent.");
// // Wait for RX return data
// #(BIT_TIME * 500);
// $display("[SIM] Simulation finished.");
// $finish;
// end
// ==========================================
// RX Monitor: Save to rx_data.txt
// ==========================================
int rx_file_h;
initial begin
logic [7:0] rx_byte;
rx_file_h = $fopen("rx_data.txt", "w");
if (!rx_file_h) begin
$display("[RX ERROR] Cannot create rx_data.txt");
$finish;
end
forever begin
logic [31:0] packet_word; // 32-bit data packet
logic [7:0] rx_byte;
// Collect 4 bytes to form 32-bit data
for (int byte_idx = 0; byte_idx < 4; byte_idx++) begin
// 1. Wait for start bit (falling edge)
@(negedge uart_tx);
// 2. Skip start bit, sample at center point
#(BIT_TIME / 2);
#(BIT_TIME);
// Read 8 data bits
for (int i = 0; i < 8; i++) begin
rx_byte[i] = uart_tx;
#(BIT_TIME);
end
// Combine to 32-bit (little-endian)
packet_word[24 - 8*byte_idx +: 8] = rx_byte;
$display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte);
// Wait for end of stop bit
if (byte_idx < 3) begin
#(BIT_TIME / 2);
end
end
// Write to file (one 32-bit data per line)
$fdisplay(rx_file_h, "%08h", packet_word);
$display("[%t] Packet (32-bit): 0x%08h", $time, packet_word);
// Wait for end of last stop bit
#(BIT_TIME / 2);
end
end
final begin
if (rx_file_h) begin
$fclose(rx_file_h);
$display("[RX] File closed at %t",$time);
end
end
// --- Pulse Generation Task ---
// freq_khz: Target frequency (kHz)
// duration_ms: Test duration (ms)
task automatic gen_pulses(input int freq_khz, input int duration_ms);
int half_period_ns;
longint end_time_ns;
begin
if (freq_khz <= 0) begin
sig_in = 0;
#(duration_ms * 1000000);
end else begin
half_period_ns = 500000 / freq_khz;
end_time_ns = $time + (longint'(duration_ms) * 1000000);
$display("[%0t] Start generating signal: %0d kHz", $time, freq_khz);
while ($time < end_time_ns) begin
sig_in = 1;
#(half_period_ns);
sig_in = 0;
#(half_period_ns);
end
end
end
endtask
// ==========================================
// Task: Send one byte (Serial TX)
// ==========================================
task automatic send_byte(input [7:0] data);
begin
uart_rx = 0; // Start bit
#(BIT_TIME);
for (int i = 0; i < 8; i++) begin
uart_rx = data[i]; // LSB First
#(BIT_TIME);
end
uart_rx = 1; // Stop bit
#(BIT_TIME);
end
endtask
// Task: Send 32/64 bit data
task automatic send_data(input [63:0] data, input int len_bits);
int bytes = len_bits / 8;
for (int i = bytes - 1; i >= 0; i--) begin // Send from highest byte
send_byte(data[i*8 +: 8]);
end
endtask
initial begin
// 1. Initialization
rst_n = 0; uart_rx = 1; sig_in = 0;
#(CLK_PERIOD * 20);
rst_n = 1;
#(CLK_PERIOD * 100);
$display("------- Step 1: Configure Thermometer Regs -------");
send_data(64'h80000004_00000004,64);
send_data(64'h80000008_00000004,64);
send_data(64'h8000000c_00000004,64);
send_data(64'h80000010_00000004,64);
send_data(64'h80000014_00000004,64);
$display("------- Step 2: Running Concurrent Tasks -------");
fork
// Process A: Generate input pulses (simulate temperature change)
begin
gen_pulses(400, 10); // 100kHz for 10ms
end
// Process B: Insert read command during reporting
begin
#(2_000000); // Wait for first report packet
$display("[%t] TX: Sending Read Request during active reporting...", $time);
send_data(64'h80000014_00000004,64);
send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32);
send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32);
#30000;
send_data(64'h80000014_00000004,64);
end
join
#(BIT_TIME * 500);
$display("Test Done.");
$finish;
end
endmodule

20
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Command: vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k -debug_access+pp -lca -q -timescale=1ns/1ps \
+nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb \
-f filelist_vlg.f
Warning-[LCA_FEATURES_ENABLED] Usage warning
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS/VCS-MX Release Notes
VCS Coverage Metrics Release O-2018.09-SP2_Full64 Copyright (c) 1991-2018 by Synopsys Inc.
Note-[VCS_PARAL] Parallel code-gen enabled
VCS is running with parallel code generation(-j)...
6 modules and 0 UDP read.
make[1]: Entering directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \
../simv up to date
make[1]: Leaving directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \

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Instrument
cond 3
line 3
fsm 65539
tgl 8
assign 0
obc 0
path 0
branch 3
Count 0
Glitch -1
cm_tglmda 0
cm_tglstructarr 0
cm_tglcount 0
cm_hier 0
cm_assert_hier 0

0
sim/therm_chip_top/coverage/simv.vdb/.mode64 Normal file
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1
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O-2018.09-SP2

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sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt Normal file
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TB.u_digital_top.u_uart_ctrl.S_IDLE0
TB.u_digital_top.u_uart_ctrl.S_PARSE2
TB.u_digital_top.u_uart_ctrl.S_RD_DATA4
TB.u_digital_top.u_uart_ctrl.S_REPORT6
TB.u_digital_top.u_uart_ctrl.S_RX_CMD_L1
TB.u_digital_top.u_uart_ctrl.S_WAIT_RD3
TB.u_digital_top.u_uart_ctrl.S_WR_DATA5

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<?xml version="1.0"?>
<!DOCTYPE cov SYSTEM "ucdb_srcinfo.dtd">
<srcinfo name="/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top" >
<ucapi_version major_ver="13" minor_ver="1" patch_str="O-2018.09-SP2" />
<fileinfo name="../../rtl/systemregfile/my_systemregfile.v" id="0" />
<fileinfo name="../../rtl/systemregfile/sirv_gnrl_dffs.v" id="1" />
<fileinfo name="../../rtl/digital_top.v" id="2" />
<fileinfo name="../../rtl/uart/uart_byte_rx.v" id="3" />
<fileinfo name="../../rtl/uart/uart_ctrl_sysreg.v" id="4" />
<fileinfo name="../../rtl/uart/uart_top_32bit.v" id="5" />
<fileinfo name="../../rtl/uart/uart_byte_tx.v" id="6" />
<fileinfo name="../../rtl/therm/digital_thermometer.v" id="7" />
<fileinfo name="../../rtl/therm/pulse_cnt.v" id="8" />
<fileinfo name="./TB.sv" id="9" />
</srcinfo>

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// Synopsys, Inc.
// User: shbyang
// Date: Tue Apr 7 09:38:18 2026
// ==================================================================================================
// This config file prototype is produced from the last run using the complete list of extracted fsms.
// Please note that by providing your own description of the module you are enforcing what will be
// extracted for that module.
// Copy this file to your source directory and edit it as described below,
// then pass the file to VCS using the -cm_fsmcfg command line option.
// FSMs will be extracted normally for any module not mentioned in this file
// ==================================================================================================
// 1. For every module that you want to specify yourself, use:
// MODULE==name
// -----------------------------------------------------
// The following options are defining the behavior on the module level.
// -----------------------------------------------------
// 1.1 You can control what fsms should be used within this module:
// FSMS=AUTO
// this means that you want VCS to automatically extract all
// detectable FSMs from this module.
// -----------------------------------------------------
// FSMS=EXCLUDE
// this means that you want all fsms except the ones from the list that follows
// if the list is empty, all fsms will be extracted for this module
// -----------------------------------------------------
// FSMS=RESTRICT
// this means that you want only the fsms from the list that follows
// if the list is empty, no fsms will be extracted for this module
// -----------------------------------------------------
// If none of these options are specified, the program will assume FSMS=RESTRICT
// -----------------------------------------------------
// 1.2 You can specify that the state with the minimal value should be used as a
// start state for all sequences in every fsm in the module.
// FSMS=START_STATE_DFLT
// For any particular fsm you can overwrite this behavior inside its description.
// -----------------------------------------------------
// 2. Each fsm description in the list of fsms should be specified as follows:
// 2.1 provide the current state variable declaration:
// CURRENT= name of the current state variable
// -----------------------------------------------------
// 2.2 if next state variable is different from the current state provide:
// NEXT= next state variable
// if you don't use NEXT=, the program will assume that CURRENT and NEXT are the same
// -----------------------------------------------------
// 2.3 if you want to provide the restrictive the list of states, provide:
// STATES= s0,s1 etc. where s0 is either a name or a value of the state
// if you don't use STATES=, the program will assume that you want to use all states
// -----------------------------------------------------
// 2.4 if you want to ignore some states, specify them in the following list:
// STATES_X= s0,s1, etc.
// -----------------------------------------------------
// 2.5 if you want to mark, that some states should never be reached, specify them as a list:
// STATES_NEVER= s0,s1, etc.
// -----------------------------------------------------
// 2.6 similar to the STATES, if you want to provide the restrictive the list of transitions, specify:
// TRANSITIONS= s0->s1,s1->s2, etc.
// -----------------------------------------------------
// 2.7 similar to the STATES_X, if you want to ignore some transitions, specify them in the following list:
// TRANSITIONS_X= s0->s1,s1->s2, etc.
// -----------------------------------------------------
// 2.8 similar to the STATES_NEVER,if you want to mark, that some transitions should never occur,
// specify them as a list:
// TRANSITIONS_NEVER= s0->s1,s1->s2, etc.
// -----------------------------------------------------
// 2.9 if you want to specify the start state use:
// START_STATE= s0
// -----------------------------------------------------
// Please note:
// - that a state in every list can be specified either by name or by value.
// - in specifying the transitions you can use * in order to refer to 'any' state.
// ==================================================================================================
// Uncomment and modify the following 2 line to override default FSM sequence limits for all FSMs in the design.
//SEQ_NUMBER_MAX=10000
//SEQ_LENGTH_MAX=32
MODULE=uart_ctrl_sysreg
CURRENT=state
NEXT=state
STATES=S_IDLE,S_PARSE,S_RD_DATA,S_REPORT,S_RX_CMD_L,S_WAIT_RD,S_WR_DATA,'h0
TRANSITIONS=S_IDLE->'h0,
S_IDLE->S_REPORT,
S_IDLE->S_RX_CMD_L,
S_PARSE->'h0,
S_PARSE->S_WAIT_RD,
S_PARSE->S_WR_DATA,
S_RD_DATA->'h0,
S_RD_DATA->S_IDLE,
S_REPORT->'h0,
S_REPORT->S_IDLE,
S_RX_CMD_L->'h0,
S_RX_CMD_L->S_PARSE,
S_WAIT_RD->'h0,
S_WAIT_RD->S_RD_DATA,
S_WR_DATA->'h0,
S_WR_DATA->S_IDLE,
'h0->S_IDLE

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<?xml version="1.0"?>
<!DOCTYPE cov SYSTEM "ucdb_fsm.dtd">
<fsm count="0" noconst="0" >
<ucapi_version major_ver="13" minor_ver="1" patch_str="O-2018.09-SP2" />
<fsmdef file="4" name="uart_ctrl_sysreg" lib="" parameterized="1" >
<fsmshape >
<fsmfsm name="state" id="0" width="3" line="76" chksum="3416069012" >
<state name="S_IDLE" value="parameterized" id="0" flag="L" line="120" />
<state name="S_PARSE" value="parameterized" id="1" flag="L" line="99" />
<state name="S_RD_DATA" value="parameterized" id="2" flag="L" line="115" />
<state name="S_REPORT" value="parameterized" id="3" flag="L" line="93" />
<state name="S_RX_CMD_L" value="parameterized" id="4" flag="L" line="90" />
<state name="S_WAIT_RD" value="parameterized" id="5" flag="L" line="107" />
<state name="S_WR_DATA" value="parameterized" id="6" flag="L" line="110" />
<state name="&apos;h0" value="0" id="7" flag="L" line="76" />
<transition fromid="0" toid="7" flag="L" line="76" />
<transition fromid="0" toid="3" flag="L" line="93" />
<transition fromid="0" toid="4" flag="L" line="90" />
<transition fromid="1" toid="7" flag="L" line="76" />
<transition fromid="1" toid="5" flag="L" line="107" />
<transition fromid="1" toid="6" flag="L" line="110" />
<transition fromid="2" toid="7" flag="L" line="76" />
<transition fromid="2" toid="0" flag="L" line="120" />
<transition fromid="3" toid="7" flag="L" line="76" />
<transition fromid="3" toid="0" flag="L" line="139" />
<transition fromid="4" toid="7" flag="L" line="76" />
<transition fromid="4" toid="1" flag="L" line="99" />
<transition fromid="5" toid="7" flag="L" line="76" />
<transition fromid="5" toid="2" flag="L" line="115" />
<transition fromid="6" toid="7" flag="L" line="76" />
<transition fromid="6" toid="0" flag="L" line="132" />
<transition fromid="7" toid="0" flag="L" line="142" />
</fsmfsm>
</fsmshape>
<fsminst name="TB.u_digital_top.u_uart_ctrl" />
</fsmdef>
<metric_sig chksum="65346B85311F2B356F944DB142EE5F5060E09C14" />
</fsm>

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# Makefile generated by VCS to build your model
# This file may be modified; VCS will not overwrite it unless -Mupdate is used
# define default verilog source directory
VSRC=..
# Override TARGET_ARCH
TARGET_ARCH=
# Choose name of executable
PRODUCTBASE=$(VSRC)/simv
PRODUCT=$(PRODUCTBASE)
# Product timestamp file. If product is newer than this one,
# we will also re-link the product.
PRODUCT_TIMESTAMP=product_timestamp
# Path to runtime library
DEPLIBS=
VCSUCLI=-lvcsucli
RUNTIME=-lvcsnew -lsimprofile -lreader_common /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libBA.a -luclinative /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_tls.o $(DEPLIBS)
VCS_SAVE_RESTORE_OBJ=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o
# Select your favorite compiler
# Linux:
VCS_CC=gcc
# Internal CC for gen_c flow:
CC_CG=gcc
# User overrode default CC:
VCS_CC=gcc
# Loader
LD=g++
# Strip Flags for target product
STRIPFLAGS=
PRE_LDFLAGS= # Loader Flags
LDFLAGS= -rdynamic -Wl,-rpath=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib -L/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib
# Picarchive Flags
PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir
# C run time startup
CRT0=
# C run time startup
CRTN=
# Machine specific libraries
SYSLIBS=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
# Default defines
SHELL=/bin/sh
VCSTMPSPECARG=
VCSTMPSPECENV=
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
#and you are using gcc, uncomment the next line
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
TMPSPECARG=$(VCSTMPSPECARG)
TMPSPECENV=$(VCSTMPSPECENV)
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
# C flags for compilation
CFLAGS=-w -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include
CFLAGS_O0=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O0 -fno-strict-aliasing
CFLAGS_CG=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O -fno-strict-aliasing
LD_PARTIAL_LOADER=ld
# Partial linking
LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o
ASFLAGS=
LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs
# Note: if make gives you errors about include, either get gmake, or
# replace the following line with the contents of the file filelist,
# EACH TIME IT CHANGES
# included file defines OBJS, and is automatically generated by vcs
include filelist
OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS)
product : $(PRODUCT_TIMESTAMP)
@echo $(PRODUCT) up to date
objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS)
clean :
rm -f $(VCS_OBJS) $(CU_OBJS)
clobber : clean
rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP)
picclean :
@rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
@rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null
product_clean_order :
@$(MAKE) -f Makefile --no-print-directory picclean
@$(MAKE) -f Makefile --no-print-directory product_order
product_order : $(PRODUCT)
$(PRODUCT_TIMESTAMP) : product_clean_order
@-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi
@$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN)
@rm -f csrc[0-9]*.o
@touch $(PRODUCT_TIMESTAMP)
@-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi
$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvcsnew.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsimprofile.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libreader_common.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libBA.a /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libuclinative.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_tls.o /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ)
@touch $(PRODUCT)

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# Makefile generated by VCS to build rmapats.so for your model
VSRC=..
# Override TARGET_ARCH
TARGET_ARCH=
# Select your favorite compiler
# Linux:
VCS_CC=gcc
# Internal CC for gen_c flow:
CC_CG=gcc
# User overrode default CC:
VCS_CC=gcc
# Loader
LD=g++
# Loader Flags
LDFLAGS=
# Default defines
SHELL=/bin/sh
VCSTMPSPECARG=
VCSTMPSPECENV=
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
#and you are using gcc, uncomment the next line
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
TMPSPECARG=$(VCSTMPSPECARG)
TMPSPECENV=$(VCSTMPSPECENV)
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
# C flags for compilation
CFLAGS=-w -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include
CFLAGS_CG=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O -fno-strict-aliasing
ASFLAGS=
LIBS=
include filelist.hsopt
rmapats.so: $(HSOPT_OBJS)
@$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS)

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.//../simv.daidir//_131020_archive_1.so

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.//../simv.daidir//_131039_archive_1.so

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.//../simv.daidir//_131040_archive_1.so

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#ifndef _GNU_SOURCE
#define _GNU_SOURCE
#endif
#include <stdio.h>
#include <dlfcn.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void* VCS_dlsymLookup(const char *);
extern void vcsMsgReportNoSource1(const char *, const char*);
/* PLI routine: $fsdbDumpvars:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars
#define __VCS_PLI_STUB_novas_call_fsdbDumpvars
extern void novas_call_fsdbDumpvars(int data, int reason);
#pragma weak novas_call_fsdbDumpvars
void novas_call_fsdbDumpvars(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars;
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */
/* PLI routine: $fsdbDumpvars:misc */
#ifndef __VCS_PLI_STUB_novas_misc
#define __VCS_PLI_STUB_novas_misc
extern void novas_misc(int data, int reason, int iparam );
#pragma weak novas_misc
void novas_misc(int data, int reason, int iparam )
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason, iparam );
}
}
void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc;
#endif /* __VCS_PLI_STUB_novas_misc */
/* PLI routine: $fsdbDumpvarsByFile:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
extern void novas_call_fsdbDumpvarsByFile(int data, int reason);
#pragma weak novas_call_fsdbDumpvarsByFile
void novas_call_fsdbDumpvarsByFile(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile;
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */
/* PLI routine: $fsdbAddRuntimeSignal:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
extern void novas_call_fsdbAddRuntimeSignal(int data, int reason);
#pragma weak novas_call_fsdbAddRuntimeSignal
void novas_call_fsdbAddRuntimeSignal(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal;
#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */
/* PLI routine: $sps_create_transaction_stream:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
extern void novas_call_sps_create_transaction_stream(int data, int reason);
#pragma weak novas_call_sps_create_transaction_stream
void novas_call_sps_create_transaction_stream(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream;
#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */
/* PLI routine: $sps_begin_transaction:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction
#define __VCS_PLI_STUB_novas_call_sps_begin_transaction
extern void novas_call_sps_begin_transaction(int data, int reason);
#pragma weak novas_call_sps_begin_transaction
void novas_call_sps_begin_transaction(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction;
#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */
/* PLI routine: $sps_end_transaction:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction
#define __VCS_PLI_STUB_novas_call_sps_end_transaction
extern void novas_call_sps_end_transaction(int data, int reason);
#pragma weak novas_call_sps_end_transaction
void novas_call_sps_end_transaction(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction;
#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */
/* PLI routine: $sps_free_transaction:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction
#define __VCS_PLI_STUB_novas_call_sps_free_transaction
extern void novas_call_sps_free_transaction(int data, int reason);
#pragma weak novas_call_sps_free_transaction
void novas_call_sps_free_transaction(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction;
#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */
/* PLI routine: $sps_add_attribute:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute
#define __VCS_PLI_STUB_novas_call_sps_add_attribute
extern void novas_call_sps_add_attribute(int data, int reason);
#pragma weak novas_call_sps_add_attribute
void novas_call_sps_add_attribute(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute;
#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */
/* PLI routine: $sps_update_label:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_update_label
#define __VCS_PLI_STUB_novas_call_sps_update_label
extern void novas_call_sps_update_label(int data, int reason);
#pragma weak novas_call_sps_update_label
void novas_call_sps_update_label(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label;
#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */
/* PLI routine: $sps_add_relation:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation
#define __VCS_PLI_STUB_novas_call_sps_add_relation
extern void novas_call_sps_add_relation(int data, int reason);
#pragma weak novas_call_sps_add_relation
void novas_call_sps_add_relation(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation;
#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */
/* PLI routine: $fsdbWhatif:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif
#define __VCS_PLI_STUB_novas_call_fsdbWhatif
extern void novas_call_fsdbWhatif(int data, int reason);
#pragma weak novas_call_fsdbWhatif
void novas_call_fsdbWhatif(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif;
#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */
/* PLI routine: $paa_init:call */
#ifndef __VCS_PLI_STUB_novas_call_paa_init
#define __VCS_PLI_STUB_novas_call_paa_init
extern void novas_call_paa_init(int data, int reason);
#pragma weak novas_call_paa_init
void novas_call_paa_init(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init");
}
}
void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init;
#endif /* __VCS_PLI_STUB_novas_call_paa_init */
/* PLI routine: $paa_sync:call */
#ifndef __VCS_PLI_STUB_novas_call_paa_sync
#define __VCS_PLI_STUB_novas_call_paa_sync
extern void novas_call_paa_sync(int data, int reason);
#pragma weak novas_call_paa_sync
void novas_call_paa_sync(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync");
}
}
void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync;
#endif /* __VCS_PLI_STUB_novas_call_paa_sync */
/* PLI routine: $fsdbDumpClassMethod:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
extern void novas_call_fsdbDumpClassMethod(int data, int reason);
#pragma weak novas_call_fsdbDumpClassMethod
void novas_call_fsdbDumpClassMethod(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod;
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */
/* PLI routine: $fsdbSuppressClassMethod:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
extern void novas_call_fsdbSuppressClassMethod(int data, int reason);
#pragma weak novas_call_fsdbSuppressClassMethod
void novas_call_fsdbSuppressClassMethod(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod;
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */
/* PLI routine: $fsdbSuppressClassProp:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
extern void novas_call_fsdbSuppressClassProp(int data, int reason);
#pragma weak novas_call_fsdbSuppressClassProp
void novas_call_fsdbSuppressClassProp(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp;
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */
/* PLI routine: $fsdbDumpMDAByFile:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
extern void novas_call_fsdbDumpMDAByFile(int data, int reason);
#pragma weak novas_call_fsdbDumpMDAByFile
void novas_call_fsdbDumpMDAByFile(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile;
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */
/* PLI routine: $fsdbTrans_create_stream_begin:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason);
#pragma weak novas_call_fsdbEvent_create_stream_begin
void novas_call_fsdbEvent_create_stream_begin(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */
/* PLI routine: $fsdbTrans_define_attribute:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason);
#pragma weak novas_call_fsdbEvent_add_stream_attribute
void novas_call_fsdbEvent_add_stream_attribute(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */
/* PLI routine: $fsdbTrans_create_stream_end:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
extern void novas_call_fsdbEvent_create_stream_end(int data, int reason);
#pragma weak novas_call_fsdbEvent_create_stream_end
void novas_call_fsdbEvent_create_stream_end(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */
/* PLI routine: $fsdbTrans_begin:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin
#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin
extern void novas_call_fsdbEvent_begin(int data, int reason);
#pragma weak novas_call_fsdbEvent_begin
void novas_call_fsdbEvent_begin(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */
/* PLI routine: $fsdbTrans_set_label:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
extern void novas_call_fsdbEvent_set_label(int data, int reason);
#pragma weak novas_call_fsdbEvent_set_label
void novas_call_fsdbEvent_set_label(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */
/* PLI routine: $fsdbTrans_add_attribute:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
extern void novas_call_fsdbEvent_add_attribute(int data, int reason);
#pragma weak novas_call_fsdbEvent_add_attribute
void novas_call_fsdbEvent_add_attribute(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */
/* PLI routine: $fsdbTrans_add_tag:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
extern void novas_call_fsdbEvent_add_tag(int data, int reason);
#pragma weak novas_call_fsdbEvent_add_tag
void novas_call_fsdbEvent_add_tag(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */
/* PLI routine: $fsdbTrans_end:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end
#define __VCS_PLI_STUB_novas_call_fsdbEvent_end
extern void novas_call_fsdbEvent_end(int data, int reason);
#pragma weak novas_call_fsdbEvent_end
void novas_call_fsdbEvent_end(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */
/* PLI routine: $fsdbTrans_add_relation:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
extern void novas_call_fsdbEvent_add_relation(int data, int reason);
#pragma weak novas_call_fsdbEvent_add_relation
void novas_call_fsdbEvent_add_relation(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */
/* PLI routine: $fsdbTrans_get_error_code:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
extern void novas_call_fsdbEvent_get_error_code(int data, int reason);
#pragma weak novas_call_fsdbEvent_get_error_code
void novas_call_fsdbEvent_get_error_code(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code;
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */
/* PLI routine: $fsdbTrans_add_stream_attribute:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason);
#pragma weak novas_call_fsdbTrans_add_stream_attribute
void novas_call_fsdbTrans_add_stream_attribute(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute;
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */
/* PLI routine: $fsdbTrans_add_scope_attribute:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason);
#pragma weak novas_call_fsdbTrans_add_scope_attribute
void novas_call_fsdbTrans_add_scope_attribute(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute;
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */
/* PLI routine: $sps_interactive:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_interactive
#define __VCS_PLI_STUB_novas_call_sps_interactive
extern void novas_call_sps_interactive(int data, int reason);
#pragma weak novas_call_sps_interactive
void novas_call_sps_interactive(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive;
#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */
/* PLI routine: $sps_test:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_test
#define __VCS_PLI_STUB_novas_call_sps_test
extern void novas_call_sps_test(int data, int reason);
#pragma weak novas_call_sps_test
void novas_call_sps_test(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test;
#endif /* __VCS_PLI_STUB_novas_call_sps_test */
/* PLI routine: $fsdbDumpClassObject:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
extern void novas_call_fsdbDumpClassObject(int data, int reason);
#pragma weak novas_call_fsdbDumpClassObject
void novas_call_fsdbDumpClassObject(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject;
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */
/* PLI routine: $fsdbDumpClassObjectByFile:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason);
#pragma weak novas_call_fsdbDumpClassObjectByFile
void novas_call_fsdbDumpClassObjectByFile(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile;
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */
/* PLI routine: $ridbDump:call */
#ifndef __VCS_PLI_STUB_novas_call_ridbDump
#define __VCS_PLI_STUB_novas_call_ridbDump
extern void novas_call_ridbDump(int data, int reason);
#pragma weak novas_call_ridbDump
void novas_call_ridbDump(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump");
}
}
void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump;
#endif /* __VCS_PLI_STUB_novas_call_ridbDump */
/* PLI routine: $sps_flush_file:call */
#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file
#define __VCS_PLI_STUB_novas_call_sps_flush_file
extern void novas_call_sps_flush_file(int data, int reason);
#pragma weak novas_call_sps_flush_file
void novas_call_sps_flush_file(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file");
}
}
void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file;
#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */
/* PLI routine: $fsdbDumpSingle:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle
#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle
extern void novas_call_fsdbDumpSingle(int data, int reason);
#pragma weak novas_call_fsdbDumpSingle
void novas_call_fsdbDumpSingle(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle;
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */
/* PLI routine: $fsdbDumpIO:call */
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO
#define __VCS_PLI_STUB_novas_call_fsdbDumpIO
extern void novas_call_fsdbDumpIO(int data, int reason);
#pragma weak novas_call_fsdbDumpIO
void novas_call_fsdbDumpIO(int data, int reason)
{
static int _vcs_pli_stub_initialized_ = 0;
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
if (!_vcs_pli_stub_initialized_) {
_vcs_pli_stub_initialized_ = 1;
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO");
if (_vcs_pli_fp_ == NULL) {
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO");
}
}
if (_vcs_pli_fp_) {
_vcs_pli_fp_(data, reason);
} else {
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO");
}
}
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO;
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */
#ifdef __cplusplus
}
#endif

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"ru_stime_sec": 0.0,
"ru_minflt": 0,
"ru_nivcsw": 0,
"ru_majflt": 0,
"ru_nvcsw": 0
},
"cpu_cycles_end": 4026985004857588,
"peak_mem_kb": 294580
}
}

116
sim/therm_chip_top/csrc/cgproc.131040.json Normal file
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@ -0,0 +1,116 @@
{
"reusePaths": {},
"Modules": {
"std": {
"start_perf": [
0.44302701950073242,
0.001,
0.0,
285836,
285836,
1775525898.9101679,
4026984766925290
],
"nQuads": 224,
"child_modules": {},
"Compiled": "Yes",
"end_perf": [
0.45973801612854004,
0.0093670000000000003,
0.0083260000000000001,
289492,
289492,
4026984809951740,
8589934594,
0
],
"Compiled Times": 1,
"svclass": [
"$vcs_nba_dyn_obj",
385,
37,
2,
2,
0,
"sigprop$$",
385,
37,
2,
2,
0,
"process",
1645,
184,
8,
8,
0,
"event",
462,
36,
2,
2,
0,
"mailbox",
912,
107,
9,
9,
0,
"semaphore",
672,
71,
5,
5,
0
],
"nMops": 477,
"nRouts": 36
}
},
"CompUnits": {
"reYIK_d": {
"mod": "std",
"checksum": 0,
"out": "reYIK_d.o",
"bytes": 35776,
"mode": 4,
"text": 4811,
"cls": 4461,
"archive": "archive.0/_131040_archive_1.a"
}
},
"ObjArchives": [
{
"archive": "archive.0/_131040_archive_1.a",
"objects": [
[
"reYIK_d.o",
35776
]
],
"size": 35776
}
],
"stat": {
"ru_self_end": {
"ru_utime_sec": 0.0093670000000000003,
"ru_maxrss_kb": 33524,
"ru_stime_sec": 0.0086359999999999996,
"ru_minflt": 2444,
"ru_nivcsw": 0,
"ru_majflt": 0,
"ru_nvcsw": 1
},
"ru_childs_end": {
"ru_utime_sec": 0.0,
"ru_maxrss_kb": 0,
"ru_stime_sec": 0.0,
"ru_minflt": 0,
"ru_nivcsw": 0,
"ru_majflt": 0,
"ru_nvcsw": 0
},
"cpu_cycles_end": 4026984810673476,
"peak_mem_kb": 289496
}
}

32
sim/therm_chip_top/csrc/filelist Normal file
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@ -0,0 +1,32 @@
AR=ar
DOTLIBS=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libzerosoft_rt_stubs.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so
# This file is automatically generated by VCS. Any changes you make to it
# will be overwritten the next time VCS is run
VCS_LIBEXT=
XTRN_OBJS=
DPI_WRAPPER_OBJS =
DPI_STUB_OBJS =
# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS
include filelist.dpi
PLI_STUB_OBJS =
include filelist.pli
include filelist.hsopt
include filelist.cu
VCS_MISC_OBJS=
VCS_INCR_OBJS=
AUGDIR=
AUG_LDFLAGS=
SHARED_OBJ_SO=
VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS)

49
sim/therm_chip_top/csrc/filelist.cu Normal file
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PIC_LD=ld
ARCHIVE_OBJS=
ARCHIVE_OBJS += _131020_archive_1.so
_131020_archive_1.so : archive.0/_131020_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131020_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_131020_archive_1.so $@
ARCHIVE_OBJS += _131039_archive_1.so
_131039_archive_1.so : archive.0/_131039_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131039_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_131039_archive_1.so $@
ARCHIVE_OBJS += _131040_archive_1.so
_131040_archive_1.so : archive.0/_131040_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131040_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_131040_archive_1.so $@
O0_OBJS =
$(O0_OBJS) : %.o: %.c
$(CC_CG) $(CFLAGS_O0) -c -o $@ $<
%.o: %.c
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
CU_UDP_OBJS = \
CU_LVL_OBJS = \
SIM_l.o
MAIN_OBJS = \
objs/amcQw_d.o
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)

0
sim/therm_chip_top/csrc/filelist.dpi Normal file
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13
sim/therm_chip_top/csrc/filelist.hsopt Normal file
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@ -0,0 +1,13 @@
rmapats_mop.o: rmapats.m
@/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o
rmapats.o: rmapats.c
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c
rmapats%.o: rmapats%.c
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
rmar.o: rmar.c
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c
rmar%.o: rmar%.c
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
include filelist.hsopt.objs

1
sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs Normal file
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LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o

7
sim/therm_chip_top/csrc/filelist.hsopt.objs Normal file
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@ -0,0 +1,7 @@
HSOPT_OBJS +=rmapats_mop.o \
rmapats.o \
rmar.o rmar_nd.o
include filelist.hsopt.llvm2_0.objs
HSOPT_OBJS += $(LLVM_OBJS)

4
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PLI_STUB_OBJS += _vcs_pli_stub_.o
_vcs_pli_stub_.o: _vcs_pli_stub_.c
@$(CC) -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c
@strip -g _vcs_pli_stub_.o

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0
sim/therm_chip_top/csrc/import_dpic.h Normal file
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0
sim/therm_chip_top/csrc/product_timestamp Normal file
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43
sim/therm_chip_top/csrc/rmapats.c Normal file
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// file = 0; split type = patterns; threshold = 100000; total count = 0.
#include <stdio.h>
#include <stdlib.h>
#include <strings.h>
#include "rmapats.h"
void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685);
void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685)
{
U I1547;
U I1548;
U I1549;
struct futq * I1550;
struct dummyq_struct * pQ = I1289;
I1547 = ((U )vcs_clocks) + I685;
I1549 = I1547 & ((1 << fHashTableSize) - 1);
I1283->I727 = (EBLK *)(-1);
I1283->I731 = I1547;
if (I1547 < (U )vcs_clocks) {
I1548 = ((U *)&vcs_clocks)[1];
sched_millenium(pQ, I1283, I1548 + 1, I1547);
}
else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) {
I1283->I733 = (struct eblk *)peblkFutQ1Tail;
peblkFutQ1Tail->I727 = I1283;
peblkFutQ1Tail = I1283;
}
else if ((I1550 = pQ->I1190[I1549].I745)) {
I1283->I733 = (struct eblk *)I1550->I744;
I1550->I744->I727 = (RP )I1283;
I1550->I744 = (RmaEblk *)I1283;
}
else {
sched_hsopt(pQ, I1283, I1547);
}
}
#ifdef __cplusplus
extern "C" {
#endif
void SinitHsimPats(void);
#ifdef __cplusplus
}
#endif

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sim/therm_chip_top/csrc/rmapats.m Normal file
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sim/therm_chip_top/csrc/rmapats.o Normal file
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sim/therm_chip_top/csrc/rmapats_mop.o Normal file
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#include <stdio.h>
#include <stdlib.h>
#include "rmar0.h"
// stubs for Hil functions
#ifdef __cplusplus
extern "C" {
#endif
void __Hil__Static_Init_Func__(void) {}
#ifdef __cplusplus
}
#endif

18
sim/therm_chip_top/csrc/rmar.h Normal file
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#ifndef _RMAR1_H_
#define _RMAR1_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __DO_RMAHDR_
#include "rmar0.h"
#endif /*__DO_RMAHDR_*/
extern UP rmaFunctionRtlArray[];
#ifdef __cplusplus
}
#endif
#endif

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sim/therm_chip_top/csrc/rmar0.h Normal file
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#ifndef _RMAR0_H_
#define _RMAR0_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

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sim/therm_chip_top/csrc/vcspieces.incr Normal file
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10
sim/therm_chip_top/filelist_vlg.f Normal file
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@ -0,0 +1,10 @@
../../rtl/systemregfile/my_systemregfile.v
../../rtl/systemregfile/sirv_gnrl_dffs.v
../../rtl/digital_top.v
../../rtl/uart/uart_byte_rx.v
../../rtl/uart/uart_ctrl_sysreg.v
../../rtl/uart/uart_top_32bit.v
../../rtl/uart/uart_byte_tx.v
../../rtl/therm/digital_thermometer.v
../../rtl/therm/pulse_cnt.v
./TB.sv

338
sim/therm_chip_top/novas.conf Normal file
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sim/therm_chip_top/novas.rc Normal file
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347
sim/therm_chip_top/novas_dump.log Normal file
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@ -0,0 +1,347 @@
#######################################################################################
# log primitive debug message of FSDB dumping #
# This is for R&D to analyze when there are issues happening when FSDB dump #
#######################################################################################
ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status')
ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback')
ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback')
ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name')
ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info')
ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info')
ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info')
ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle')
ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle')
ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle')
ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent')
ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope')
ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled')
ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted')
ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue')
ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue')
ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue')
ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode')
ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info')
ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init')
ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk')
ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores')
ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode')
ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion')
ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp')
ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady')
ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback')
ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle')
ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst')
ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle')
ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig')
ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo')
ANF: msvRelease('./simv: undefined symbol: msvRelease')
ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc')
ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback')
ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback')
ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback')
ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue')
ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback')
ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe')
ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo')
ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo')
ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit')
ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync')
ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile')
ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback')
ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback')
ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback')
ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback')
ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus')
ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type')
ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key')
ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module')
ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope')
ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable')
ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id')
ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free')
ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope')
ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable')
ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi')
ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone')
ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free')
ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key')
ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare')
ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr')
ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback')
ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback')
ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force')
ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback')
ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback')
ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback')
ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data')
ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback')
ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr')
ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr')
ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted')
ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi')
ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id')
ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type')
ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback')
ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name')
ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt')
ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option')
ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode')
ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var')
ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis')
ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id')
ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr')
VCS compile option:
option[0]: ./simv
option[1]: sync:busywait
option[2]: -l
option[3]: /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1
option[4]: -Mcc=gcc
option[5]: -Mcplusplus=g++
option[6]: -Masflags=
option[7]: -Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include
option[8]: -Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include
option[9]: -Mldflags= -rdynamic
option[10]: -Mout=simv
option[11]: -Mamsrun=
option[12]: -Mvcsaceobjs=
option[13]: -Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so
option[14]: -Mexternalobj=
option[15]: -Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o
option[16]: -Mcrt0=
option[17]: -Mcrtn=
option[18]: -Mcsrc=
option[19]: -Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
option[20]: -l
option[21]: compile.log
option[22]: -full64
option[23]: -j8
option[24]: +lint=TFIPC-L
option[25]: +v2k
option[26]: -debug_access+pp
option[27]: +vpi
option[28]: +vcsd1
option[29]: +itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab
option[30]: -lca
option[31]: -q
option[32]: -timescale=1ns/1ps
option[33]: +nospecify
option[34]: -cm
option[35]: line+cond+fsm+tgl+branch
option[36]: -cm_dir
option[37]: ./coverage/simv.vdb
option[38]: -picarchive
option[39]: -P
option[40]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
option[41]: -fsdb
option[42]: -sverilog
option[43]: -gen_obj
option[44]: -f
option[45]: filelist_vlg.f
option[46]: -load
option[47]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
option[48]: timescale=1ns/1ps
Chronologic Simulation VCS Release O-2018.09-SP2_Full64
Linux 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64
CPU cores: 96
Limit information:
======================================
cputime unlimited
filesize unlimited
datasize unlimited
stacksize 8192 kbytes
coredumpsize 0 kbytes
memoryuse unlimited
vmemoryuse unlimited
descriptors 4096
memorylocked 64 kbytes
maxproc 4096
======================================
(Special)Runtime environment variables:
Runtime environment variables:
INNOVUS_HOME=/opt/cadence/INNOVUS181
VNCDESKTOP=cryo1:17 (shbyang)
MGC_PDF_REDER=evince
XDG_SESSION_ID=c5
SSH_AGENT_PID=6119
DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67
MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1
HOSTNAME=cryo1
IMSETTINGS_INTEGRATE_DESKTOP=yes
CDSROOT=/opt/cadence/IC618
NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2
HOST=cryo1
TERM=xterm-256color
XDG_MENU_PREFIX=gnome-
VTE_VERSION=5204
SHELL=/bin/csh
MAKEFLAGS=
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/33c4f0fe_b1af_4925_918d_f401e6285844
SPECTRE_HOME=/opt/cadence/SPECTRE181
VIVADO_HOME=/opt/xilinx/Vivado/2019.2/
CDS_LOAD_ENV=CWD
PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3
QTDIR=/usr/lib64/qt-3.3
QTINC=/usr/lib64/qt-3.3/include
MENTOR_HOME=/opt/mentor
IMSETTINGS_MODULE=none
QT_GRAPHICSSYSTEM_CHECKED=1
GROUP=cryo
USER=shbyang
LD_LIBRARY_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/shared/pkgs/icv/tools/calibre_client/lib/64
LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45:
GNOME_TERMINAL_SERVICE=:1.2258
W3264_NO_HOST_CHECK=1
CDS=/opt/cadence/IC618
HOSTTYPE=x86_64-linux
SSH_AUTH_SOCK=/run/user/1019/keyring/ssh
MAKELEVEL=1
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/5094,unix/unix:/tmp/.ICE-unix/5094
SNPSLMD_LICENSE_FILE=27050@192.168.1.77
MFLAGS=
SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1
VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12
GNOME_SHELL_SESSION_MODE=classic
GENUS_HOME=/opt/cadence/GENUS152
MAIL=/var/spool/mail/shbyang
starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1
PATH=/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/
SPECTRE_DEFAULTS=-E
PT_HOME=/opt/synopsys/pts/O-2018.06-SP1
QT_IM_MODULE=ibus
_=./simv
VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2
CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11
CDS_SPECTRERF_FBENABLE=1
CADENCE_DIR=/opt/cadence/IC618
PWD=/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top
CDSDIR=/opt/cadence/IC618
VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2
XMODIFIERS=@im=ibus
MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1
TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1
FM_HOME=/opt/synopsys/fm/L-2016.03-SP1
LANG=C
VRST_HOME=/opt/cadence/INCISIVE152
CDSHOME=/opt/cadence/IC618
CDS_Netlisting_Mode=Analog
SYNOPSYS=/opt/synopsys
AMS_ENABLE_NOISE=YES
SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn
DBUS_STARTER_BUS_TYPE=session
SHLVL=5
HOME=/home/shbyang
OSTYPE=linux
MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
CDS_AUTO_64BIT=ALL
CADHOME=/opt/cadence
VENDOR=unknown
MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib
LOGNAME=shbyang
MACHTYPE=x86_64
QTLIB=/usr/lib64/qt-3.3/lib
MGLS_LICENSE_FILE=/opt/mentor/license/license.dat
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67
IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1
CDS_LIC_FILE=/opt/cadence/license/license.dat
MOZILLA_HOME=/usr/bin/firefox
LESSOPEN=||/usr/bin/lesspipe.sh %s
SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn
SCL_HOME=/opt/synopsys/scl/2018.06
HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2
FPGA_HOME=/opt/synopsys/fpga/K-2015.09
OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x
CDS_ENABLE_VMS=1
MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1
DISPLAY=unix:17
XDG_RUNTIME_DIR=/run/user/1019
CDS_LIC_ONLY=1
LC_HOME=/opt/synopsys/lc/O-2018.06-SP1
CDS_ROOT=/opt/cadence/IC618
XILINX_HOME=/opt/xilinx
INCISIVE_HOME=/opt/cadence/INCISIVE152
XDG_CURRENT_DESKTOP=GNOME
CDS_SPECTRE_FBENABLE=1
CALIBRE_ENABLE_SKILL_PEXBA_MODE=1
CDS_INST_DIR=/opt/cadence/IC618
WV_HOME=/opt/synopsys/wv/N-2017.12-SP2
COLORTERM=truecolor
VCS_HEAP_EXEC=true
VCS_PATHMAP_PRELOAD_DONE=1
VCS_STACK_EXEC=true
VCS_EXEC_DONE=1
LC_ALL=C
DVE=/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve
SPECMAN_OUTPUT_TO_TTY=1
Runtime command line arguments:
argv[0]=./simv
argv[1]=sync:busywait
argv[2]=-l
291 profile - 100
CPU/Mem usage: 0.050 sys, 0.220 user, 282.41M mem
292 Tue Apr 7 09:38:20 2026
293 pliAppInit
294 FSDB_GATE is set.
295 FSDB_RTL is set.
296 Enable Parallel Dumping.
297 pliAppMiscSet: New Sim Round
298 pliEntryInit
299 LIBSSCORE=found /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
300 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
301 (C) 1996 - 2019 by Synopsys, Inc.
302 sps_call_fsdbDumpfile_main at 0 : ./TB.sv(22)
303 argv[0]: (wave.fsdb)
304 *Verdi* : Create FSDB file 'wave.fsdb'
305 compile option from '/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/vcs_rebuild'.
306 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1"
307 FSDB_VCS_ENABLE_FAST_VC is enable
308 sps_call_fsdbDumpvars_vd_main at 0 : ./TB.sv(23)
309 [spi_vcs_vd_ppi_create_root]: no upf option
310 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
311 *Verdi* : Begin traversing the scopes, layer (0).
312 *Verdi* : End of traversing.
313 pliAppHDL_DumpVarComplete traverse var: profile -
CPU/Mem usage: 0.080 sys, 0.230 user, 378.79M mem
incr: 0.000 sys, 0.010 user, 8.98M mem
accu: 0.000 sys, 0.010 user, 8.98M mem
accu incr: 0.000 sys, 0.010 user, 8.98M mem
Count usage: 224 var, 123 idcode, 86 callback
incr: 224 var, 123 idcode, 86 callback
accu: 224 var, 123 idcode, 86 callback
accu incr: 224 var, 123 idcode, 86 callback
314 Tue Apr 7 09:38:20 2026
315 pliAppHDL_DumpVarComplete: profile -
CPU/Mem usage: 0.080 sys, 0.230 user, 379.84M mem
incr: 0.000 sys, 0.000 user, 1.05M mem
accu: 0.000 sys, 0.010 user, 10.04M mem
accu incr: 0.000 sys, 0.000 user, 1.05M mem
Count usage: 224 var, 123 idcode, 86 callback
incr: 0 var, 0 idcode, 0 callback
accu: 224 var, 123 idcode, 86 callback
accu incr: 0 var, 0 idcode, 0 callback
316 Tue Apr 7 09:38:20 2026
317 End of simulation at 17814400000
318 Tue Apr 7 09:38:21 2026
319 Begin FSDB profile info:
320 FSDB Writer : bc1(1815118) bcn(1365370) mtf/stf(0/1)
FSDB Writer elapsed time : flush(0.171826) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
FSDB Writer cpu time : MT Compression : 0
321 End FSDB profile info
322 Parallel profile - Flush:3 Expand:0 ProduceWait:0 ConsumerWait:27 BlockUsed:34
323 ProduceTime:1.172810727 ConsumerTime:0.465192911 Buffer:64MB
324 SimExit
325 Sim process exit

8
sim/therm_chip_top/rx_data.txt Normal file
View File

@ -0,0 +1,8 @@
20260406
000003e8
025800a0
0000c350
00fff060
00000b02
aa000b02
00000b02

61
sim/therm_chip_top/sim.log Normal file
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@ -0,0 +1,61 @@
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Apr 7 09:38 2026
*Verdi* Loading libsscore_vcs201809.so
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc.
*Verdi* : Create FSDB file 'wave.fsdb'
*Verdi* : Begin traversing the scopes, layer (0).
*Verdi* : End of traversing.
------- Step 1: Configure Thermometer Regs -------
[ 775170000] Byte 0: 0x20
[ 862030000] Byte 1: 0x26
[ 948890000] Byte 2: 0x04
[ 1035750000] Byte 3: 0x06
[ 1035750000] Packet (32-bit): 0x20260406
[ 1469570000] Byte 0: 0x00
[ 1556430000] Byte 1: 0x00
[ 1643290000] Byte 2: 0x03
[ 1730150000] Byte 3: 0xe8
[ 1730150000] Packet (32-bit): 0x000003e8
[ 2163970000] Byte 0: 0x02
[ 2250830000] Byte 1: 0x58
[ 2337690000] Byte 2: 0x00
[ 2424550000] Byte 3: 0xa0
[ 2424550000] Packet (32-bit): 0x025800a0
[ 2858370000] Byte 0: 0x00
[ 2945230000] Byte 1: 0x00
[ 3032090000] Byte 2: 0xc3
[ 3118950000] Byte 3: 0x50
[ 3118950000] Packet (32-bit): 0x0000c350
------- Step 2: Running Concurrent Tasks -------
[3474400000] Start generating signal: 400 kHz
[ 3552770000] Byte 0: 0x00
[ 3639630000] Byte 1: 0xff
[ 3726490000] Byte 2: 0xf0
[ 3813350000] Byte 3: 0x60
[ 3813350000] Packet (32-bit): 0x00fff060
[ 5474400000] TX: Sending Read Request during active reporting...
[ 6247170000] Byte 0: 0x00
[ 6334030000] Byte 1: 0x00
[ 6420890000] Byte 2: 0x0b
[ 6507750000] Byte 3: 0x02
[ 6507750000] Packet (32-bit): 0x00000b02
[ 8330370000] Byte 0: 0xaa
[ 8417230000] Byte 1: 0x00
[ 8504090000] Byte 2: 0x0b
[ 8590950000] Byte 3: 0x02
[ 8590950000] Packet (32-bit): 0xaa000b02
[ 9054770000] Byte 0: 0x00
[ 9141630000] Byte 1: 0x00
[ 9228490000] Byte 2: 0x0b
[ 9315350000] Byte 3: 0x02
[ 9315350000] Packet (32-bit): 0x00000b02
Test Done.
$finish called from file "./TB.sv", line 221.
[RX] File closed at 17814400000
$finish at simulation time 17814400000
V C S S i m u l a t i o n R e p o r t
Time: 17814400000 ps
CPU Time: 1.630 seconds; Data structure size: 0.0Mb
Tue Apr 7 09:38:21 2026

BIN
sim/therm_chip_top/simv Normal file
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0
sim/therm_chip_top/simv.daidir/.daidir_complete Normal file
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0
sim/therm_chip_top/simv.daidir/.normal_done Normal file
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172
sim/therm_chip_top/simv.daidir/.vcs.timestamp Normal file
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@ -0,0 +1,172 @@
0
41
+itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab
+lint=TFIPC-L
+nospecify
+v2k
+vcsd1
+vpi
-Mamsrun=
-Masflags=
-Mcc=gcc
-Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include
-Mcplusplus=g++
-Mcrt0=
-Mcrtn=
-Mcsrc=
-Mexternalobj=
-Mldflags= -rdynamic
-Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so
-Mout=simv
-Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o
-Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
-Mvcsaceobjs=
-Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include
-P
-cm
-cm_dir
-debug_access+pp
-f filelist_vlg.f
-fsdb
-full64
-gen_obj
-l
-lca
-picarchive
-q
-sverilog
-timescale=1ns/1ps
./coverage/simv.vdb
/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1
/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
compile.log
line+cond+fsm+tgl+branch
105
sysc_uni_pwd=/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top
starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1
XMODIFIERS=@im=ibus
XILINX_HOME=/opt/xilinx
XDG_SESSION_ID=c5
XDG_RUNTIME_DIR=/run/user/1019
XDG_MENU_PREFIX=gnome-
XDG_CURRENT_DESKTOP=GNOME
WV_HOME=/opt/synopsys/wv/N-2017.12-SP2
W3264_NO_HOST_CHECK=1
VTE_VERSION=5204
VRST_HOME=/opt/cadence/INCISIVE152
VNCDESKTOP=cryo1:17 (shbyang)
VMR_MODE_FLAG=64
VIVADO_HOME=/opt/xilinx/Vivado/2019.2/
VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2
VENDOR=unknown
VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12
VCS_MX_HOME_INTERNAL=1
VCS_MODE_FLAG=64
VCS_LOG_FILE=compile.log
VCS_LCAMSG_PRINT_OFF=1
VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2
VCS_DEPTH=0
VCS_ARG_ADDED_FOR_TMP=1
VCS_ARCH=linux64
UNAME=/bin/uname
TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1
TOOL_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64
SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1
SYNOPSYS=/opt/synopsys
SSH_AUTH_SOCK=/run/user/1019/keyring/ssh
SSH_AGENT_PID=6119
SPECTRE_HOME=/opt/cadence/SPECTRE181
SPECTRE_DEFAULTS=-E
SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn
SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/5094,unix/unix:/tmp/.ICE-unix/5094
SCRNAME=vcs
SCRIPT_NAME=vcs
SCL_HOME=/opt/synopsys/scl/2018.06
QT_IM_MODULE=ibus
QT_GRAPHICSSYSTEM_CHECKED=1
QTLIB=/usr/lib64/qt-3.3/lib
QTINC=/usr/lib64/qt-3.3/include
QTDIR=/usr/lib64/qt-3.3
PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3
PT_HOME=/opt/synopsys/pts/O-2018.06-SP1
OVA_UUM=0
OSTYPE=linux
OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x
NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2
MOZILLA_HOME=/usr/bin/firefox
MGLS_LICENSE_FILE=/opt/mentor/license/license.dat
MGC_PDF_REDER=evince
MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib
MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11
MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1
MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1
MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1
MFLAGS=
MENTOR_HOME=/opt/mentor
MAKELEVEL=1
MAKEFLAGS=
LESSOPEN=||/usr/bin/lesspipe.sh %s
LC_HOME=/opt/synopsys/lc/O-2018.06-SP1
LC_ALL=C
INNOVUS_HOME=/opt/cadence/INNOVUS181
INCISIVE_HOME=/opt/cadence/INCISIVE152
IMSETTINGS_MODULE=none
IMSETTINGS_INTEGRATE_DESKTOP=yes
IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1
HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2
HOSTTYPE=x86_64-linux
GROUP=cryo
GNOME_TERMINAL_SERVICE=:1.2258
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/33c4f0fe_b1af_4925_918d_f401e6285844
GNOME_SHELL_SESSION_MODE=classic
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
GENUS_HOME=/opt/cadence/GENUS152
FPGA_HOME=/opt/synopsys/fpga/K-2015.09
FM_HOME=/opt/synopsys/fm/L-2016.03-SP1
DBUS_STARTER_BUS_TYPE=session
DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67
COLORTERM=truecolor
CDS_SPECTRE_FBENABLE=1
CDS_SPECTRERF_FBENABLE=1
CDS_ROOT=/opt/cadence/IC618
CDS_Netlisting_Mode=Analog
CDS_LOAD_ENV=CWD
CDS_LIC_ONLY=1
CDS_LIC_FILE=/opt/cadence/license/license.dat
CDS_INST_DIR=/opt/cadence/IC618
CDS_ENABLE_VMS=1
CDS_AUTO_64BIT=ALL
CDSROOT=/opt/cadence/IC618
CDSHOME=/opt/cadence/IC618
CDSDIR=/opt/cadence/IC618
CDS=/opt/cadence/IC618
CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11
CALIBRE_ENABLE_SKILL_PEXBA_MODE=1
CADHOME=/opt/cadence
CADENCE_DIR=/opt/cadence/IC618
AMS_ENABLE_NOISE=YES
0
14
1775464866 ./TB.sv
1775377742 ../../rtl/therm/pulse_cnt.v
1775454778 ../../rtl/therm/digital_thermometer.v
1774925224 ../../rtl/uart/uart_byte_tx.v
1775370228 ../../rtl/uart/uart_top_32bit.v
1775459928 ../../rtl/uart/uart_ctrl_sysreg.v
1774924538 ../../rtl/uart/uart_byte_rx.v
1775525487 ../../rtl/digital_top.v
1774930574 ../../rtl/systemregfile/sirv_gnrl_dffs.v
1775525827 ../../rtl/systemregfile/my_systemregfile.v
1551421444 /opt/synopsys/vcs-mx/O-2018.09-SP2/include/cm_vcsd.tab
1775464043 filelist_vlg.f
1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
1551421246 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab
4
1551422344 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so
1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so
1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so
1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so
1775525900 simv.daidir
-1 partitionlib

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sim/therm_chip_top/simv.daidir/build_db Normal file
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#!/bin/sh -e
# This file is automatically generated by VCS. Any changes you make
# to it will be overwritten the next time VCS is run.
vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' -static_dbgen_only -daidir=$1 2>&1

12
sim/therm_chip_top/simv.daidir/cc/cc_bcode.db Normal file
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sid TB
bcid 0 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
bcid 1 1 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU WIDTH,30 CALL_ARG_VAL,3,0 OPT_CONST,433 WIDTH,1 M_EQU AND RET
bcid 2 2 WIDTH,30 CALL_ARG_VAL,2,0 OPT_CONST,216 WIDTH,1 M_EQU WIDTH,4 CALL_ARG_VAL,3,0 OPT_CONST,9 WIDTH,1 M_EQU AND RET
bcid 3 3 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET
bcid 4 4 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,4 WIDTH,1 M_EQU RET
bcid 5 5 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,8 WIDTH,1 M_EQU RET
bcid 6 6 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,12 WIDTH,1 M_EQU RET
bcid 7 7 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,16 WIDTH,1 M_EQU RET
bcid 8 8 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,20 WIDTH,1 M_EQU RET
bcid 9 9 WIDTH,24 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,1000 MULTIPLY WIDTH,24 CALL_ARG_VAL,3,0 WIDTH,32 PAD DIVIDE OPT_CONST,0 WIDTH,24 SLICE,1 RET
bcid 10 10 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET

2
sim/therm_chip_top/simv.daidir/cc/cc_dummy_file Normal file
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Dummy_file
Missing line/file info

50
sim/therm_chip_top/simv.daidir/cgname.json Normal file
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{
"TB": [
"TB",
"sH4Fc",
"module",
7
],
"sirv_gnrl_dffl": [
"sirv_gnrl_dffl",
"BM4bj",
"module",
4
],
"std": [
"std",
"reYIK",
"module",
1
],
"sirv_gnrl_dffrs": [
"sirv_gnrl_dffrs",
"QHiet",
"module",
5
],
"sirv_gnrl_dfflrs": [
"sirv_gnrl_dfflrs",
"ZJgwY",
"module",
2
],
"sirv_gnrl_dfflrd": [
"sirv_gnrl_dfflrd",
"Uye5v",
"module",
3
],
"sirv_gnrl_ltch": [
"sirv_gnrl_ltch",
"UTi0b",
"module",
6
],
"...MASTER...": [
"SIM",
"amcQw",
"module",
8
]
}

0
sim/therm_chip_top/simv.daidir/covg_defs Normal file
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sim/therm_chip_top/simv.daidir/debug_dump/.version Normal file
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O-2018.09-SP2_Full64
Build Date = Feb 28 2019 22:34:30
RedHat
Compile Location: /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top

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sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db Normal file
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#!/bin/sh -h
PYTHONHOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/etc/search/pyh
export PYTHONHOME
PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27
export PYTHONPATH
LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27
export LD_LIBRARY_PATH
/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_ik1qVk.xml.gz" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
\mv "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db"

57
sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db Normal file
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#!/bin/sh -h
FILE_PATH="/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch"
lockfile="${FILE_PATH}"/lock
FSearch_lock_release() {
echo "" > /dev/null
}
create_fsearch_db_ctrl() {
if [ -s "${FILE_PATH}"/fsearch.stat ]; then
if [ -s "${FILE_PATH}"/fsearch.log ]; then
echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log"
else
cat "${FILE_PATH}"/fsearch.stat
fi
return
fi
nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null &
MY_PID=`echo $!`
BUILDER="pid ${MY_PID} ${USER}@${hostname}"
echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier."
echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat
return
}
dir_name=`/bin/dirname "$0"`
if [ "${dir_name}" = "." ]; then
cd $dir_name
dir_name=`/bin/pwd`
fi
if [ -d "$dir_name"/../../../../../../../../../.. ]; then
cd "$dir_name"/../../../../../../../../../..
fi
if [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
if [ ! -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then
trap FSearch_lock_release EXIT
(
flock 193
create_fsearch_db_ctrl "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
exit 193
) 193> "$lockfile"
rstat=$?
if [ "${rstat}"x != "193x" ]; then
exit $rstat
fi
else
"/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
if [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
rm -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat"
fi
fi
elif [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
rm -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat"
fi
fi

0
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