From 3368b7c023e88558c9bdc90ccb9a08bf40db7dab Mon Sep 17 00:00:00 2001 From: yangshenbo Date: Tue, 7 Apr 2026 09:50:35 +0800 Subject: [PATCH] organize the table + translate --- rtl/digital_top.v | 10 +- rtl/systemregfile/my_systemregfile.v | 266 +- rtl/systemregfile/sirv_gnrl_dffs.v | 684 ++--- rtl/{ => therm}/digital_thermometer.v | 32 +- rtl/{ => therm}/pulse_cnt.v | 15 +- rtl/{ => uart}/uart_byte_rx.v | 0 rtl/{ => uart}/uart_byte_tx.v | 0 rtl/{ => uart}/uart_ctrl_sysreg.v | 52 +- rtl/{ => uart}/uart_top_32bit.v | 52 +- sim/therm_chip_top/Makefile | 74 + sim/therm_chip_top/TB.sv | 224 ++ sim/therm_chip_top/compile.log | 20 + .../coverage/simv.vdb/.cmoptions | 16 + sim/therm_chip_top/coverage/simv.vdb/.mode64 | 0 .../coverage/simv.vdb/.vdb_version | 1 + .../snps/coverage/db/auxiliary/dve_debug.xml | Bin 0 -> 1324 bytes .../auxiliary/verilog.instance_parameters.txt | 7 + .../db/auxiliary/verilog.sourceinfo.xml | 15 + .../coverage/db/design/verilog.design.xml | Bin 0 -> 971 bytes .../db/shape/branch.verilog.shape.xml | Bin 0 -> 3733 bytes .../db/shape/cond.verilog.exclude.xml | Bin 0 -> 47 bytes .../coverage/db/shape/cond.verilog.shape.xml | Bin 0 -> 740 bytes .../coverage/db/shape/fsm.verilog.exclude.xml | Bin 0 -> 47 bytes .../db/shape/fsm.verilog.generated_config.txt | 97 + .../coverage/db/shape/fsm.verilog.shape.xml | 47 + .../db/shape/line.verilog.exclude.xml | Bin 0 -> 47 bytes .../coverage/db/shape/line.verilog.shape.xml | Bin 0 -> 8759 bytes .../coverage/db/shape/tgl.verilog.shape.xml | Bin 0 -> 2481 bytes sim/therm_chip_top/csrc/Makefile | 116 + sim/therm_chip_top/csrc/Makefile.hsopt | 47 + sim/therm_chip_top/csrc/SIM_l.o | Bin 0 -> 558 bytes sim/therm_chip_top/csrc/_131020_archive_1.so | 1 + sim/therm_chip_top/csrc/_131039_archive_1.so | 1 + sim/therm_chip_top/csrc/_131040_archive_1.so | 1 + sim/therm_chip_top/csrc/_vcs_pli_stub_.c | 964 +++++++ sim/therm_chip_top/csrc/_vcs_pli_stub_.o | Bin 0 -> 32032 bytes .../csrc/archive.0/_131020_archive_1.a | Bin 0 -> 186416 bytes .../csrc/archive.0/_131020_archive_1.a.info | 6 + .../csrc/archive.0/_131039_archive_1.a | Bin 0 -> 135950 bytes .../csrc/archive.0/_131039_archive_1.a.info | 1 + .../csrc/archive.0/_131040_archive_1.a | Bin 0 -> 39322 bytes .../csrc/archive.0/_131040_archive_1.a.info | 1 + sim/therm_chip_top/csrc/cgincr.sdb | Bin 0 -> 3585 bytes sim/therm_chip_top/csrc/cginfo.json | 388 +++ sim/therm_chip_top/csrc/cgproc.131020.json | 281 ++ sim/therm_chip_top/csrc/cgproc.131039.json | 88 + sim/therm_chip_top/csrc/cgproc.131040.json | 116 + sim/therm_chip_top/csrc/filelist | 32 + sim/therm_chip_top/csrc/filelist.cu | 49 + sim/therm_chip_top/csrc/filelist.dpi | 0 sim/therm_chip_top/csrc/filelist.hsopt | 13 + .../csrc/filelist.hsopt.llvm2_0.objs | 1 + sim/therm_chip_top/csrc/filelist.hsopt.objs | 7 + sim/therm_chip_top/csrc/filelist.pli | 4 + sim/therm_chip_top/csrc/hsim/hsim.sdb | Bin 0 -> 2512 bytes sim/therm_chip_top/csrc/import_dpic.h | 0 sim/therm_chip_top/csrc/objs/amcQw_d.o | Bin 0 -> 9036 bytes sim/therm_chip_top/csrc/product_timestamp | 0 sim/therm_chip_top/csrc/rmapats.c | 43 + sim/therm_chip_top/csrc/rmapats.h | 2474 +++++++++++++++++ sim/therm_chip_top/csrc/rmapats.m | 0 sim/therm_chip_top/csrc/rmapats.o | Bin 0 -> 2096 bytes sim/therm_chip_top/csrc/rmapats_mop.o | Bin 0 -> 8446 bytes sim/therm_chip_top/csrc/rmar.c | 13 + sim/therm_chip_top/csrc/rmar.h | 18 + sim/therm_chip_top/csrc/rmar.o | Bin 0 -> 1232 bytes sim/therm_chip_top/csrc/rmar0.h | 13 + sim/therm_chip_top/csrc/rmar_llvm_0_0.o | Bin 0 -> 2248 bytes sim/therm_chip_top/csrc/rmar_llvm_0_1.o | Bin 0 -> 1408 bytes sim/therm_chip_top/csrc/rmar_nd.o | Bin 0 -> 1248 bytes sim/therm_chip_top/csrc/vcspieces.incr | 0 sim/therm_chip_top/filelist_vlg.f | 10 + sim/therm_chip_top/novas.conf | 338 +++ sim/therm_chip_top/novas.rc | 1310 +++++++++ sim/therm_chip_top/novas_dump.log | 347 +++ sim/therm_chip_top/rx_data.txt | 8 + sim/therm_chip_top/sim.log | 61 + sim/therm_chip_top/simv | Bin 0 -> 923936 bytes .../simv.daidir/.daidir_complete | 0 sim/therm_chip_top/simv.daidir/.normal_done | 0 sim/therm_chip_top/simv.daidir/.vcs.timestamp | 172 ++ .../simv.daidir/_131020_archive_1.so | Bin 0 -> 210744 bytes .../simv.daidir/_131039_archive_1.so | Bin 0 -> 137184 bytes .../simv.daidir/_131040_archive_1.so | Bin 0 -> 43200 bytes sim/therm_chip_top/simv.daidir/binmap.sdb | Bin 0 -> 13499 bytes sim/therm_chip_top/simv.daidir/build_db | 4 + sim/therm_chip_top/simv.daidir/cc/cc_bcode.db | 12 + .../simv.daidir/cc/cc_dummy_file | 2 + sim/therm_chip_top/simv.daidir/cgname.json | 50 + sim/therm_chip_top/simv.daidir/covg_defs | 0 .../simv.daidir/debug_dump/.version | 4 + .../debug_dump/AllModulesSkeletons.sdb | Bin 0 -> 2271 bytes .../simv.daidir/debug_dump/HsimSigOptDb.sdb | Bin 0 -> 3910 bytes .../simv.daidir/debug_dump/dumpcheck.db | 0 .../simv.daidir/debug_dump/dve_debug.db.gz | Bin 0 -> 1324 bytes .../debug_dump/fsearch/.create_fsearch_db | 9 + .../debug_dump/fsearch/check_fsearch_db | 57 + .../debug_dump/fsearch/fsearch.stat | 0 .../debug_dump/fsearch/idents_ik1qVk.xml.gz | Bin 0 -> 2914 bytes .../debug_dump/fsearch/idents_tapi.xml.gz | Bin 0 -> 205 bytes .../simv.daidir/debug_dump/src_files_verilog | 10 + .../simv.daidir/debug_dump/topmodules | 1 + .../simv.daidir/debug_dump/vir.sdb | Bin 0 -> 39224 bytes sim/therm_chip_top/simv.daidir/eblklvl.db | Bin 0 -> 24 bytes sim/therm_chip_top/simv.daidir/elabmoddb.sdb | Bin 0 -> 15142 bytes .../simv.daidir/external_functions | 78 + .../simv.daidir/hslevel_callgraph.sdb | Bin 0 -> 1974 bytes .../simv.daidir/hslevel_level.sdb | Bin 0 -> 1663 bytes .../simv.daidir/hslevel_rtime_level.sdb | Bin 0 -> 248 bytes sim/therm_chip_top/simv.daidir/hsscan_cfg.dat | 0 sim/therm_chip_top/simv.daidir/indcall.sdb | Bin 0 -> 573 bytes .../simv.daidir/indcall_131020.sdb | Bin 0 -> 2385 bytes .../simv.daidir/indcall_131039.sdb | Bin 0 -> 573 bytes .../simv.daidir/indcall_131040.sdb | Bin 0 -> 573 bytes sim/therm_chip_top/simv.daidir/nsparam.dat | Bin 0 -> 8 bytes sim/therm_chip_top/simv.daidir/pcc.sdb | Bin 0 -> 1028 bytes sim/therm_chip_top/simv.daidir/pcxpxmr.dat | Bin 0 -> 20 bytes sim/therm_chip_top/simv.daidir/prof.sdb | Bin 0 -> 14026 bytes sim/therm_chip_top/simv.daidir/rmapats.dat | Bin 0 -> 2104 bytes sim/therm_chip_top/simv.daidir/rmapats.so | Bin 0 -> 20368 bytes sim/therm_chip_top/simv.daidir/saifNetInfo.db | 1 + .../simv.daidir/stitch_nsparam.dat | Bin 0 -> 4 bytes sim/therm_chip_top/simv.daidir/tt.sdb | Bin 0 -> 9691 bytes .../simv.daidir/ttIncr_131020.sdb | Bin 0 -> 563 bytes .../simv.daidir/ttIncr_131039.sdb | Bin 0 -> 223 bytes .../simv.daidir/ttIncr_131040.sdb | Bin 0 -> 223 bytes sim/therm_chip_top/simv.daidir/vcs_rebuild | 4 + .../vcselab_master_hsim_elabout.db | 691 +++++ .../simv.daidir/vcselab_misc_hsdef.db | Bin 0 -> 28 bytes .../simv.daidir/vcselab_misc_hsim_elab.db | 1217 ++++++++ .../simv.daidir/vcselab_misc_hsim_fegate.db | Bin 0 -> 4680 bytes .../simv.daidir/vcselab_misc_hsim_lvl.db | Bin 0 -> 1988 bytes .../simv.daidir/vcselab_misc_hsim_name.db | Bin 0 -> 193 bytes .../simv.daidir/vcselab_misc_hsim_uds.db | 3 + .../simv.daidir/vcselab_misc_midd.db | Bin 0 -> 583 bytes .../simv.daidir/vcselab_misc_mnmn.db | Bin 0 -> 133 bytes .../simv.daidir/vcselab_misc_partition.db | Bin 0 -> 5152 bytes .../simv.daidir/vcselab_misc_vcselabref.db | Bin 0 -> 1 bytes .../simv.daidir/vcselab_misc_vpdnodenums | Bin 0 -> 1348 bytes sim/therm_chip_top/ucli.key | 0 .../verdiLog/.diagnose.oneSearch | 0 sim/therm_chip_top/verdiLog/ToNetlist.log | 0 sim/therm_chip_top/verdiLog/compiler.log | 26 + sim/therm_chip_top/verdiLog/exe.log | 0 sim/therm_chip_top/verdiLog/novas.log | 10 + sim/therm_chip_top/verdiLog/novas.rc | 1306 +++++++++ .../verdiLog/novas_autosave.ses | 83 + .../verdiLog/novas_autosave.ses.config | 55 + .../verdiLog/novas_autosave.ses.png | Bin 0 -> 99865 bytes .../verdiLog/novas_autosave.ses.wave.0 | 65 + sim/therm_chip_top/verdiLog/pes.bat | 3 + sim/therm_chip_top/verdiLog/turbo.log | 3 + sim/therm_chip_top/verdiLog/verdi.cmd | 66 + .../verdiLog/verdi_perf_err.log | 0 sim/therm_chip_top/wave.fsdb | Bin 0 -> 119376 bytes tb/TB.v | 95 - 156 files changed, 11739 insertions(+), 652 deletions(-) rename rtl/{ => therm}/digital_thermometer.v (67%) rename rtl/{ => therm}/pulse_cnt.v (73%) rename rtl/{ => uart}/uart_byte_rx.v (100%) rename rtl/{ => uart}/uart_byte_tx.v (100%) rename rtl/{ => uart}/uart_ctrl_sysreg.v (72%) rename rtl/{ => uart}/uart_top_32bit.v (74%) create mode 100644 sim/therm_chip_top/Makefile create mode 100644 sim/therm_chip_top/TB.sv create mode 100644 sim/therm_chip_top/compile.log create mode 100644 sim/therm_chip_top/coverage/simv.vdb/.cmoptions create mode 100644 sim/therm_chip_top/coverage/simv.vdb/.mode64 create mode 100644 sim/therm_chip_top/coverage/simv.vdb/.vdb_version create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/dve_debug.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.instance_parameters.txt create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/auxiliary/verilog.sourceinfo.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/design/verilog.design.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/branch.verilog.shape.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.exclude.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/cond.verilog.shape.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.exclude.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.generated_config.txt create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.exclude.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/line.verilog.shape.xml create mode 100644 sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/tgl.verilog.shape.xml create mode 100644 sim/therm_chip_top/csrc/Makefile create mode 100644 sim/therm_chip_top/csrc/Makefile.hsopt create mode 100644 sim/therm_chip_top/csrc/SIM_l.o create mode 120000 sim/therm_chip_top/csrc/_131020_archive_1.so create mode 120000 sim/therm_chip_top/csrc/_131039_archive_1.so create mode 120000 sim/therm_chip_top/csrc/_131040_archive_1.so create mode 100644 sim/therm_chip_top/csrc/_vcs_pli_stub_.c create mode 100644 sim/therm_chip_top/csrc/_vcs_pli_stub_.o create mode 100644 sim/therm_chip_top/csrc/archive.0/_131020_archive_1.a create mode 100644 sim/therm_chip_top/csrc/archive.0/_131020_archive_1.a.info create mode 100644 sim/therm_chip_top/csrc/archive.0/_131039_archive_1.a create mode 100644 sim/therm_chip_top/csrc/archive.0/_131039_archive_1.a.info create mode 100644 sim/therm_chip_top/csrc/archive.0/_131040_archive_1.a create mode 100644 sim/therm_chip_top/csrc/archive.0/_131040_archive_1.a.info create mode 100644 sim/therm_chip_top/csrc/cgincr.sdb create mode 100644 sim/therm_chip_top/csrc/cginfo.json create mode 100644 sim/therm_chip_top/csrc/cgproc.131020.json create mode 100644 sim/therm_chip_top/csrc/cgproc.131039.json create mode 100644 sim/therm_chip_top/csrc/cgproc.131040.json create mode 100644 sim/therm_chip_top/csrc/filelist create mode 100644 sim/therm_chip_top/csrc/filelist.cu create mode 100644 sim/therm_chip_top/csrc/filelist.dpi create mode 100644 sim/therm_chip_top/csrc/filelist.hsopt create mode 100644 sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs create mode 100644 sim/therm_chip_top/csrc/filelist.hsopt.objs create mode 100644 sim/therm_chip_top/csrc/filelist.pli create mode 100644 sim/therm_chip_top/csrc/hsim/hsim.sdb create mode 100644 sim/therm_chip_top/csrc/import_dpic.h create mode 100644 sim/therm_chip_top/csrc/objs/amcQw_d.o create mode 100644 sim/therm_chip_top/csrc/product_timestamp create mode 100644 sim/therm_chip_top/csrc/rmapats.c create mode 100644 sim/therm_chip_top/csrc/rmapats.h create mode 100644 sim/therm_chip_top/csrc/rmapats.m create mode 100644 sim/therm_chip_top/csrc/rmapats.o create mode 100644 sim/therm_chip_top/csrc/rmapats_mop.o create mode 100644 sim/therm_chip_top/csrc/rmar.c create mode 100644 sim/therm_chip_top/csrc/rmar.h create mode 100644 sim/therm_chip_top/csrc/rmar.o create mode 100644 sim/therm_chip_top/csrc/rmar0.h create mode 100644 sim/therm_chip_top/csrc/rmar_llvm_0_0.o create mode 100644 sim/therm_chip_top/csrc/rmar_llvm_0_1.o create mode 100644 sim/therm_chip_top/csrc/rmar_nd.o create mode 100644 sim/therm_chip_top/csrc/vcspieces.incr create mode 100644 sim/therm_chip_top/filelist_vlg.f create mode 100644 sim/therm_chip_top/novas.conf create mode 100644 sim/therm_chip_top/novas.rc create mode 100644 sim/therm_chip_top/novas_dump.log create mode 100644 sim/therm_chip_top/rx_data.txt create mode 100644 sim/therm_chip_top/sim.log create mode 100644 sim/therm_chip_top/simv create mode 100644 sim/therm_chip_top/simv.daidir/.daidir_complete create mode 100644 sim/therm_chip_top/simv.daidir/.normal_done create mode 100644 sim/therm_chip_top/simv.daidir/.vcs.timestamp create mode 100644 sim/therm_chip_top/simv.daidir/_131020_archive_1.so create mode 100644 sim/therm_chip_top/simv.daidir/_131039_archive_1.so create mode 100644 sim/therm_chip_top/simv.daidir/_131040_archive_1.so create mode 100644 sim/therm_chip_top/simv.daidir/binmap.sdb create mode 100644 sim/therm_chip_top/simv.daidir/build_db create mode 100644 sim/therm_chip_top/simv.daidir/cc/cc_bcode.db create mode 100644 sim/therm_chip_top/simv.daidir/cc/cc_dummy_file create mode 100644 sim/therm_chip_top/simv.daidir/cgname.json create mode 100644 sim/therm_chip_top/simv.daidir/covg_defs create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/.version create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/dumpcheck.db create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/dve_debug.db.gz create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_ik1qVk.xml.gz create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/src_files_verilog create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/topmodules create mode 100644 sim/therm_chip_top/simv.daidir/debug_dump/vir.sdb create mode 100644 sim/therm_chip_top/simv.daidir/eblklvl.db create mode 100644 sim/therm_chip_top/simv.daidir/elabmoddb.sdb create mode 100644 sim/therm_chip_top/simv.daidir/external_functions create mode 100644 sim/therm_chip_top/simv.daidir/hslevel_callgraph.sdb create mode 100644 sim/therm_chip_top/simv.daidir/hslevel_level.sdb create mode 100644 sim/therm_chip_top/simv.daidir/hslevel_rtime_level.sdb create mode 100644 sim/therm_chip_top/simv.daidir/hsscan_cfg.dat create mode 100644 sim/therm_chip_top/simv.daidir/indcall.sdb create mode 100644 sim/therm_chip_top/simv.daidir/indcall_131020.sdb create mode 100644 sim/therm_chip_top/simv.daidir/indcall_131039.sdb create mode 100644 sim/therm_chip_top/simv.daidir/indcall_131040.sdb create mode 100644 sim/therm_chip_top/simv.daidir/nsparam.dat create mode 100644 sim/therm_chip_top/simv.daidir/pcc.sdb create mode 100644 sim/therm_chip_top/simv.daidir/pcxpxmr.dat create mode 100644 sim/therm_chip_top/simv.daidir/prof.sdb create mode 100644 sim/therm_chip_top/simv.daidir/rmapats.dat create mode 100644 sim/therm_chip_top/simv.daidir/rmapats.so create mode 100644 sim/therm_chip_top/simv.daidir/saifNetInfo.db create mode 100644 sim/therm_chip_top/simv.daidir/stitch_nsparam.dat create mode 100644 sim/therm_chip_top/simv.daidir/tt.sdb create mode 100644 sim/therm_chip_top/simv.daidir/ttIncr_131020.sdb create mode 100644 sim/therm_chip_top/simv.daidir/ttIncr_131039.sdb create mode 100644 sim/therm_chip_top/simv.daidir/ttIncr_131040.sdb create mode 100644 sim/therm_chip_top/simv.daidir/vcs_rebuild create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_hsdef.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_elab.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_fegate.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_lvl.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_name.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_hsim_uds.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_midd.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_mnmn.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_partition.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_vcselabref.db create mode 100644 sim/therm_chip_top/simv.daidir/vcselab_misc_vpdnodenums create mode 100644 sim/therm_chip_top/ucli.key create mode 100644 sim/therm_chip_top/verdiLog/.diagnose.oneSearch create mode 100644 sim/therm_chip_top/verdiLog/ToNetlist.log create mode 100644 sim/therm_chip_top/verdiLog/compiler.log create mode 100644 sim/therm_chip_top/verdiLog/exe.log create mode 100644 sim/therm_chip_top/verdiLog/novas.log create mode 100644 sim/therm_chip_top/verdiLog/novas.rc create mode 100644 sim/therm_chip_top/verdiLog/novas_autosave.ses create mode 100644 sim/therm_chip_top/verdiLog/novas_autosave.ses.config create mode 100644 sim/therm_chip_top/verdiLog/novas_autosave.ses.png create mode 100644 sim/therm_chip_top/verdiLog/novas_autosave.ses.wave.0 create mode 100644 sim/therm_chip_top/verdiLog/pes.bat create mode 100644 sim/therm_chip_top/verdiLog/turbo.log create mode 100644 sim/therm_chip_top/verdiLog/verdi.cmd create mode 100644 sim/therm_chip_top/verdiLog/verdi_perf_err.log create mode 100644 sim/therm_chip_top/wave.fsdb delete mode 100644 tb/TB.v diff --git a/rtl/digital_top.v b/rtl/digital_top.v index b657eaa..9768a3b 100644 --- a/rtl/digital_top.v +++ b/rtl/digital_top.v @@ -28,11 +28,11 @@ module digital_top( input sig_in ); -wire [31:0] w_wrdata; // DUT -> SRAM 写数据 -wire [24:0] w_addr; // DUT -> SRAM 地址 -wire w_wren; // 写使能 -wire w_rden; // 读使能 -wire [31:0] w_rddata; // SRAM -> DUT 读数据 +wire [31:0] w_wrdata; +wire [24:0] w_addr; +wire w_wren; +wire w_rden; +wire [31:0] w_rddata; wire [23:0] win_us; wire [1:0] out_mode; diff --git a/rtl/systemregfile/my_systemregfile.v b/rtl/systemregfile/my_systemregfile.v index b528b72..86eb5f1 100644 --- a/rtl/systemregfile/my_systemregfile.v +++ b/rtl/systemregfile/my_systemregfile.v @@ -1,134 +1,134 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// 增加一个新寄存器： - -// SECTION A: 添加 localparam ADDR_NEW = 16'hXX;。 - -// SECTION B: 声明 wire sel_new, we_new, [31:0] reg_new;。 - -// SECTION C: 增加译码逻辑：assign sel_new = (reg_idx == ADDR_NEW >> 2);。 - -// SECTION D: 调用底层库，例如 sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);。 - -// SECTION F: 在 always 块中加入 else if (sel_new) rddata_reg = reg_new;。 - -// SECTION G: 将 reg_new 映射给模块的输出端口。 -//-FHDR-------------------------------------------------------------------------------------------------------- - -module system_regfile ( - // [BLOCK 0] 系统与总线接口 - input clk, - input rst_n, - input [31:0] wrdata, - input wren, - input [24:0] rwaddr, - input rden, - output [31:0] rddata, - - output [23:0]win_us, - output [1:0]out_mode, //0输出对应温度， 1输出对应的频率，2单位窗口输出脉冲的个数 - output [15:0]temp_85_fre_k, //85°对应的频率,默认为600khz - output [15:0]temp_neg_40_fre_k , //-40对应的频率，默认为160khz,单位khz - output report_en, - output [23:0]rep_gap_us, //最小位win_us 小于就不上报了 - input [23:0]therm_out, - input therm_vld - -); - -// ============================================================================= -// [SECTION A] 地址偏移定义 (Localparams) -// ============================================================================= - localparam TESTR = 16'h00, DATER = 16'h04; - localparam WIN_MODE_R = 16'h08; // 配置窗口时间与输出模式 - localparam CALIB_R = 16'h0C; // 标定参数寄存器 - localparam REPORT_R = 16'h10; // 上报使能与间隔 - localparam RESULT_R = 16'h14; // 状态与结果寄存器 (只读) - - - -// ============================================================================= -// [SECTION B] 内部连线声明 (Wires) -// ============================================================================= - -// 寄存器选择信号 (Enable Wires) - wire sel_testr, sel_dater; - wire sel_win_mode, sel_calib, sel_report, sel_result; - -// 写使能信号 (Write Enable Wires) - wire we_testr, we_dater; - wire we_win_mode, we_calib, we_report; - - -// 寄存器存储连线 (Storage Wires) - wire [31:0] testr, dater; - wire [31:0] win_mode_r, calib_r, report_r, result_r; -// ============================================================================= -// [SECTION C] 译码逻辑 (Decoding) -// ============================================================================= - assign sel_testr = (rwaddr[15:0] == TESTR ); - assign sel_dater = (rwaddr[15:0] == DATER ); - assign sel_win_mode = (rwaddr[15:0] == WIN_MODE_R ); - assign sel_calib = (rwaddr[15:0] == CALIB_R ); - assign sel_report = (rwaddr[15:0] == REPORT_R ); - assign sel_result = (rwaddr[15:0] == RESULT_R ); - -// 写使能分配 -assign we_testr = sel_testr & wren; -assign we_dater = sel_dater & wren; -assign we_win_mode = sel_win_mode & wren; -assign we_calib = sel_calib & wren; -assign we_report = sel_report & wren; - - -// ============================================================================= -// [SECTION D] 寄存器实例化 (Storage Implementation) -// ============================================================================= - -// --- 通用与测试寄存器 --- -sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n); -sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n); - -// --- 温度计业务寄存器 --- -// win_mode_r: [25:24] out_mode, [23:0] win_us (默认窗口 1000us) -sirv_gnrl_dfflrd #(32) win_mode_dff (32'h0000_03E8, we_win_mode, wrdata, win_mode_r, clk, rst_n); -// calib_r: [31:16] 85度频率(默认600k), [15:0] -40度频率(默认160k) -sirv_gnrl_dfflrd #(32) calib_dff (32'h0258_00A0, we_calib, wrdata, calib_r, clk, rst_n); -// report_r: [31] report_en, [23:0] rep_gap_us (默认间隔 50ms) -sirv_gnrl_dfflrd #(32) report_dff (32'h0000_C350, we_report, wrdata, report_r, clk, rst_n); - -sirv_gnrl_dffr #(32) result_dff ({8'b0,therm_out},result_r, clk, rst_n); - -// ============================================================================= -// [SECTION E] 特殊业务逻辑 (Business Logic) -// ============================================================================= - -// LVDS 实时状态寄存器 -// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n); - -// ============================================================================= -// [SECTION F] 读回逻辑 (Readback Mux) -// ============================================================================= -reg [31:0] rddata_reg; -always @(*) begin - rddata_reg = 32'b0; - if (sel_testr) rddata_reg = testr; - else if (sel_dater) rddata_reg = dater; - else if (sel_win_mode) rddata_reg = win_mode_r; - else if (sel_calib) rddata_reg = calib_r; - else if (sel_report) rddata_reg = report_r; - else if (sel_result) rddata_reg = result_r; -end - - sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n); - -// ============================================================================= -// [SECTION G] 输出映射 (Output Assignments) -// ============================================================================= -assign win_us = win_mode_r[23:0]; -assign out_mode = win_mode_r[25:24]; -assign temp_85_fre_k = calib_r[31:16]; -assign temp_neg_40_fre_k = calib_r[15:0]; -assign report_en = report_r[31]; -assign rep_gap_us = report_r[23:0]; - +//+FHDR-------------------------------------------------------------------------------------------------------- +// Add a new register: + +// SECTION A: Add localparam ADDR_NEW = 16'hXX;. + +// SECTION B: Declare wire sel_new, we_new, [31:0] reg_new;. + +// SECTION C: Add decoding logic: assign sel_new = (reg_idx == ADDR_NEW >> 2);. + +// SECTION D: Instantiate the underlying library, e.g., sirv_gnrl_dfflr #(32) new_dff (we_new, wrdata, reg_new, clk, rst_n);. + +// SECTION F: Add else if (sel_new) rddata_reg = reg_new; in the always block. + +// SECTION G: Map reg_new to the module's output ports. +//-FHDR-------------------------------------------------------------------------------------------------------- + +module system_regfile ( + // [BLOCK 0] System and Bus Interface + input clk, + input rst_n, + input [31:0] wrdata, + input wren, + input [24:0] rwaddr, + input rden, + output [31:0] rddata, + + output [23:0]win_us, + output [1:0]out_mode, //0: output temperature, 1: output frequency, 2: output pulse count per window + output [15:0]temp_85_fre_k, //Frequency at 85¡ãC, default 600khz + output [15:0]temp_neg_40_fre_k , //Frequency at -40¡ãC, default 160khz, unit khz + output report_en, + output [23:0]rep_gap_us, //Minimum interval (us), no reporting if smaller than win_us + input [23:0]therm_out, + input therm_vld + +); + +// ============================================================================= +// [SECTION A] Address Offset Definition (Localparams) +// ============================================================================= + localparam TESTR = 16'h00, DATER = 16'h04; + localparam WIN_MODE_R = 16'h08; // Configure window time and output mode + localparam CALIB_R = 16'h0C; // Calibration parameter register + localparam REPORT_R = 16'h10; // Report enable and interval + localparam RESULT_R = 16'h14; // Status and result register (Read-only) + + + +// ============================================================================= +// [SECTION B] Internal Wire Declaration (Wires) +// ============================================================================= + +// Register selection signals (Enable Wires) + wire sel_testr, sel_dater; + wire sel_win_mode, sel_calib, sel_report, sel_result; + +// Write enable signals (Write Enable Wires) + wire we_testr, we_dater; + wire we_win_mode, we_calib, we_report; + + +// Register storage wires (Storage Wires) + wire [31:0] testr, dater; + wire [31:0] win_mode_r, calib_r, report_r, result_r; +// ============================================================================= +// [SECTION C] Decoding Logic (Decoding) +// ============================================================================= + assign sel_testr = (rwaddr[15:0] == TESTR ); + assign sel_dater = (rwaddr[15:0] == DATER ); + assign sel_win_mode = (rwaddr[15:0] == WIN_MODE_R ); + assign sel_calib = (rwaddr[15:0] == CALIB_R ); + assign sel_report = (rwaddr[15:0] == REPORT_R ); + assign sel_result = (rwaddr[15:0] == RESULT_R ); + +// Write enable allocation +assign we_testr = sel_testr & wren; +assign we_dater = sel_dater & wren; +assign we_win_mode = sel_win_mode & wren; +assign we_calib = sel_calib & wren; +assign we_report = sel_report & wren; + + +// ============================================================================= +// [SECTION D] Register Instantiation (Storage Implementation) +// ============================================================================= + +// --- General and Test Registers --- +sirv_gnrl_dfflrd #(32) testr_dff (32'h01234567, we_testr, wrdata[31:0], testr, clk, rst_n); +sirv_gnrl_dfflrd #(32) sfrtr_dff (32'h20260406, we_dater, wrdata[31:0], dater, clk, rst_n); + +// --- Thermometer Functional Registers --- +// win_mode_r: [25:24] out_mode, [23:0] win_us (Default window 1000us) +sirv_gnrl_dfflrd #(32) win_mode_dff (32'h0000_03E8, we_win_mode, wrdata, win_mode_r, clk, rst_n); +// calib_r: [31:16] Frequency at 85¡ãC (default 600k), [15:0] Frequency at -40¡ãC (default 160k) +sirv_gnrl_dfflrd #(32) calib_dff (32'h0258_00A0, we_calib, wrdata, calib_r, clk, rst_n); +// report_r: [31] report_en, [23:0] rep_gap_us (Default interval 50ms) +sirv_gnrl_dfflrd #(32) report_dff (32'h0000_C350, we_report, wrdata, report_r, clk, rst_n); + +sirv_gnrl_dffr #(32) result_dff ({8'b0,therm_out},result_r, clk, rst_n); + +// ============================================================================= +// [SECTION E] Special Business Logic (Business Logic) +// ============================================================================= + +// LVDS Real-time status register +// sirv_gnrl_dffr #(8) lvdssr_inst ({link_down, train_ready, crc_error_r, phase_adj_req_r, phase_tap[2:0], prefilling}, lvdssr, clk, rst_n); + +// ============================================================================= +// [SECTION F] Readback Logic (Readback Mux) +// ============================================================================= +reg [31:0] rddata_reg; +always @(*) begin + rddata_reg = 32'b0; + if (sel_testr) rddata_reg = testr; + else if (sel_dater) rddata_reg = dater; + else if (sel_win_mode) rddata_reg = win_mode_r; + else if (sel_calib) rddata_reg = calib_r; + else if (sel_report) rddata_reg = report_r; + else if (sel_result) rddata_reg = result_r; +end + + sirv_gnrl_dfflr #(32) rddata_out_dff (rden, rddata_reg, rddata, clk, rst_n); + +// ============================================================================= +// [SECTION G] Output Mapping (Output Assignments) +// ============================================================================= +assign win_us = win_mode_r[23:0]; +assign out_mode = win_mode_r[25:24]; +assign temp_85_fre_k = calib_r[31:16]; +assign temp_neg_40_fre_k = calib_r[15:0]; +assign report_en = report_r[31]; +assign rep_gap_us = report_r[23:0]; + endmodule \ No newline at end of file diff --git a/rtl/systemregfile/sirv_gnrl_dffs.v b/rtl/systemregfile/sirv_gnrl_dffs.v index 6526cd4..2448ae7 100644 --- a/rtl/systemregfile/sirv_gnrl_dffs.v +++ b/rtl/systemregfile/sirv_gnrl_dffs.v @@ -1,342 +1,342 @@ - /* - Copyright 2018-2020 Nuclei System Technology, Inc. - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - */ - - - -//===================================================================== -// -// Designer : Bob Hu -// -// Description: -// All of the general DFF and Latch modules -// -// ==================================================================== - -// - - -// -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is 1 -// -// =========================================================================== -`define DISABLE_SV_ASSERTION -`define dly #0.2 -module sirv_gnrl_dfflrs # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLRS_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b1}}; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is 0 -// -// =========================================================================== - -module sirv_gnrl_dfflr # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLR_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b0}}; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule - -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is input -// -// =========================================================================== - -module sirv_gnrl_dfflrd # ( - parameter DW = 32 -) ( - input [DW-1:0] init, - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLR_PROC - if (rst_n == 1'b0) - qout_r <= init; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule - -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable, no reset -// -// =========================================================================== - -module sirv_gnrl_dffl # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk -); - -reg [DW-1:0] qout_r; - -always @(posedge clk) -begin : DFFL_PROC - if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Reset, no load-enable -// Default reset value is 1 -// -// =========================================================================== - -module sirv_gnrl_dffrs # ( - parameter DW = 32 -) ( - - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFRS_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b1}}; - else - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Reset, no load-enable -// Default reset value is 0 -// -// =========================================================================== - -module sirv_gnrl_dffr # ( - parameter DW = 32 -) ( - - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFR_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b0}}; - else - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -endmodule -// =========================================================================== -// -// Description: -// Verilog module for general latch -// -// =========================================================================== - -module sirv_gnrl_ltch # ( - parameter DW = 32 -) ( - - //input test_mode, - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout -); - -reg [DW-1:0] qout_r; - -always @ * -begin : LTCH_PROC - if (lden == 1'b1) - qout_r <= dnxt; -end - -//assign qout = test_mode ? dnxt : qout_r; -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -always_comb -begin - CHECK_THE_X_VALUE: - assert (lden !== 1'bx) - else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); -end - -//synopsys translate_on -`endif//} -`endif//} - - -endmodule - -// module sirv_gnrl_edffr #(parameter type T = logic) ( -// input T dnxt, -// output T qout, -// input clk, rst_n -// ); - -// T qout_r; - -// always_ff @(posedge clk or negedge rst_n) begin -// if (!rst_n) qout_r <= T'('0); -// else qout_r <= `dly dnxt; -// end -// assign qout = qout_r; -// endmodule - + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// All of the general DFF and Latch modules +// +// ==================================================================== + +// + + +// +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 1 +// +// =========================================================================== +`define DISABLE_SV_ASSERTION +`define dly #0.2 +module sirv_gnrl_dfflrs # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dfflr # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is input +// +// =========================================================================== + +module sirv_gnrl_dfflrd # ( + parameter DW = 32 +) ( + input [DW-1:0] init, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= init; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable, no reset +// +// =========================================================================== + +module sirv_gnrl_dffl # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk +); + +reg [DW-1:0] qout_r; + +always @(posedge clk) +begin : DFFL_PROC + if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 1 +// +// =========================================================================== + +module sirv_gnrl_dffrs # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dffr # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module for general latch +// +// =========================================================================== + +module sirv_gnrl_ltch # ( + parameter DW = 32 +) ( + + //input test_mode, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout +); + +reg [DW-1:0] qout_r; + +always @ * +begin : LTCH_PROC + if (lden == 1'b1) + qout_r <= dnxt; +end + +//assign qout = test_mode ? dnxt : qout_r; +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +always_comb +begin + CHECK_THE_X_VALUE: + assert (lden !== 1'bx) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); +end + +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// module sirv_gnrl_edffr #(parameter type T = logic) ( +// input T dnxt, +// output T qout, +// input clk, rst_n +// ); + +// T qout_r; + +// always_ff @(posedge clk or negedge rst_n) begin +// if (!rst_n) qout_r <= T'('0); +// else qout_r <= `dly dnxt; +// end +// assign qout = qout_r; +// endmodule + diff --git a/rtl/digital_thermometer.v b/rtl/therm/digital_thermometer.v similarity index 67% rename from rtl/digital_thermometer.v rename to rtl/therm/digital_thermometer.v index 226ad15..5cec864 100644 --- a/rtl/digital_thermometer.v +++ b/rtl/therm/digital_thermometer.v @@ -11,11 +11,11 @@ module digital_thermometer( input rst_n, input sig_in, input [23:0]win_us, - input [1:0]out_mode, //0输出对应温度， 1输出对应的频率，2单位窗口输出脉冲的个数 - input [15:0]temp_85_fre_k, //85°对应的频率,默认为600khz - input [15:0]temp_neg_40_fre_k , //-40对应的频率，默认为160khz,单位khz - input report_en, //主动上报使能 - input [23:0]rep_gap_us, //最小位win_us + input [1:0]out_mode, //0: output temperature, 1: output frequency, 2: output pulse count per window + input [15:0]temp_85_fre_k, //Frequency at 85¡ãC, default 600khz + input [15:0]temp_neg_40_fre_k , //Frequency at -40¡ãC, default 160khz, unit khz + input report_en, //Auto report enable + input [23:0]rep_gap_us, //Minimum report gap (us) output reg [23:0]therm_out, output reg therm_vld ); @@ -23,28 +23,28 @@ module digital_thermometer( wire [23:0] wd_cnt_out; wire wd_cnt_vld; - reg [23:0] gap_cnt; // 上报间隔计数器 + reg [23:0] gap_cnt; // Report interval counter wire [23:0] cur_freq_khz; reg signed [23:0] temp_scaled; assign cur_freq_khz = (wd_cnt_out * 1000) / win_us; - //我们将温度结果放大100倍 + //Scale temperature result by 100 times always @(posedge clk or negedge rst_n) begin if (!rst_n) begin temp_scaled <= 0; end else if (wd_cnt_vld) begin - // 如果当前频率低于或等于 -40度对应的标定频率，直接输出 -4000 + //If current frequency <= calibrated frequency at -40¡ãC, output -4000 directly if (cur_freq_khz <= temp_neg_40_fre_k) begin temp_scaled <= -32'sd4000; end else begin - // 只有在频率大于下限时，才进行插值计算，避免减法溢出 + //Calculate interpolation only when frequency > lower limit to avoid subtraction overflow temp_scaled <= ((cur_freq_khz - temp_neg_40_fre_k) * 12500) / (temp_85_fre_k - temp_neg_40_fre_k) - 4000; end end end - // 上报逻辑与输出选择 + // Report logic and output selection always @(posedge clk or negedge rst_n) begin if (!rst_n) begin gap_cnt <= 0; @@ -65,11 +65,11 @@ module digital_thermometer( therm_vld <= 1'b0; end - // 模式切换输出 + //Output mode switching case (out_mode) - 2'd0: therm_out <= temp_scaled; // 输出放大100倍的温度 - 2'd1: therm_out <= cur_freq_khz; // 输出频率(kHz) - 2'd2: therm_out <= wd_cnt_out; // 输出原始脉冲计数值 + 2'd0: therm_out <= temp_scaled; //Output temperature scaled by 100 + 2'd1: therm_out <= cur_freq_khz; //Output frequency (kHz) + 2'd2: therm_out <= wd_cnt_out; //Output raw pulse count default: therm_out <= temp_scaled; endcase end @@ -79,7 +79,7 @@ module digital_thermometer( end - // 实例化被测模块 + //Instantiate sub-module pulse_cnt #( .CLK_FREQ(50_000_000) ) pulse_cnt_inst ( @@ -91,4 +91,4 @@ module digital_thermometer( .vld_out(wd_cnt_vld) ); -endmodule +endmodule \ No newline at end of file diff --git a/rtl/pulse_cnt.v b/rtl/therm/pulse_cnt.v similarity index 73% rename from rtl/pulse_cnt.v rename to rtl/therm/pulse_cnt.v index e313a37..06ee09b 100644 --- a/rtl/pulse_cnt.v +++ b/rtl/therm/pulse_cnt.v @@ -12,14 +12,13 @@ module pulse_cnt #( ); - reg [31:0] window_cnt; // 当前时钟周期计数 - reg [31:0] target_cnt; // 当前窗口所需时钟周期数 + reg [31:0] window_cnt; // Current clock cycle count + reg [31:0] target_cnt; // Required clock cycles for current measurement window - // 脉冲计数（宽度与输出一致，防止溢出） + // Pulse counter (width matches output to prevent overflow) reg [23:0] pulse_cnt; - // 标志：是否正在计算新的 target_cnt（避免组合逻辑环路） - reg calc_done; + reg sig_sync1, sig_sync2, sig_sync3; wire sig_rise = sig_sync2 & ~sig_sync3; @@ -30,7 +29,7 @@ module pulse_cnt #( sig_sync3 <= sig_sync2; end - // 主控制逻辑 + // Main control logic always @(posedge clk or negedge rst_n) begin if (!rst_n) begin window_cnt <= 0; @@ -42,11 +41,11 @@ module pulse_cnt #( end else begin vld_out <= 1'b0; target_cnt <= ( {40'd0, win_us} * CLK_FREQ) / 1_000_000 ; - // 窗口计数结束条件：当前计数值到达 target_cnt + // Window count end condition: current count reaches target_cnt if (window_cnt >= target_cnt) begin cnt_out <= pulse_cnt; vld_out <= 1'b1; - // 复位窗口计数器与脉冲计数器，并触发重新计算目标值 + // Reset window counter and pulse counter, trigger target value recalculation window_cnt <= 0; pulse_cnt <= 0; end else begin diff --git a/rtl/uart_byte_rx.v b/rtl/uart/uart_byte_rx.v similarity index 100% rename from rtl/uart_byte_rx.v rename to rtl/uart/uart_byte_rx.v diff --git a/rtl/uart_byte_tx.v b/rtl/uart/uart_byte_tx.v similarity index 100% rename from rtl/uart_byte_tx.v rename to rtl/uart/uart_byte_tx.v diff --git a/rtl/uart_ctrl_sysreg.v b/rtl/uart/uart_ctrl_sysreg.v similarity index 72% rename from rtl/uart_ctrl_sysreg.v rename to rtl/uart/uart_ctrl_sysreg.v index c233384..6331c58 100644 --- a/rtl/uart_ctrl_sysreg.v +++ b/rtl/uart/uart_ctrl_sysreg.v @@ -6,16 +6,16 @@ module uart_ctrl_sysreg #( )( input clk ,input rst_n - // 串口接口 + // UART Interface ,input uart_rx ,output uart_tx - //5口 - ,output reg [31:0] o_wrdata //write data to sram - ,output reg [24:0] o_addr //sram address - ,output reg o_wren //write enable sram - ,output reg o_rden //rden enable sram - ,input [31:0] i_rddata //read data from sram - //主动上报机制 + // Register File Interface + ,output reg [31:0] o_wrdata //write data to register file + ,output reg [24:0] o_addr //register file address + ,output reg o_wren //write enable to register file + ,output reg o_rden //read enable to register file + ,input [31:0] i_rddata //read data from register file + // Auto-Report Mechanism ,input [23:0] i_report_data ,input i_report_vld ); @@ -37,12 +37,12 @@ module uart_ctrl_sysreg #( ); - // 协议解析寄存器 + // Protocol parsing registers reg [63:0] cmd_reg; - reg [31:0]wr_data_buff; + reg [31:0] wr_data_buff; reg [19:0] data_bytes_len; - // 状态机定义 + // State machine definition reg [2:0] state; localparam S_IDLE = 3'd0, S_RX_CMD_L = 3'd1, @@ -50,14 +50,14 @@ module uart_ctrl_sysreg #( S_WAIT_RD = 3'd3, S_RD_DATA = 3'd4, S_WR_DATA = 3'd5, - S_REPORT = 3'd6; //主动上报状态 + S_REPORT = 3'd6; // Auto-report state -// --- 主动上报数据先锁存着 --- +// Latch auto-report data reg [23:0] report_data_latch; reg report_pending; - // 捕捉上报脉冲：如果当前忙，先存起来 + // Capture report pulse: store if busy always @(posedge clk or negedge rst_n) begin if(!rst_n) begin report_pending <= 1'b0; @@ -66,7 +66,7 @@ module uart_ctrl_sysreg #( report_pending <= 1'b1; report_data_latch <= i_report_data; end else if(state == S_REPORT) begin - report_pending <= 1'b0; // 进入上报状态后清除标志 + report_pending <= 1'b0; // Clear flag after entering report state end end @@ -83,7 +83,7 @@ module uart_ctrl_sysreg #( end else begin case(state) - S_IDLE : begin //0 + S_IDLE : begin // IDLE state uart_tx_go <= 1'b0; if(uart_rx_done) begin cmd_reg[63:32] <= uart_rx_data; @@ -93,33 +93,33 @@ module uart_ctrl_sysreg #( state <= S_REPORT; end end - S_RX_CMD_L : begin //1 + S_RX_CMD_L : begin // Receive lower command word if(uart_rx_done)begin cmd_reg[31:0] <= uart_rx_data; state <= S_PARSE; end end - S_PARSE : begin //2 + S_PARSE : begin // Parse command o_addr <= cmd_reg[56:32]; data_bytes_len <= cmd_reg[19:0]; - if(cmd_reg[63] == 1'b1) begin //读指令 + if(cmd_reg[63] == 1'b1) begin // Read command o_rden <= 1'b1; state <= S_WAIT_RD; end - else begin //写指令 + else begin // Write command state <= S_WR_DATA; end end - S_WAIT_RD : begin //3 + S_WAIT_RD : begin // Wait for read data ready o_rden <= 1'b0; state <= S_RD_DATA; end - S_RD_DATA :begin //4 + S_RD_DATA :begin // Transmit read data uart_tx_data <= i_rddata; uart_tx_go <= 1'b1; state <= S_IDLE; end - S_WR_DATA : begin //5 + S_WR_DATA : begin // Receive and write data o_wren <= 1'b0; if(data_bytes_len != 0)begin if(uart_rx_done) begin @@ -132,8 +132,8 @@ module uart_ctrl_sysreg #( state <= S_IDLE; end end - S_REPORT : begin //6 - // 构造上报数据包，例如：[8'hAA (帧头) + 24'bit温度数据] + S_REPORT : begin // Auto-report data + // Construct report packet: [8'hAA (header) + 24bit sensor data] uart_tx_data <= {8'hAA, report_data_latch}; uart_tx_go <= 1'b1; state <= S_IDLE; @@ -148,6 +148,4 @@ module uart_ctrl_sysreg #( - - endmodule \ No newline at end of file diff --git a/rtl/uart_top_32bit.v b/rtl/uart/uart_top_32bit.v similarity index 74% rename from rtl/uart_top_32bit.v rename to rtl/uart/uart_top_32bit.v index f5574ed..5bd57b0 100644 --- a/rtl/uart_top_32bit.v +++ b/rtl/uart/uart_top_32bit.v @@ -16,19 +16,19 @@ module uart_top_32bit #( input Clk, input Reset_n, - // 32位发送接口 - input Send_Go32, // 32位发送启动脉冲 - input [31:0] Tx_Data32, // 待发送的32位数据 - output Tx_Done32, // 32位发送完成标志 - output uart_tx, // 物理引脚TX + // 32-bit Transmit Interface + input Send_Go32, // 32-bit transmit start pulse + input [31:0] Tx_Data32, // 32-bit data to transmit + output Tx_Done32, // 32-bit transmit done flag + output uart_tx, // Physical TX pin - // 32位接收接口 - input uart_rx, // 物理引脚RX - output reg Rx_Done32, // 32位接收完成标志 - output reg [31:0] Rx_Data32 // 接收到的32位数据 + // 32-bit Receive Interface + input uart_rx, // Physical RX pin + output reg Rx_Done32, // 32-bit receive done flag + output reg [31:0] Rx_Data32 // 32-bit received data ); - // --- 内部连线 --- + // --- Internal Wires --- wire byte_tx_go; wire [7:0] byte_tx_data; wire byte_tx_done; @@ -37,7 +37,7 @@ module uart_top_32bit #( wire [7:0] byte_rx_data; // ============================================================ - // 1. 发送逻辑控制 (32-bit to 4x8-bit) + // 1. Transmit Control Logic (32-bit to 4x8-bit) // ============================================================ reg [3:0] tx_state; reg [31:0] tx_data_buffer; @@ -54,26 +54,26 @@ module uart_top_32bit #( tx_data_buffer <= 0; end else begin case (tx_state) - 0: begin // 等待发送触发 + 0: begin // Wait for transmit trigger if (Send_Go32) begin tx_data_buffer <= Tx_Data32; tx_state <= 1; end end - 1, 2, 3, 4: begin // 依次发送字节0, 1, 2, 3 - byte_tx_data_reg <= tx_data_buffer[31:24]; // 优先发高位置(大端) + 1, 2, 3, 4: begin // Send byte 0, 1, 2, 3 sequentially + byte_tx_data_reg <= tx_data_buffer[31:24]; // Send high byte first (Big-endian) byte_tx_go_reg <= 1; - tx_state <= tx_state + 4; // 跳转到等待状态 (利用加法偏移) + tx_state <= tx_state + 4; // Jump to wait state end - // 状态 5, 6, 7, 8 用于等待 byte_tx_done + // States 5, 6, 7, 8: Wait for byte_tx_done 5, 6, 7, 8: begin byte_tx_go_reg <= 0; if (byte_tx_done) begin - tx_data_buffer <= tx_data_buffer << 8; // 移位，准备下一字节 - if (tx_state == 8) tx_state <= 0; // 发完4个 - else tx_state <= tx_state - 3; // 回到下一个发送状态 + tx_data_buffer <= tx_data_buffer << 8; // Shift for next byte + if (tx_state == 8) tx_state <= 0; // 4 bytes sent + else tx_state <= tx_state - 3; // Return to next send state end end endcase @@ -83,7 +83,7 @@ module uart_top_32bit #( assign Tx_Done32 = (tx_state == 8 && byte_tx_done); // ============================================================ - // 2. 接收逻辑控制 (4x8-bit to 32-bit) + // 2. Receive Control Logic (4x8-bit to 32-bit) // ============================================================ reg [1:0] rx_cnt; reg [31:0] rx_data_buffer; @@ -97,7 +97,7 @@ module uart_top_32bit #( end else begin rx_done32_reg <= 0; if (byte_rx_done) begin - // 拼接数据 (大端模式) + // Concatenate data (Big-endian mode) case(rx_cnt) 0: rx_data_buffer[31:24] <= byte_rx_data; 1: rx_data_buffer[23:16] <= byte_rx_data; @@ -116,7 +116,7 @@ module uart_top_32bit #( end - always @(posedge Clk or Reset_n) begin + always @(posedge Clk or negedge Reset_n) begin if(!Reset_n) begin Rx_Data32 <= 1'b0; Rx_Done32 <= 1'b0; @@ -132,10 +132,10 @@ module uart_top_32bit #( end // ============================================================ - // 3. 模块实例化 + // 3. Module Instantiation // ============================================================ - // 实例化发送字节模块 + // Instantiate byte transmit module uart_byte_tx #( .BAUD(BAUD), .CLOCK_FREQ(CLOCK_FREQ) @@ -148,7 +148,7 @@ module uart_top_32bit #( .Tx_Done(byte_tx_done) ); - // 实例化接收字节模块 + // Instantiate byte receive module uart_byte_rx #( .BAUD(BAUD), .CLOCK_FREQ(CLOCK_FREQ) @@ -160,4 +160,4 @@ module uart_top_32bit #( .Rx_Data(byte_rx_data) ); -endmodule +endmodule \ No newline at end of file diff --git a/sim/therm_chip_top/Makefile b/sim/therm_chip_top/Makefile new file mode 100644 index 0000000..d594bea --- /dev/null +++ b/sim/therm_chip_top/Makefile @@ -0,0 +1,74 @@ + +WAVE ?= 0 + +SIM = RTL + +folder = simv + +ifeq ($(WAVE),1) + WAVE_OPTS = -debug_access+all -debug_region+cell+encrypt -P $(NOVAS_HOME)/share/PLI/VCS/linux64/novas_new_dumper.tab $(NOVAS_HOME)/share/PLI/VCS/linux64/pli.a +define+DUMP_FSDB + WAVE_SIM_OPTS = -fsdbDumpfile=sim.fsdb + else + WAVE_OPTS = -debug_access+pp +endif + +ifeq ($(SIM),PostPr) +VCS = vcs -full64 -sverilog -Mupdate +lint=TFIPC-L +v2k +warn=noSDFCOM_IWSBA,noNTCDNC -notice +mindelays +tchk+edge+warn +neg_tchk -negdelay +overlap +sdfverbose -sdfretain +optconfigfile+notimingcheck.cfg -override_timescale=1ns/1ps -debug_access+all $(WAVE_OPTS) -lca -q -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb |tee +else +VCS = vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k $(WAVE_OPTS) -lca -q -timescale=1ns/1ps +nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb +endif + +ifeq ($(SIM),PostPr) + post_dir = ./data_PostPr +else + post_dir = ./data_PostSyn +endif + + +ifeq ($(SIM),PostSyn) +FileList = filelist_syn.f +else + ifeq ($(SIM),PostPr) + FileList = filelist_pr.f + else + FileList = filelist_vlg.f + endif +endif + +SIMV = ./simv sync:busywait $(WAVE_SIM_OPTS) -l |tee sim.log + +all:comp run dbg +rsim: comp run + +comp: +# ${VCS} -f $(FileList) +incdir+./../../rtl/define +incdir+./../../rtl/qubitmcu +incdir+./../../model + ${VCS} -f $(FileList) + +run: + ${SIMV} + +dbg: + verdi -sverilog -f $(FileList) -top TB -ssf *.fsdb -nologo & + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *fsdb* *.dat *.daidir *.vdb *~ + +compare: + ./compare_files.csh ${post_dir} ./data_RTL ./compare.txt + +regress: + ./regress.csh $(SIM) + +rmwork: + rm -rf ./work* + +rmdata: + rm -rf ./data* +cov: + verdi -cov -covdir coverage/merged.vdb & +cov_d: + dve -full64 -covdir coverage/*.vdb & +merge: + urg -full64 -dbname coverage/merged.vdb -flex_merge union -dir coverage/simv.vdb -parallel -maxjobs 64& +merge_i: + urg -full64 -flex_merge union -dir coverage/merged.vdb -dir coverage/$(folder) -dbname coverage/merged.vdb -parallel -maxjobs 64& diff --git a/sim/therm_chip_top/TB.sv b/sim/therm_chip_top/TB.sv new file mode 100644 index 0000000..73c806b --- /dev/null +++ b/sim/therm_chip_top/TB.sv @@ -0,0 +1,224 @@ +`timescale 1ns / 1ps + +module TB(); + + // ========================================== + // Parameters & Signal Definitions + // ========================================== + parameter CLK_PERIOD = 20; // 50MHz + parameter BAUD = 115200; + localparam BIT_TIME = 1_000_000_000 / BAUD; + + reg clk; + reg rst_n; + reg uart_rx; // DUT RX + wire uart_tx; // DUT TX + reg sig_in; + + // Clock Generation + initial clk = 0; + always #(CLK_PERIOD/2) clk = ~clk; + initial begin + $fsdbDumpfile("wave.fsdb"); + $fsdbDumpvars(); + end + // ========================================== + // DUT Instantiation + // ========================================== + digital_top u_digital_top( + .clk (clk), + .rst_n (rst_n), + .uart_rx (uart_rx), + .uart_tx (uart_tx), + .sig_in (sig_in) + ); + + + // // ========================================== + // // TX Driver: Read from case.txt + // // ========================================== + // initial begin + // int file_h; + // int status; + // logic [63:0] val; + + // // Initialize signals + // rst_n = 0; + // uart_rx = 1; + // #(CLK_PERIOD * 10); + // rst_n = 1; + // file_h = $fopen("case.txt", "r"); + // if (!file_h) begin + // $display("[TX ERROR] Cannot open case.txt"); + // $finish; + // end + + // $display("[TX] Starting transmission..."); + + // while (!$feof(file_h)) begin + // // Read hex data per line + // status = $fscanf(file_h, "%h\n", val); + // if (status == 1) begin + // if (val > 64'hFFFF_FFFF) begin + // $display("[%t] TX CMD: %h", $time, val); + // send_data(val, 64); + // end else begin + // $display("[%t] TX DATA: %h", $time, val[31:0]); + // send_data(val[31:0], 32); + // end + // #(BIT_TIME * 5); // Frame gap + // } + // end + + // $fclose(file_h); + // $display("[TX] All cases sent."); + + // // Wait for RX return data + // #(BIT_TIME * 500); + // $display("[SIM] Simulation finished."); + // $finish; + // end + + + + // ========================================== + // RX Monitor: Save to rx_data.txt + // ========================================== + int rx_file_h; + initial begin + + logic [7:0] rx_byte; + + rx_file_h = $fopen("rx_data.txt", "w"); + if (!rx_file_h) begin + $display("[RX ERROR] Cannot create rx_data.txt"); + $finish; + end + + forever begin + logic [31:0] packet_word; // 32-bit data packet + logic [7:0] rx_byte; + // Collect 4 bytes to form 32-bit data + for (int byte_idx = 0; byte_idx < 4; byte_idx++) begin + // 1. Wait for start bit (falling edge) + @(negedge uart_tx); + // 2. Skip start bit, sample at center point + #(BIT_TIME / 2); + #(BIT_TIME); + // Read 8 data bits + for (int i = 0; i < 8; i++) begin + rx_byte[i] = uart_tx; + #(BIT_TIME); + end + // Combine to 32-bit (little-endian) + packet_word[24 - 8*byte_idx +: 8] = rx_byte; + $display("[%t] Byte %0d: 0x%h", $time, byte_idx, rx_byte); + // Wait for end of stop bit + if (byte_idx < 3) begin + #(BIT_TIME / 2); + end + end + + // Write to file (one 32-bit data per line) + $fdisplay(rx_file_h, "%08h", packet_word); + $display("[%t] Packet (32-bit): 0x%08h", $time, packet_word); + // Wait for end of last stop bit + #(BIT_TIME / 2); + end + end + + final begin + if (rx_file_h) begin + $fclose(rx_file_h); + $display("[RX] File closed at %t",$time); + end + end + + // --- Pulse Generation Task --- + // freq_khz: Target frequency (kHz) + // duration_ms: Test duration (ms) + task automatic gen_pulses(input int freq_khz, input int duration_ms); + int half_period_ns; + longint end_time_ns; + begin + if (freq_khz <= 0) begin + sig_in = 0; + #(duration_ms * 1000000); + end else begin + half_period_ns = 500000 / freq_khz; + end_time_ns = $time + (longint'(duration_ms) * 1000000); + + $display("[%0t] Start generating signal: %0d kHz", $time, freq_khz); + while ($time < end_time_ns) begin + sig_in = 1; + #(half_period_ns); + sig_in = 0; + #(half_period_ns); + end + end + end + endtask + + // ========================================== + // Task: Send one byte (Serial TX) + // ========================================== + task automatic send_byte(input [7:0] data); + begin + uart_rx = 0; // Start bit + #(BIT_TIME); + for (int i = 0; i < 8; i++) begin + uart_rx = data[i]; // LSB First + #(BIT_TIME); + end + uart_rx = 1; // Stop bit + #(BIT_TIME); + end + endtask + + // Task: Send 32/64 bit data + task automatic send_data(input [63:0] data, input int len_bits); + int bytes = len_bits / 8; + for (int i = bytes - 1; i >= 0; i--) begin // Send from highest byte + send_byte(data[i*8 +: 8]); + end + endtask + + initial begin + // 1. Initialization + rst_n = 0; uart_rx = 1; sig_in = 0; + #(CLK_PERIOD * 20); + rst_n = 1; + #(CLK_PERIOD * 100); + $display("------- Step 1: Configure Thermometer Regs -------"); + send_data(64'h80000004_00000004,64); + send_data(64'h80000008_00000004,64); + send_data(64'h8000000c_00000004,64); + send_data(64'h80000010_00000004,64); + send_data(64'h80000014_00000004,64); + + + $display("------- Step 2: Running Concurrent Tasks -------"); + fork + // Process A: Generate input pulses (simulate temperature change) + begin + gen_pulses(400, 10); // 100kHz for 10ms + end + + // Process B: Insert read command during reporting + begin + #(2_000000); // Wait for first report packet + $display("[%t] TX: Sending Read Request during active reporting...", $time); + send_data(64'h80000014_00000004,64); + send_data(64'h00000010_00000004,64);send_data(32'h8000_06e8,32); + send_data(64'h00000010_00000004,64);send_data(32'h0000_06e8,32); + #30000; + send_data(64'h80000014_00000004,64); + end + join + + #(BIT_TIME * 500); + $display("Test Done."); + $finish; + end + +endmodule \ No newline at end of file diff --git a/sim/therm_chip_top/compile.log b/sim/therm_chip_top/compile.log new file mode 100644 index 0000000..8855fd6 --- /dev/null +++ b/sim/therm_chip_top/compile.log @@ -0,0 +1,20 @@ +Command: vcs -full64 -j8 -sverilog +lint=TFIPC-L +v2k -debug_access+pp -lca -q -timescale=1ns/1ps \ ++nospecify -l compile.log -cm line+cond+fsm+tgl+branch -cm_dir ./coverage/simv.vdb \ +-f filelist_vlg.f + +Warning-[LCA_FEATURES_ENABLED] Usage warning + LCA features enabled by '-lca' argument on the command line. For more + information regarding list of LCA features please refer to Chapter "LCA + features" in the VCS/VCS-MX Release Notes + +VCS Coverage Metrics Release O-2018.09-SP2_Full64 Copyright (c) 1991-2018 by Synopsys Inc. + +Note-[VCS_PARAL] Parallel code-gen enabled + VCS is running with parallel code generation(-j)... + +6 modules and 0 UDP read. +make[1]: Entering directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \ + +../simv up to date +make[1]: Leaving directory `/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/csrc' \ + diff --git a/sim/therm_chip_top/coverage/simv.vdb/.cmoptions b/sim/therm_chip_top/coverage/simv.vdb/.cmoptions new file mode 100644 index 0000000..aa3c928 --- /dev/null +++ b/sim/therm_chip_top/coverage/simv.vdb/.cmoptions @@ -0,0 +1,16 @@ +Instrument +cond 3 +line 3 +fsm 65539 +tgl 8 +assign 0 +obc 0 +path 0 +branch 3 +Count 0 +Glitch -1 +cm_tglmda 0 +cm_tglstructarr 0 +cm_tglcount 0 +cm_hier 0 +cm_assert_hier 0 \ No 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+// - in specifying the transitions you can use * in order to refer to 'any' state. +// ================================================================================================== +// Uncomment and modify the following 2 line to override default FSM sequence limits for all FSMs in the design. +//SEQ_NUMBER_MAX=10000 +//SEQ_LENGTH_MAX=32 + +MODULE=uart_ctrl_sysreg +CURRENT=state +NEXT=state +STATES=S_IDLE,S_PARSE,S_RD_DATA,S_REPORT,S_RX_CMD_L,S_WAIT_RD,S_WR_DATA,'h0 +TRANSITIONS=S_IDLE->'h0, +S_IDLE->S_REPORT, +S_IDLE->S_RX_CMD_L, +S_PARSE->'h0, +S_PARSE->S_WAIT_RD, +S_PARSE->S_WR_DATA, +S_RD_DATA->'h0, +S_RD_DATA->S_IDLE, +S_REPORT->'h0, +S_REPORT->S_IDLE, +S_RX_CMD_L->'h0, +S_RX_CMD_L->S_PARSE, +S_WAIT_RD->'h0, +S_WAIT_RD->S_RD_DATA, +S_WR_DATA->'h0, +S_WR_DATA->S_IDLE, +'h0->S_IDLE diff --git a/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml b/sim/therm_chip_top/coverage/simv.vdb/snps/coverage/db/shape/fsm.verilog.shape.xml new file mode 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file. If product is newer than this one, +# we will also re-link the product. +PRODUCT_TIMESTAMP=product_timestamp + +# Path to runtime library +DEPLIBS= +VCSUCLI=-lvcsucli +RUNTIME=-lvcsnew -lsimprofile -lreader_common /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libBA.a -luclinative /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_tls.o $(DEPLIBS) + +VCS_SAVE_RESTORE_OBJ=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ + +# Strip Flags for target product +STRIPFLAGS= + +PRE_LDFLAGS= # Loader Flags +LDFLAGS= -rdynamic -Wl,-rpath=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib -L/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib +# Picarchive Flags +PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir + +# C run time startup +CRT0= +# C run time startup +CRTN= +# Machine specific libraries +SYSLIBS=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + +CFLAGS_O0=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O0 -fno-strict-aliasing + +CFLAGS_CG=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O -fno-strict-aliasing + +LD_PARTIAL_LOADER=ld +# Partial linking +LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o +ASFLAGS= +LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs +# Note: if make gives you errors about include, either get gmake, or +# replace the following line with the contents of the file filelist, +# EACH TIME IT CHANGES +# included file defines OBJS, and is automatically generated by vcs +include filelist + +OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS) + +product : $(PRODUCT_TIMESTAMP) + @echo $(PRODUCT) up to date + +objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) + +clean : + rm -f $(VCS_OBJS) $(CU_OBJS) + +clobber : clean + rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP) + +picclean : + @rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so + @rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null + +product_clean_order : + @$(MAKE) -f Makefile --no-print-directory picclean + @$(MAKE) -f Makefile --no-print-directory product_order + +product_order : $(PRODUCT) + +$(PRODUCT_TIMESTAMP) : product_clean_order + @-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi + @$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN) + @rm -f csrc[0-9]*.o + @touch $(PRODUCT_TIMESTAMP) + @-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi + +$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvcsnew.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsimprofile.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libreader_common.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libBA.a /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libuclinative.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_tls.o /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ) + @touch $(PRODUCT) + diff --git a/sim/therm_chip_top/csrc/Makefile.hsopt b/sim/therm_chip_top/csrc/Makefile.hsopt new file mode 100644 index 0000000..dcb7127 --- /dev/null +++ b/sim/therm_chip_top/csrc/Makefile.hsopt @@ -0,0 +1,47 @@ +# Makefile generated by VCS to build rmapats.so for your model +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc + +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ +# Loader Flags +LDFLAGS= + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + +CFLAGS_CG=-w -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -O -fno-strict-aliasing + +ASFLAGS= +LIBS= + +include filelist.hsopt + + +rmapats.so: $(HSOPT_OBJS) + @$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS) diff --git a/sim/therm_chip_top/csrc/SIM_l.o b/sim/therm_chip_top/csrc/SIM_l.o new file mode 100644 index 0000000000000000000000000000000000000000..8fd683e07e3e2bd62531d7fae3f6d84b443a6136 GIT binary patch literal 558 zcmb<-^>JfjWMqH=Mg}_u1P><4z_1R%WN-kp9T?a^D)ovpic5-05|e-|7+skQ<`)#@ zr)B1)G3ccvmLxJT9%RKpHoAUcpcoUH8W6V(DrNwsL25vHS)hCgC@l>YhjQW6GB^vB Zfo{JFP#PqL?gyBD4ybmRJd6)B6#y^y7>)n{ literal 0 HcmV?d00001 diff --git a/sim/therm_chip_top/csrc/_131020_archive_1.so b/sim/therm_chip_top/csrc/_131020_archive_1.so new file mode 120000 index 0000000..3e06bf7 --- /dev/null +++ b/sim/therm_chip_top/csrc/_131020_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131020_archive_1.so \ No newline at end of file diff --git a/sim/therm_chip_top/csrc/_131039_archive_1.so b/sim/therm_chip_top/csrc/_131039_archive_1.so new file mode 120000 index 0000000..bcc14ae --- /dev/null +++ b/sim/therm_chip_top/csrc/_131039_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131039_archive_1.so \ No newline at end of file diff --git a/sim/therm_chip_top/csrc/_131040_archive_1.so b/sim/therm_chip_top/csrc/_131040_archive_1.so new file mode 120000 index 0000000..cd1589e --- /dev/null +++ b/sim/therm_chip_top/csrc/_131040_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_131040_archive_1.so \ No newline at end of file diff --git a/sim/therm_chip_top/csrc/_vcs_pli_stub_.c b/sim/therm_chip_top/csrc/_vcs_pli_stub_.c new file mode 100644 index 0000000..e4d8eaa --- /dev/null +++ b/sim/therm_chip_top/csrc/_vcs_pli_stub_.c @@ -0,0 +1,964 @@ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* VCS_dlsymLookup(const char *); +extern void vcsMsgReportNoSource1(const char *, const char*); + +/* PLI routine: $fsdbDumpvars:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars +#define __VCS_PLI_STUB_novas_call_fsdbDumpvars +extern void novas_call_fsdbDumpvars(int data, int reason); +#pragma weak novas_call_fsdbDumpvars +void novas_call_fsdbDumpvars(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */ + +/* PLI routine: $fsdbDumpvars:misc */ +#ifndef __VCS_PLI_STUB_novas_misc +#define __VCS_PLI_STUB_novas_misc +extern void novas_misc(int data, int reason, int iparam ); +#pragma weak novas_misc +void novas_misc(int data, int reason, int iparam ) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason, iparam ); + } +} +void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc; +#endif /* __VCS_PLI_STUB_novas_misc */ + +/* PLI routine: $fsdbDumpvarsByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +extern void novas_call_fsdbDumpvarsByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpvarsByFile +void novas_call_fsdbDumpvarsByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */ + +/* PLI routine: $fsdbAddRuntimeSignal:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +extern void novas_call_fsdbAddRuntimeSignal(int data, int reason); +#pragma weak novas_call_fsdbAddRuntimeSignal +void novas_call_fsdbAddRuntimeSignal(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal; +#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */ + +/* PLI routine: $sps_create_transaction_stream:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +extern void novas_call_sps_create_transaction_stream(int data, int reason); +#pragma weak novas_call_sps_create_transaction_stream +void novas_call_sps_create_transaction_stream(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream; +#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */ + +/* PLI routine: $sps_begin_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction +#define __VCS_PLI_STUB_novas_call_sps_begin_transaction +extern void novas_call_sps_begin_transaction(int data, int reason); +#pragma weak novas_call_sps_begin_transaction +void novas_call_sps_begin_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */ + +/* PLI routine: $sps_end_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction +#define __VCS_PLI_STUB_novas_call_sps_end_transaction +extern void novas_call_sps_end_transaction(int data, int reason); +#pragma weak novas_call_sps_end_transaction +void novas_call_sps_end_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */ + +/* PLI routine: $sps_free_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction +#define __VCS_PLI_STUB_novas_call_sps_free_transaction +extern void novas_call_sps_free_transaction(int data, int reason); +#pragma weak novas_call_sps_free_transaction +void novas_call_sps_free_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */ + +/* PLI routine: $sps_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute +#define __VCS_PLI_STUB_novas_call_sps_add_attribute +extern void novas_call_sps_add_attribute(int data, int reason); +#pragma weak novas_call_sps_add_attribute +void novas_call_sps_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */ + +/* PLI routine: $sps_update_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_update_label +#define __VCS_PLI_STUB_novas_call_sps_update_label +extern void novas_call_sps_update_label(int data, int reason); +#pragma weak novas_call_sps_update_label +void novas_call_sps_update_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label; +#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */ + +/* PLI routine: $sps_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation +#define __VCS_PLI_STUB_novas_call_sps_add_relation +extern void novas_call_sps_add_relation(int data, int reason); +#pragma weak novas_call_sps_add_relation +void novas_call_sps_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */ + +/* PLI routine: $fsdbWhatif:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif +#define __VCS_PLI_STUB_novas_call_fsdbWhatif +extern void novas_call_fsdbWhatif(int data, int reason); +#pragma weak novas_call_fsdbWhatif +void novas_call_fsdbWhatif(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif; +#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */ + +/* PLI routine: $paa_init:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_init +#define __VCS_PLI_STUB_novas_call_paa_init +extern void novas_call_paa_init(int data, int reason); +#pragma weak novas_call_paa_init +void novas_call_paa_init(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init; +#endif /* __VCS_PLI_STUB_novas_call_paa_init */ + +/* PLI routine: $paa_sync:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_sync +#define __VCS_PLI_STUB_novas_call_paa_sync +extern void novas_call_paa_sync(int data, int reason); +#pragma weak novas_call_paa_sync +void novas_call_paa_sync(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync; +#endif /* __VCS_PLI_STUB_novas_call_paa_sync */ + +/* PLI routine: $fsdbDumpClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +extern void novas_call_fsdbDumpClassMethod(int data, int reason); +#pragma weak novas_call_fsdbDumpClassMethod +void novas_call_fsdbDumpClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */ + +/* PLI routine: $fsdbSuppressClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +extern void novas_call_fsdbSuppressClassMethod(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassMethod +void novas_call_fsdbSuppressClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */ + +/* PLI routine: $fsdbSuppressClassProp:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +extern void novas_call_fsdbSuppressClassProp(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassProp +void novas_call_fsdbSuppressClassProp(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */ + +/* PLI routine: $fsdbDumpMDAByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +extern void novas_call_fsdbDumpMDAByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpMDAByFile +void novas_call_fsdbDumpMDAByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */ + +/* PLI routine: $fsdbTrans_create_stream_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_begin +void novas_call_fsdbEvent_create_stream_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */ + +/* PLI routine: $fsdbTrans_define_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_stream_attribute +void novas_call_fsdbEvent_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_create_stream_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +extern void novas_call_fsdbEvent_create_stream_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_end +void novas_call_fsdbEvent_create_stream_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */ + +/* PLI routine: $fsdbTrans_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin +extern void novas_call_fsdbEvent_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_begin +void novas_call_fsdbEvent_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */ + +/* PLI routine: $fsdbTrans_set_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +extern void novas_call_fsdbEvent_set_label(int data, int reason); +#pragma weak novas_call_fsdbEvent_set_label +void novas_call_fsdbEvent_set_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */ + +/* PLI routine: $fsdbTrans_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +extern void novas_call_fsdbEvent_add_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_attribute +void novas_call_fsdbEvent_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */ + +/* PLI routine: $fsdbTrans_add_tag:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +extern void novas_call_fsdbEvent_add_tag(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_tag +void novas_call_fsdbEvent_add_tag(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */ + +/* PLI routine: $fsdbTrans_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_end +extern void novas_call_fsdbEvent_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_end +void novas_call_fsdbEvent_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */ + +/* PLI routine: $fsdbTrans_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +extern void novas_call_fsdbEvent_add_relation(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_relation +void novas_call_fsdbEvent_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */ + +/* PLI routine: $fsdbTrans_get_error_code:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +extern void novas_call_fsdbEvent_get_error_code(int data, int reason); +#pragma weak novas_call_fsdbEvent_get_error_code +void novas_call_fsdbEvent_get_error_code(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */ + +/* PLI routine: $fsdbTrans_add_stream_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_stream_attribute +void novas_call_fsdbTrans_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_add_scope_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_scope_attribute +void novas_call_fsdbTrans_add_scope_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */ + +/* PLI routine: $sps_interactive:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_interactive +#define __VCS_PLI_STUB_novas_call_sps_interactive +extern void novas_call_sps_interactive(int data, int reason); +#pragma weak novas_call_sps_interactive +void novas_call_sps_interactive(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive; +#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */ + +/* PLI routine: $sps_test:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_test +#define __VCS_PLI_STUB_novas_call_sps_test +extern void novas_call_sps_test(int data, int reason); +#pragma weak novas_call_sps_test +void novas_call_sps_test(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test; +#endif /* __VCS_PLI_STUB_novas_call_sps_test */ + +/* PLI routine: $fsdbDumpClassObject:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +extern void novas_call_fsdbDumpClassObject(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObject +void novas_call_fsdbDumpClassObject(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */ + +/* PLI routine: $fsdbDumpClassObjectByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObjectByFile +void novas_call_fsdbDumpClassObjectByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */ + +/* PLI routine: $ridbDump:call */ +#ifndef __VCS_PLI_STUB_novas_call_ridbDump +#define __VCS_PLI_STUB_novas_call_ridbDump +extern void novas_call_ridbDump(int data, int reason); +#pragma weak novas_call_ridbDump +void novas_call_ridbDump(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump; +#endif /* __VCS_PLI_STUB_novas_call_ridbDump */ + +/* PLI routine: $sps_flush_file:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file +#define __VCS_PLI_STUB_novas_call_sps_flush_file +extern void novas_call_sps_flush_file(int data, int reason); +#pragma weak novas_call_sps_flush_file +void novas_call_sps_flush_file(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file; +#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */ + +/* PLI routine: $fsdbDumpSingle:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle +#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle +extern void novas_call_fsdbDumpSingle(int data, int reason); +#pragma weak novas_call_fsdbDumpSingle +void novas_call_fsdbDumpSingle(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */ + +/* PLI routine: $fsdbDumpIO:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO +#define __VCS_PLI_STUB_novas_call_fsdbDumpIO +extern void novas_call_fsdbDumpIO(int data, int reason); +#pragma weak novas_call_fsdbDumpIO +void novas_call_fsdbDumpIO(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */ + +#ifdef __cplusplus +} +#endif diff --git a/sim/therm_chip_top/csrc/_vcs_pli_stub_.o b/sim/therm_chip_top/csrc/_vcs_pli_stub_.o new file mode 100644 index 0000000000000000000000000000000000000000..7927935c57aee37f8abf6ae68b875d307c9fe183 GIT binary patch literal 32032 zcmeI5eR!1BnZ^g=2P#Tb=;Feq(M208#3all6BRcILQoKDK(S(zAsI+CUuGs46cs8e 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/dev/null +++ b/sim/therm_chip_top/csrc/filelist @@ -0,0 +1,32 @@ + + +AR=ar +DOTLIBS=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libzerosoft_rt_stubs.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so + +# This file is automatically generated by VCS. Any changes you make to it +# will be overwritten the next time VCS is run +VCS_LIBEXT= +XTRN_OBJS= + +DPI_WRAPPER_OBJS = +DPI_STUB_OBJS = +# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS +include filelist.dpi +PLI_STUB_OBJS = +include filelist.pli + +include filelist.hsopt + +include filelist.cu + +VCS_MISC_OBJS= +VCS_INCR_OBJS= + + +AUGDIR= +AUG_LDFLAGS= +SHARED_OBJ_SO= + + + +VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS) diff --git a/sim/therm_chip_top/csrc/filelist.cu b/sim/therm_chip_top/csrc/filelist.cu new file mode 100644 index 0000000..aca2596 --- /dev/null +++ b/sim/therm_chip_top/csrc/filelist.cu @@ -0,0 +1,49 @@ +PIC_LD=ld + +ARCHIVE_OBJS= +ARCHIVE_OBJS += _131020_archive_1.so +_131020_archive_1.so : archive.0/_131020_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131020_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_131020_archive_1.so $@ + + +ARCHIVE_OBJS += _131039_archive_1.so +_131039_archive_1.so : archive.0/_131039_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131039_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_131039_archive_1.so $@ + + +ARCHIVE_OBJS += _131040_archive_1.so +_131040_archive_1.so : archive.0/_131040_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_131040_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_131040_archive_1.so $@ + + + + + +O0_OBJS = + +$(O0_OBJS) : %.o: %.c + $(CC_CG) $(CFLAGS_O0) -c -o $@ $< + + +%.o: %.c + $(CC_CG) $(CFLAGS_CG) -c -o $@ $< +CU_UDP_OBJS = \ + + +CU_LVL_OBJS = \ +SIM_l.o + +MAIN_OBJS = \ +objs/amcQw_d.o + +CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS) + diff --git a/sim/therm_chip_top/csrc/filelist.dpi b/sim/therm_chip_top/csrc/filelist.dpi new file mode 100644 index 0000000..e69de29 diff --git a/sim/therm_chip_top/csrc/filelist.hsopt b/sim/therm_chip_top/csrc/filelist.hsopt new file mode 100644 index 0000000..468b268 --- /dev/null +++ b/sim/therm_chip_top/csrc/filelist.hsopt @@ -0,0 +1,13 @@ +rmapats_mop.o: rmapats.m + @/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o + +rmapats.o: rmapats.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c +rmapats%.o: rmapats%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< +rmar.o: rmar.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c +rmar%.o: rmar%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< + +include filelist.hsopt.objs diff --git a/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs b/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs new file mode 100644 index 0000000..4c31419 --- /dev/null +++ b/sim/therm_chip_top/csrc/filelist.hsopt.llvm2_0.objs @@ -0,0 +1 @@ +LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o diff --git a/sim/therm_chip_top/csrc/filelist.hsopt.objs b/sim/therm_chip_top/csrc/filelist.hsopt.objs new file mode 100644 index 0000000..f40e57c --- /dev/null +++ b/sim/therm_chip_top/csrc/filelist.hsopt.objs @@ -0,0 +1,7 @@ +HSOPT_OBJS +=rmapats_mop.o \ + rmapats.o \ + rmar.o rmar_nd.o + +include filelist.hsopt.llvm2_0.objs +HSOPT_OBJS += $(LLVM_OBJS) + diff --git a/sim/therm_chip_top/csrc/filelist.pli b/sim/therm_chip_top/csrc/filelist.pli new file mode 100644 index 0000000..653944b --- /dev/null +++ b/sim/therm_chip_top/csrc/filelist.pli @@ -0,0 +1,4 @@ +PLI_STUB_OBJS += _vcs_pli_stub_.o +_vcs_pli_stub_.o: _vcs_pli_stub_.c + @$(CC) -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c + @strip -g _vcs_pli_stub_.o diff --git a/sim/therm_chip_top/csrc/hsim/hsim.sdb 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((U )vcs_clocks) + I685; + I1549 = I1547 & ((1 << fHashTableSize) - 1); + I1283->I727 = (EBLK *)(-1); + I1283->I731 = I1547; + if (I1547 < (U )vcs_clocks) { + I1548 = ((U *)&vcs_clocks)[1]; + sched_millenium(pQ, I1283, I1548 + 1, I1547); + } + else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) { + I1283->I733 = (struct eblk *)peblkFutQ1Tail; + peblkFutQ1Tail->I727 = I1283; + peblkFutQ1Tail = I1283; + } + else if ((I1550 = pQ->I1190[I1549].I745)) { + I1283->I733 = (struct eblk *)I1550->I744; + I1550->I744->I727 = (RP )I1283; + I1550->I744 = (RmaEblk *)I1283; + } + else { + sched_hsopt(pQ, I1283, I1547); + } +} +#ifdef __cplusplus +extern "C" { +#endif +void SinitHsimPats(void); +#ifdef __cplusplus +} +#endif diff --git a/sim/therm_chip_top/csrc/rmapats.h b/sim/therm_chip_top/csrc/rmapats.h new file mode 100644 index 0000000..680890e --- /dev/null +++ b/sim/therm_chip_top/csrc/rmapats.h @@ -0,0 +1,2474 @@ +#ifndef __DO_RMAHDR_ +#define __DO_RMAHDR_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define VCS_RTLIB_TLS_MODEL __attribute__((tls_model("initial-exec"))) + +typedef unsigned long UP; +typedef unsigned U; +typedef unsigned char UB; +typedef unsigned char scalar; +typedef struct vec32 vec32; +typedef unsigned short US; +typedef unsigned char SVAL; +typedef unsigned char TYPEB; +typedef struct qird QIRD; +typedef unsigned char UST_e; +typedef unsigned uscope_t; +typedef U NumLibs_t; +struct vec32 { + U I1; + U I2; +}; +typedef unsigned long RP; +typedef unsigned long RO; +typedef unsigned long long ULL; +typedef U GateCount; +typedef U NodeCount; +typedef unsigned short HsimEdge; +typedef unsigned char HsimExprChar; +typedef struct { + U I706; + RP I707; +} RmaReceiveClock1; +typedef NodeCount FlatNodeNum; +typedef U InstNum; +typedef unsigned ProcessNum; +typedef unsigned long long TimeStamp64; +typedef unsigned long long TimeStamp; +typedef enum { + PD_SING = 0, + PD_RF = 1, + PD_PLSE = 2, + PD_PLSE_RF = 3, + PD_NULL = 4 +} PD_e; +typedef TimeStamp RmaTimeStamp; +typedef TimeStamp64 RmaTimeStamp64; +typedef struct { + int * I708; + int * I709; + int I710; + union { + long long enumDesc; + long long classId; + } I711; +} TypeData; +struct etype { + U I586 :8; + U I587; + U I588; + U I589 :1; + U I590 :1; + U I591 :1; + U I592 :1; + U I593 :1; + U I594 :1; + U I595 :1; + U I596 :1; + U I597 :1; + U I598 :4; + U I599 :1; + U I600 :1; + U I601 :1; + U I602 :1; + U I603 :1; + U I604 :1; + U I605 :1; + U I606 :1; + U I607 :2; + U I608 :1; + U I609 :2; + U I610 :1; + U I611 :1; + U I612 :1; + U I613 :1; + U I614 :1; + U I615 :1; + TypeData * I616; + U I617; + U I618; + U I619 :1; + U I620 :1; + U I621 :1; + U I622 :1; + U I623 :2; + U I624 :2; + U I625 :1; + U I626 :1; + U I627 :1; + U I628 :1; + U I629 :1; + U I630 :1; + U I631 :1; + U I632 :1; + U I633 :1; + U I634 :1; + U I635 :1; + U I636 :13; +}; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} rma_clock_struct; +typedef struct eblk EBLK; +typedef int (* E_fn)(void); +typedef struct eblk { + struct eblk * I727; + E_fn I728; + struct iptmpl * I729; + unsigned I731; + unsigned I732; + struct eblk * I733; +} eblk_struct; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; +} RmaEblk; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; + unsigned val; +} RmaEblklq; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} clock_struct; +typedef clock_struct RmaClockStruct; +typedef struct RmaRetain_t RmaRetain; +struct RmaRetain_t { + RP I769; + RmaEblk I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I569 :1; + scalar newval; + scalar I780; + RP I781; +}; +struct retain_t { + struct retain_t * I769; + EBLK I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I778 :1; + scalar newval; + scalar I780; + void * I781; +}; +typedef struct MPSched MPS; +typedef struct RmaMPSched RmaMps; +struct MPSched { + MPS * I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + EBLK I766; + void * I767; + UP I768[1]; +}; +struct RmaMPSched { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + RP I767; + RP I768[1]; +}; +typedef struct RmaMPSchedPulse RmaMpsp; +struct RmaMPSchedPulse { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar I181; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U I789; + RmaClockStruct I790; + RmaClockStruct I791; + U state; + U I792; + RP I729; + RP I793; + RP I794; + RP I768[1]; +}; +typedef struct MPItem MPI; +struct MPItem { + U * I796; + void * I797; +}; +typedef struct { + RmaEblk I726; + RP I798; + scalar I799; + scalar I777; + scalar I800; +} RmaTransEventHdr; +typedef struct RmaMPSchedPulseNewCsdf RmaMpspNewCsdf; +struct RmaMPSchedPulseNewCsdf { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U state :4; + U I802 :28; + RmaClockStruct I790; + RmaClockStruct I791; + RP I803; + RP I729; + RP I804; + RP I768[1]; +}; +typedef struct red_t { + U I805; + U I806; + U I685; +} RED; +typedef struct predd { + PD_e I181; + RED I807[0]; +} PREDD; +union rhs_value { + vec32 I808; + scalar I799; + vec32 * I777; + double I809; + U I810; +}; +typedef struct nbs_t { + struct nbs_t * I811; + struct nbs_t * I813; + void (* I814)(struct nbs_t * I781); + U I815 :1; + U I816 :1; + U I817 :1; + U I818 :1; + U I819 :1; + U I820 :1; + U I821 :26; + U I822; + void * I823; + union rhs_value I824; + vec32 I718; + union { + struct nbs_t * first; + struct nbs_t * last; + } I826; +} NBS; +typedef struct { + RP I827; + RP I793; + RP I729; + RP I794; + RmaEblk I726; + RmaEblk I828; + RP I829; + scalar I799; + scalar I777; + char state; + uscope_t I830; + U I831; + RP I832; + scalar I786; + scalar I787; + scalar I788; + RmaClockStruct I790; + RmaClockStruct I791; + RP I767; +} RmaPulse; +typedef enum { + QIRDModuleC = 1, + QIRDSVPackageC = 2, + QIRDSpiceModuleC = 3 +} QIRDModuleType; +typedef struct { + U I836 :1; + U I837 :1; + U I838 :1; + U I839 :1; + U I840 :1; + U I841 :1; + U I842 :1; + U I843 :1; + U I844 :1; + U I845 :1; + U I846 :1; + U I847 :1; + U I848 :1; + U I849 :1; + U I850 :1; + U I851 :1; + U I852 :1; + U I853 :1; + QIRDModuleType I854 :2; + U I855 :1; + U I856 :1; + U I857 :1; + U I858 :1; + U I859 :1; + U I860 :1; + U I861 :1; + U I862 :1; + U I863 :1; + U I864 :1; + U I865 :1; + U I866 :1; + U I867 :1; + U I868 :1; + U I869 :1; + U I870 :1; + U I871 :1; + U I872 :1; + U I873 :1; + U I874 :1; +} BitFlags; +struct qird { + US I4; + US I5; + U I6; + U I7; + char * I8; + char * I9; + U * I10; + char * I11; + char * I12; + U I13; + U I14; + struct vcd_rt * I15; + U I17; + struct _vcdOffset_rt * I18; + U I20; + U I21; + U * I22; + U * I23; + void * I24; + void * I25; + U I26; + int I27; + UP I28; + U I29; + U I30; + U I31; + UP I32; + U * I33; + UP I34; + U I35; + BitFlags I36; + U I37; + U I38; + U I39; + U I40; + U I41; + U * I42; + U I43; + U * I44; + U I45; + U I46; + U I47; + U I48; + U I49; + U I50; + U I51; + U * I52; + U * I53; + U I54; + U I55; + U * I56; + U I57; + U * I58; + U I59; + U I60; + U I61; + U I62; + U * I63; + U I64; + U * I65; + U I66; + U I67; + U I68; + U I69; + U I70; + U I71; + U * I72; + char * I73; + U I74; + U I75; + U I76; + U I77; + U I78; + U * I79; + U I80; + U I81; + U I82; + UP * I83; + U I84; + U I85; + U I86; + U I87; + U I88; + U I89; + U * I90; + U I91; + U I92; + U * I93; + U * I94; + U * I95; + U * I96; + U * I97; + U I98; + U I99; + struct taskInfo * I100; + U I102; + U I103; + U I104; + int * I105; + U * I106; + UP * I107; + U * I108; + U I109; + U I110; + U I111; + U I112; + U I113; + struct qrefer * I114; + U * I116; + unsigned * I117; + void * I118; + U I119; + U I120; + struct classStaticReferData * I121; + U I123; + U * I124; + U I125; + U * I126; + U I127; + struct wakeupInfoStruct * I128; + U I130; + U I131; + U I132; + U * I133; + U I134; + U * I135; + U I136; + U I137; + U I138; + U * I139; + U I140; + U * I141; + U I142; + U I143; + U * I144; + U I145; + U I146; + U * I147; + U * I148; + U * I149; + U I150; + U I151; + U I152; + U I153; + U I154; + struct qrefee * I155; + U * I157; + U I158; + struct qdefrefee * I159; + U * I161; + int (* I162)(void); + char * I163; + U I164; + U I165; + void * I166; + void * I167; + NumLibs_t I168; + char * I169; + U * I170; + U I171; + U I172; + U I173; + U I174; + U I175; + U * I176; + U * I177; + int I178; + struct clock_load * I179; + int I194; + struct clock_data * I195; + int I211; + struct clock_hiconn * I212; + U I216; + U I217; + U I218; + U I219; + U * I220; + U * I221; + U I222; + void * I223; + U I224; + U I225; + UP * I226; + void * I227; + U I228; + UP * I229; + U * I230; + int (* I231)(void); + U * I232; + UP * I233; + U * I234; + U I235 :1; + U I236 :31; + U I237; + U I238; + UP * I239; + U * I240; + U I241 :1; + U I242 :1; + U I243 :1; + U I244 :1; + U I245 :28; + U I246; + U I247; + U I248; + U I249 :31; + U I250 :1; + UP * I251; + UP * I252; + U * I253; + U * I254; + U * I255; + U * I256; + UP * I257; + UP * I258; + UP * I259; + U * I260; + UP * I261; + UP * I262; + UP * I263; + UP * I264; + char * I265; + U I266; + U I267; + U I268; + UP * I269; + U I270; + UP * I271; + UP * I272; + UP * I273; + UP * I274; + UP * I275; + UP * I276; + UP * I277; + UP * I278; + UP * I279; + UP * I280; + UP * I281; + UP * I282; + UP * I283; + UP * I284; + U * I285; + U * I286; + UP * I287; + U I288; + U I289; + U I290; + U I291; + U I292; + U I293; + U I294; + U I295; + char * I296; + U * I297; + U I298; + U I299; + U I300; + U I301; + U I302; + UP * I303; + UP * I304; + UP * I305; + UP * I306; + struct daidirInfo * I307; + struct vcs_tftable * I309; + U I311; + UP * I312; + UP * I313; + U I314; + U I315; + U I316; + UP * I317; + U * I318; + UP * I319; + UP * I320; + struct qird_hil_data * I321; + UP (* I323)(void); + UP (* I324)(void); + UP (* I325)(void); + UP (* I326)(void); + UP (* I327)(void); + int * I328; + int (* I329)(void); + char * I330; + UP * I331; + UP * I332; + UP (* I333)(void); + int (* I334)(void); + int * I335; + int (* I336)(void); + int * I337; + char * I338; + U * I339; + U * I340; + U * I341; + U * I342; + void * I343; + U I344; + void * I345; + U I346; + U I347; + U I348; + U I349; + U I350; + U I351; + char * I352; + UP * I353; + U * I354; + U * I355; + U I356 :15; + U I357 :14; + U I358 :1; + U I359 :1; + U I360 :1; + U I361 :3; + U I362 :1; + U I363 :1; + U I364 :17; + U I365 :3; + U I366 :5; + U I367 :1; + U I368 :1; + U I369; + U I370; + struct scope * I371; + U I373; + U I374; + U I375; + U * I376; + U * I377; + U * I378; + U I379; + U I380; + U I381; + struct pcbt * I382; + U I392; + U I393; + U I394; + U I395; + void * I396; + void * I397; + void * I398; + int I399; + U * I400; + U I401; + U I402; + U I403; + U I404; + U I405; + U I406; + U I407; + void * I408; + UP * I409; + U I410; + U I411; + void * I412; + U I413; + void * I414; + U I415; + void * I416; + U I417; + int (* I418)(void); + int (* I419)(void); + void * I420; + void * I421; + void * I422; + U I423; + U I424; + U I425; + U I426; + U I427; + U I428; + char * I429; + U I430; + U * I431; + U I432; + U * I433; + U I434; + U I435; + U I436; + U I437; + U I438; + U I439; + U * I440; + U I441; + U I442; + U * I443; + U I444; + U I445; + U I446; + U * I447; + char * I448; + U I449; + U I450; + U I451; + U I452; + U * I453; + U * I454; + U I455; + U * I456; + U * I457; + U I458; + U I459; + U I460; + UP * I461; + U I462; + U I463; + U I464; + struct cosim_info * I465; + U I467; + U * I468; + U I469; + void * I470; + U I471; + U * I472; + U I473; + struct hybridSimReferrerData * I474; + U I476; + U * I477; + U I478; + U I479; + U * I480; + U I481; + U * I482; + U I483; + U * I484; + U I485; + U I486; + U I487; + U I488; + U I489; + U I490; + U I491; + U I492; + U I493; + U * I494; + U * I495; + void (* I496)(void); + U * I497; + UP * I498; + struct mhdl_outInfo * I499; + UP * I501; + U I502; + UP * I503; + U I504; + void * I505; + U * I506; + void * I507; + char * I508; + int (* I509)(void); + U * I510; + char * I511; + char * I512; + U I513; + U * I514; + char * I515; + U I516; + struct regInitInfo * I517; + UP * I519; + U * I520; + char * I521; + U I522; + U I523; + U I524; + U I525; + U I526; + U I527; + U I528; + U I529; + UP * I530; + U I531; + U I532; + U I533; + U I534; + UP * I535; + U I536; + UP * I537; + U I538; + U I539; + U I540; + U * I541; + U I542; + U I543; + U I544; + U * I545; + U * I546; + UP * I547; + UP * I548; + void * I549; + UP I550; + void * I551; + void * I552; + void * I553; + void * I554; + void * I555; + UP I556; + U * I557; + U * I558; + void * I559; + U I560 :1; + U I561 :31; + U I562; + U I563; + U I564; + int I565; + U I566 :1; + U I567 :1; + U I568 :1; + U I569 :29; + void * I570; + void * I571; + void * I572; + void * I573; + void * I574; + UP * I575; + U * I576; + U I577; + char * I578; + U * I579; + U * I580; + char * I581; + int * I582; + UP * I583; + struct etype * I584; + U I637; + U I638; + U * I639; + struct etype * I640; + U I641; + U I642; + U I643; + U * I644; + void * I645; + U I646; + U I647; + void * I648; + U I649; + U I650; + U * I651; + U * I652; + char * I653; + U I654; + struct covreg_rt * I655; + U I657; + U I658; + U * I659; + U I660; + U * I661; + U I662; + U I663; + U * I664; +}; +typedef struct pcbt { + U * I384; + UP I385; + U I386; + U I387; + U I388; + U I389; + U I390; + U I391; +} PCBT; +struct iptmpl { + QIRD * I734; + struct vcs_globals_t * I735; + void * I737; + UP I738; + UP I739; + struct iptmpl * I729[2]; +}; +typedef unsigned long long FileOffset; +typedef struct _RmaMultiInputTable { + U I881 :1; + U I882 :1; + U I672 :2; + U I673 :4; + U I674 :5; + U I883 :1; + U I884 :1; + U I885 :1; + U I886 :1; + U I887 :1; + U I888 :1; + U I889; + U I890; + U I203; + U I891; + U I892 :1; + U I893 :31; + union { + U utable; + U edgeInputNum; + } I699; + U I894 :4; + U I895 :4; + U I896 :4; + U I897 :4; + U I898 :4; + U I899 :4; + U I900 :1; + U I901 :1; + U I902 :1; + U I903 :1; + U I904 :5; + HsimExprChar * I905; + UB * I906; + UB * I907; + struct _RmaMultiInputTable * I880; + struct _RmaMultiInputTable * I909; +} RmaMultiInputTable; +typedef struct _HsCgPeriod { + U I955; + U I956; +} HsCgPeriod; +typedef struct { + U I957[2]; + U I958 :1; + U I959 :1; + U I960 :8; + U I961 :8; + U I962 :8; + U I963 :4; + U I964 :1; + U I965 :1; + unsigned long long I966; + unsigned long long I967; + unsigned long long I968; + unsigned long long I969; + unsigned long long I956; + U I955; + U I970; + U I971; + U I972; + U I973; + U I974; + HsCgPeriod * I975[10]; +} HsimSignalMonitor; +typedef struct { + FlatNodeNum I976; + InstNum I977; + U I915; + scalar I978; + UB I979; + UB I980; + UB I981; + UB I982; + UB I983; + UB I984; + U I985; + U I986; + U I987; + U I988; + U I989; + U I990; + U I991; + U I992; + U I993; + HsimSignalMonitor * I994; + RP I995; + RmaTimeStamp64 I996; + U I997; + RmaTimeStamp64 I998; + U I999; + UB I1000; +} HsimNodeRecord; +typedef RP RCICODE; +typedef struct { + RP I1005; + RP I729; +} RmaIbfIp; +typedef struct { + RP I1005; + RP pcode; +} RmaIbfPcode; +typedef struct { + RmaEblk I726; +} RmaEvTriggeredOrSyncLoadCg; +typedef struct { + RO I877; + RP pcode; +} SchedGateFanout; +typedef struct { + RO I877; + RP pcode; + U I936[4]; +} SchedSelectGateFanout; +typedef struct { + RP pcode; + RmaEblklq I726; +} SchedGateEblk; +typedef struct { + RP pcode; + RmaEblklq I726; + UB * I1006; +} SchedSelectGateEblk; +typedef struct { + RP I1007; + RP pfn; + RP pcode; +} RmaSeqPrimOutputEblkData; +typedef struct { + RmaEblk I726; + RP I1008; +} RmaAnySchedSampleSCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I1009; +} RmaAnySchedVCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I776[1]; +} RmaAnySchedWCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + scalar I1010[1]; +} RmaAnySchedECg; +typedef struct { + U I1011; + U I714; + U I915; + U I1012; + RmaIbfIp * I1013; + EBLK I726; + void * val; +} RmaThreadSchedCompiledLoads; +typedef struct { + U I714; + U I722; + RmaThreadSchedCompiledLoads * I1014; +} RmaSchedCompileLoadsCg; +typedef struct { + RP I1015; +} RmaRootCbkCg; +typedef struct { + RP I1016; +} RmaRootForceCbkCg; +typedef struct { + RmaEblk I726; + RP I1017; +} RmaForceCbkJmpCg; +typedef struct { + U I5; + U I722 :31; + U I1018 :1; + vec32 I808; + U I1019; + RP I1020; + RP I1021; +} RmaForceSelectorV; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeDriverGate; +typedef struct { + U I5; + U I668; + RmaIbfPcode I1027[1]; +} RmaNetTypeScatterGate; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeGatherGate; +typedef struct { + RmaIbfPcode I1028; + U I1029 :3; + U I1030 :1; + U I1031 :1; + U I890 :16; +} RmaNbaGateOfn; +typedef struct { + U I5; + NBS I1032; + RmaIbfPcode I1028; +} RmaNbaGate1; +typedef struct { + RP ptable; + RP pfn; + RP pcode; +} Rma1InputGateFaninCgS; +typedef struct RmaSeqPrimOutputS_ RmaSeqPrimOutputOnClkS; +struct RmaSeqPrimOutputS_ { + RP pfn; + RP I1035; + U state; + U I1036; + RP I1037; + U I706; + scalar val; +}; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaCondOptLoad; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaMacroStateUpdate; +typedef struct { + U I5; + U state; + U I1041; + UB I1039; + U * I1042; +} RmaMacroState; +typedef struct { + U iinput; + RP I1043; +} RmaMultiInputLogicGateCg; +typedef struct { + U iinput; + RP ptable; + RP I1043; +} RmaSeqPrimEdgeInputCg; +typedef struct { + RmaEblk I726; + RP pcode; +} RmaSched0GateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; +} RmaUdpDeltaGateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; + scalar I1044; +} RmaSchedDeltaGateCg; +typedef struct { + UB I1045; + RP I1046; + RP I1047; +} RmaPropNodeSeqLhsSCg; +typedef struct { + RmaEblk I726; + RP pcode; + U I915; + U I715[1]; +} RmaBitEdgeEblk; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateBehavioralDelay; +typedef struct { + U I5; + union { + RP I1290; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaMPDelay; +typedef struct { + U I5; + RmaPulse I1048; + RmaIbfPcode I1028; +} RmaMPPulseHybridDelay; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMps I1049; +} RmaMPHybridDelay; +typedef struct { + U I5; + U I1050; + RmaIbfPcode I1028; + RmaEblk I766; +} RmaMPHybridDelayPacked; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMpspNewCsdf I1051; +} RmaMPPulseDelay; +typedef struct { + U I5; + RmaMpsp I1051; + RmaIbfPcode I1028; +} RmaMPPulseOptHybridDelay; +typedef struct _RmaBehavioralTransportDelay { + U I5; + RP I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaBehavioralTransportDelayS; +typedef struct { + U I5; + U I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelay; +typedef struct { + U I5; + U I685; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransZeroDelay; +typedef struct { + U I5; + U I1052; + U I1053; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelayRF; +typedef struct { + U I5; + U I1052; + U I1053; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelayRF; +typedef struct { + U I5; + RP I1054; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaICTransDelay; +typedef struct { + U I5; + RP I1054; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransZeroDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICSimpleDelay; +typedef struct { + U I5; + union { + RP psimple; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaICDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaPortDelay; +typedef struct { + U I890; + RP I1058; +} RmaRtlXEdgesLoad; +typedef struct { + U I5; + RmaRtlXEdgesLoad I1058[(5)]; +} RmaRtlXEdgesHdr; +typedef struct { + U I5; + US I1059; + US I1060 :1; + US I904 :15; + RP I1061; + RP I1062; + RP I1063; +} RmaRtlEdgeBlockHdr; +typedef struct { + RP I1064; + RP I1065; +} RemoteDbsedLoad; +typedef struct { + RmaEblk I726; + RP I1066; + RP I1067; + U I1068 :16; + U I1069 :2; + U I1070 :2; + U I1071 :1; + U I1072 :8; + U I904 :3; + U I471; + RP I1073; + RP I811[(5)]; + RP I813[(5)]; + US I1074; + US I1075; + RemoteDbsedLoad I1076[1]; +} RmaRtlEdgeBlock; +typedef struct TableAssign_ { + struct TableAssign_ * I880; + struct TableAssign_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RP I1043; +} TableAssign; +typedef struct TableAssignLayoutOnClk_ { + struct TableAssignLayoutOnClk_ * I880; + struct TableAssignLayoutOnClk_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RmaSeqPrimOutputOnClkS I1089; + RmaEblk I726; +} TableAssignLayoutOnClk; +typedef struct { + U state; + U I1090; +} RmaSeqPrimOutputOnClkOpt; +typedef struct TableAssignLayoutOnClkOpt_ { + struct TableAssignLayoutOnClkOpt_ * I880; + struct TableAssignLayoutOnClkOpt_ * I798; + U I1092; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RmaSeqPrimOutputOnClkOpt I1089; + RmaSeqPrimOutputEblkData I1093; +} TableAssignLayoutOnClkOpt; +typedef struct { + U I5; + RP I798; + RP I1094; +} RmaTableAssignList; +typedef struct { + U I5; + RP I798; + RP I1094; + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; + RP I1098[0]; +} RmaThreadTableAssignList; +typedef struct { + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; +} RmaThreadTableHeader; +typedef struct { + RP I1064; +} RmaWakeupListCg; +typedef struct { + RP I1064; +} RmaWakeupArrayCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupListCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupArrayCg; +typedef struct { + U I1100; + U I706; + RmaTimeStamp I1101[1]; +} RmaTsArray; +typedef struct { + U iinput; + RP I1102; +} RmaConditionsMdb; +typedef struct { + RP I1103; + RP I1104; + U I1105; +} RmaTcListHeader; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimple; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditional; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOpt; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtc; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimpleNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1035; +} RmaTcCoreSimpleNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditionalNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOptNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + RP I1035; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1035; +} RmaTcCoreConditionalNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + U I1122; + RP I1123; + RP I1124; + RP I1117; + RP I1125; + RP I1126; + RmaTimeStamp I1127; +} RmaTcCoreNochange; +typedef struct { + RP I1128; + RP I880; +} RmaTcCoreNochangeList; +typedef struct { + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoadNoList; +typedef struct { + RP I880; + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoad; +typedef struct { + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOptNoList; +typedef struct { + RP I880; + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOpt; +typedef struct { + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoList; +typedef struct { + RP I1035; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoListMdb; +typedef struct { + RP I880; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtc; +typedef struct { + U I1132; + U I1133; + FlatNodeNum I1004; + U I915; + U I1134; + U I1135; + RmaIbfPcode I1028; + union { + scalar I1136; + vec32 I1137; + scalar * I1138; + vec32 * I1139; + } val; +} RmaScanSwitchData; +typedef struct { + RP I880; + RP I798; + RP I1140; +} RmaDoublyLinkedListElem; +typedef struct { + RP I1141; + U I1142 :1; + U I1143 :1; + U I1144 :1; + U I1145 :4; + U I904 :25; + U I1146; +} RmaSwitchGateInCbkListInfo; +typedef struct { + union { + RmaDoublyLinkedListElem I1640; + RmaSwitchGateInCbkListInfo I2; + } I699; + RmaIbfPcode I1028; +} RmaSwitchGate; +typedef struct RmaNonEdgeLoadData1_ { + US I1147; + scalar val; + scalar I1148 :1; + scalar I1149 :1; + scalar I1150 :1; + scalar I1151 :1; + scalar I1152 :1; + U I1153; + RP I811; + RP I1154; + RP I1004; + RP I1155; + RP I1156; +} RmaNonEdgeLoadData1; +typedef struct RmaNonEdgeLoadHdr1_ { + UB I1148; + UB I1157; + UB I978; + RmaNonEdgeLoadData1 * I1058; + RmaNonEdgeLoadData1 * I798; + void * I1158; +} RmaNonEdgeLoadHdr1; +typedef struct RmaNonEdgeLoadHdrPrl1_ { + U I1159; + RP I721; +} RmaNonEdgeLoadHdrPrl1; +typedef struct RmaChildClockProp_ { + RP I811; + RP I1160; + RP I1004; + RP pcode; + scalar val; +} RmaChildClockProp; +typedef struct RmaChildClockPropList1_ { + RmaChildClockProp * I1058; + RmaChildClockProp * I798; +} RmaChildClockPropList1; +typedef struct { + U I5; + U I1161; +} RmaHDLCosimDUTGate; +typedef struct { + UB I1162; + UB I1163 :1; + UB I1164 :1; + UB I1165 :1; + UB I1166 :1; + UB I904 :4; + US cedges; +} RmaMasterXpropLoadHdr; +typedef struct { + UB I1167; + UB I1168; + UB I1169; + UB I1170; + U cedges :30; + U I1164 :1; + U I1171 :1; + U I1172; + U I1173; + RP I1174; + RP I1175; + RmaRtlEdgeBlockHdr * I1176; +} RmaChildXpropLoadHdr; +struct clock_load { + U I181 :5; + U I182 :12; + U I183 :1; + U I184 :2; + U I185 :1; + U I186 :1; + U I187 :1; + U I188 :9; + U I189; + U I190; + void (* pfn)(void * I192, char val); +}; +typedef struct clock_data { + U I197 :1; + U I198 :1; + U I199 :1; + U I200 :1; + U I181 :5; + U I182 :12; + U I201 :6; + U I202 :1; + U I184 :2; + U I185 :1; + U I188 :1; + U I203; + U I204; + U I205; + U I189; + U I206; + U I207; + U I208; + U I209; + U I210; +} HdbsClockData; +struct clock_hiconn { + U I214; + U I215; + U I189; + U I184; +}; +typedef struct _RmaDaiCg { + RP I1177; + RP I1178; + U I1179; +} RmaDaiCg; +typedef union _RmaCbkMemOptUnion { + RP I1177; + RP I1180; + RP I1181; +} RmaCbkMemOptUnion; +typedef struct _RmaDaiOptCg { + RmaCbkMemOptUnion I1182; +} RmaDaiOptCg; +struct futq_slot2 { + U I758; + U I759[32]; +}; +struct futq_slot1 { + U I755; + struct futq_slot2 I756[32]; +}; +struct futq_info { + scalar * I750; + U I751; + U I752; + struct futq_slot1 I753[32]; +}; +struct futq { + struct futq * I740; + struct futq * I742; + RmaEblk * I743; + RmaEblk * I744; + U I731; + U I1; +}; +struct sched_table { + struct futq * I745; + struct futq I746; + struct hash_bucket * I747; + struct hash_bucket * I749; +}; +struct dummyq_struct { + clock_struct I1183; + EBLK * I1184; + EBLK * I1185; + EBLK * I1186; + struct futq * I1187; + struct futq * I1188; + struct futq * I1189; + struct sched_table * I1190; + struct futq_info * I1192; + struct futq_info * I1194; + U I1195; + U I1196; + U I1197; + U I1198; + U I1199; + U I1200; + U I1201; + struct millenium * I1202; + EBLK * I1204; + EBLK * I1205; + EBLK * I1206; + EBLK * I1207; + EBLK * I1208; + EBLK * I1209; + EBLK * I1210; + EBLK * I1211; + EBLK * I1212; + EBLK * I1213; + EBLK * I1214; + EBLK * I1215; + EBLK * I1216; + EBLK * I1217; + EBLK * I1218; + EBLK * I1219; + EBLK * I1220; + EBLK * I1221; + MPS * I1222; + struct retain_t * I1223; + EBLK * I1224; + EBLK * I1225; + EBLK * I1226; + EBLK * I1227; + EBLK * I1228; + EBLK * I1229; + EBLK * I1230; + EBLK * I1231; + EBLK * I1232; + EBLK * I1233; + EBLK * I1234; + EBLK * I1235; + EBLK * I1236; + EBLK * I1237; + EBLK * I1238; + EBLK * I1239; + EBLK * I1240; + EBLK * I1241; + EBLK * I1242; + EBLK * I1243; + EBLK * I1244; + EBLK * I1245; + EBLK * I1246; + EBLK * I1247; + EBLK * I1248; + EBLK * I1249; + EBLK I1250; + EBLK * I1251; + EBLK * I1252; + EBLK * I1253; + EBLK * I1254; + int I1255; + int I1256; + struct vcs_globals_t * I1257; + clock_struct I1258; + unsigned long long I1259; + EBLK * I1260; + EBLK * I1261; + void * I1262; +}; +typedef void (* FP)(void * , scalar ); +typedef void (* FP1)(void * ); +typedef void (* FPRAP)(void * , vec32 * , U ); +typedef U (* FPU1)(void * ); +typedef void (* FPV)(void * , UB * ); +typedef void (* FPVU)(void * , UB * , U ); +typedef void (* FPLSEL)(void * , scalar , U ); +typedef void (* FPLSELV)(void * , vec32 * , U , U ); +typedef void (* FPFPV)(UB * , UB * , U , U , U , U , U , UB * , U ); +typedef void (* FPFA)(UB * , UB * , U , U , U , U , U , U , UB * , U ); +typedef void (* FPRPV)(UB * , U , U , U ); +typedef void (* FPEVCDLSEL)(void * , scalar , U , UB * ); +typedef void (* FPEVCDLSELV)(void * , vec32 * , U , U , UB * ); +typedef void (* FPNTYPE_L)(void * , void * , U , U , UB * , UB * , UB * , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_H)(void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_LPAP)(void * , void * , void * , U , U , UB * , UB * , U ); +typedef void (* FPNTYPE_HPAP)(void * , void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef struct _lqueue { + EBLK * I727; + EBLK * I1263; + int I1264; + struct _lqueue * I769; +} Queue; +typedef struct { + void * I1266; + void * I1267; + void * I1268[2]; + void * I1269; +} ClkLevel; +typedef struct { + unsigned long long I1270; + EBLK I1171; + U I1271; + U I1272; + union { + void * pHeap; + Queue * pList; + } I699; + unsigned long long I1273; + ClkLevel I1274; + Queue I1275[1]; +} Qhdr; +extern UB Xvalchg[]; +extern UB X4val[]; +extern UB X3val[]; +extern UB X2val[]; +extern UB XcvtstrTR[]; +extern UB Xcvtstr[]; +extern UB Xbuf[]; +extern UB Xbitnot[]; +extern UB Xwor[]; +extern UB Xwand[]; +extern U Xbitnot4val[]; +extern UB globalTable1Input[]; +extern __thread unsigned long long vcs_clocks; +extern UB Xunion[]; +extern U fRTFrcRelCbk; +extern FP txpFnPtr; +extern FP rmaFunctionArray[]; +extern UP rmaFunctionRtlArray[]; +extern FP rmaFunctionLRArray[]; +extern U rmaFunctionCount; +extern U rmaFunctionLRCount; +extern U rmaFunctionLRDummyCount; +extern UP rmaFunctionDummyEndPtr; +extern FP rmaFunctionFanoutArray[]; +extern __thread UB dummyScalar; +extern __thread UB fScalarIsForced; +extern __thread UB fScalarIsReleased; +extern U fNotimingchecks; +extern U fFsdbDumpOn; +extern RP * iparr; +extern FP1 * rmaPostAnySchedFnPtr; +extern FP1 * rmaPostAnySchedFnSamplePtr; +extern FP1 * rmaPostAnySchedVFnPtr; +extern FP1 * rmaPostAnySchedWFnPtr; +extern FP1 * rmaPostAnySchedEFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusNonCongruentFnPtr; +extern FP1 * rmaPostSchedUpdateEvTrigFnPtr; +extern FP1 * rmaSched0UpdateEvTrigFnPtr; +extern FP1 * rmaPostSchedRecoveryResetDbsFnPtr; +extern U fGblDataOrTime0Prop; +extern UB rmaEdgeStatusValArr[]; +extern FP1 * propForceCbkSPostSchedCgFnPtr; +extern FP1 * propForceCbkMemoptSPostSchedCgFnPtr; +extern UB * ptableGbl; +extern U * vcs_ptableOffsetsGbl; +extern UB * expandedClkValues; +extern __thread Qhdr * lvlQueue; +extern __thread unsigned threadIndex; +extern int cPeblkThreads; +extern US xedges[]; +extern U mhdl_delta_count; +extern U ignoreSchedForScanOpt; +extern U fignoreSchedForDeadComboCloud; +extern int fZeroUser; +extern U fEveBusPullVal; +extern U fEveBusPullFlag; +extern U fFutEventPRL; +extern U fParallelEBLK; +extern U fBufferingEvent; +extern __thread UB fNettypeIsForced; +extern __thread UB fNettypeIsReleased; +extern EBLK * peblkFutQ1Head; +extern EBLK * peblkFutQ1Tail; +extern US * edgeActionT; +extern unsigned long long * derivedClk; +extern U fHashTableSize; +extern U fSkipStrChangeOnDelay; +extern U fHsimTcheckOpt; +extern scalar edgeChangeLookUp[4][4]; +extern U fDoingTime0Prop; +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; + + +extern void *mempcpy(void* s1, void* s2, unsigned n); +extern UB* rmaEvalDelays(UB* pcode, scalar val); +extern UB* rmaEvalDelaysV(UB* pcode, vec32* pval); +extern void rmaPopTransEvent(UB* pcode); +extern void rmaSetupFuncArray(UP* ra, U c, U w); +extern void rmaSetupRTLoopReportPtrs(UP* funcs, UP* rtlFuncs, U cnt, U cntDummy, UP end); +extern void SinitHsimPats(void); +extern void VVrpDaicb(void* ip, U nIndex); +extern int SDaicb(void *ip, U nIndex); +extern void SDaicbForHsimNoFlagScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlagStrengthScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlag2(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimWithFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlagFrcRel(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimNoFlagFrcRel2(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void VcsHsimValueChangeCB(void* pRmaDaiCg, void* pValue, unsigned int valueFormat); +extern U isNonDesignNodeCallbackList(void* pRmaDaiCg); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void VVrpNonEventNonRegdScalarForHsimOptCbkMemopt(void* ip, U nIndex); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabFrcRel(U* mem, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimCbkMemOptNoFlagFrcRel(void* pDaiCb, unsigned char reason, int msb, int lsb, int ndx); +extern void hsimDispatchCbkMemOptForVcd(RP p, U val); +extern void* hsimGetCbkMemOptCallback(RP p); +extern void hsimDispatchCbkMemOptNoDynElabS(RP* p, U val, U isStrength); +extern void* hsimGetCbkPtrNoDynElab(RP p); +extern void hsimDispatchCbkMemOptDynElabS(U** pvcdarr, U** pcbkarr, U val, U isScalForced, U isScalReleased, U isStrength); +extern void hsimDispatchCbkMemOptNoDynElabVector(RP* /*RmaDaiOptCg* */p, void* pval, U /*RmaValueType*/ vt, U cbits); +extern void copyAndPropRootCbkCgS(RmaRootCbkCg* pRootCbk, scalar val); +extern void copyAndPropRootCbkCgV(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgW(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgE(RmaRootCbkCg* rootCbk, scalar* pval); +extern void Wsvvar_callback_non_dynamic1(RP* ptr, int); +extern void rmaExecEvSyncList(RP plist); +extern void Wsvvar_callback_virt_intf(RP* ptr); +extern void Wsvvar_callback_hsim_var(RP* ptr); +extern void checkAndConvertVec32To2State(vec32* value, vec32* svalue, U cbits, U* pforcedBits); +extern unsigned int fGblDataOrTime0Prop; +extern void SchedSemiLerMP1(UB* pmps, U partId); +extern void SchedSemiLerMPO(UB* pmpso, U partId); +extern void rmaDummyPropagate(void); +extern RP rmaTestCg(RP pcode, U vt, UB* value); +extern void hsUpdateModpathTimeStamp(UB* pmps); +extern void doMpd32One(UB* pmps); +extern void doMpdCommon(MPS* pmps); +extern TimeStamp GET_DIFF_DELAY_FUNC(TimeStamp ts); +extern void SchedSemiLerMP(UB* ppulse, U partId); +extern EBLK *peblkFutQ1Head; +extern EBLK *peblkFutQ1Tail; +extern void scheduleuna(UB *e, U t); +extern void scheduleuna_mp(EBLK *e, unsigned t); +extern void schedule(UB *e, U t); +extern void sched_hsopt(struct dummyq_struct * pQ, EBLK *e, U t); +extern void sched_millenium(struct dummyq_struct * pQ, void *e, U thigh, U t); +extern void schedule_1(EBLK *e); +extern void sched0(UB *e); +extern void sched0Raptor(UB *e); +extern void sched0lq(EBLK *e); +extern void sched0lqnc(EBLK *e); +extern void sched0una(UB *e); +extern void sched0una_th(struct dummyq_struct *pq, UB *e); +extern void hsopt_sched0u_th(struct dummyq_struct *pq, UB *e); +extern void scheduleuna_mp_th(struct dummyq_struct *pq, EBLK *e, unsigned t); +extern void schedal(UB *e); +extern void sched0_th(struct dummyq_struct * pQ, EBLK *e); +extern void sched0u(UB *e); +extern void sched0u_th(struct dummyq_struct *pq, UB *e); +extern void sched0_hsim_front_th(struct dummyq_struct * pQ, UB *e); +extern void sched0_hsim_frontlq_th(struct dummyq_struct * pQ, UB *e); +extern void sched0lq_th(struct dummyq_struct * pQ, UB *e); +extern void schedal_th(struct dummyq_struct * pQ, UB *e); +extern void scheduleuna_th(struct dummyq_struct * pQ, void *e, U t); +extern void schedule_th(struct dummyq_struct * pQ, UB *e, U t); +extern void schedule_1_th(struct dummyq_struct * pQ, EBLK *peblk); +extern void SetupLER_th(struct dummyq_struct * pQ, EBLK *e); +extern void FsdbReportClkGlitch(UB*,U); +extern void AddToClkGLitchArray(EBLK*); +extern void SchedSemiLer_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXP_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXPFreeVar_th(struct dummyq_struct * pQ, EBLK *e); +extern U getVcdFlags(UB *ip); +extern void VVrpNonEventNonRegdScalarForHsimOpt(void* ip, U nIndex); +extern void VVrpNonEventNonRegdScalarForHsimOpt2(void* ip, U nIndex); +extern void SchedSemiLerTBReactiveRegion(struct eblk* peblk); +extern void SchedSemiLerTBReactiveRegion_th(struct eblk* peblk, U partId); +extern void SchedSemiLerTr(UB* peblk, U partId); +extern void SchedSemiLerNBA(UB* peblk, U partId); +extern void NBA_Semiler(void *ip, void *pNBS); +extern void sched0sd_hsim(UB* peblk); +extern void vcs_sched0sd_hsim_udpclk(UB* peblk); +extern void vcs_sched0sd_hsim_udpclkopt(UB* peblk); +extern void sched0sd_hsim_PRL(UB* peblk); +extern void sched0lq_parallel_clk(EBLK* peblk); +extern U isRtlClockScheduled(EBLK* peblk); +extern void doFgpRaceCheck(UB* pcode, UB* p, U flag); +extern void doSanityLvlCheck(); +extern void sched0lq_parallel_ova(EBLK* peblk); +extern void sched0lq_parallel_ova_precheck(EBLK* peblk); +extern void rmaDlpEvalSeqPrim(UB* peblk, UB val, UB preval); +extern void appendNtcEvent(UB* phdr, scalar s, U schedDelta); +extern void appendTransEventS(RmaTransEventHdr* phdr, scalar s, U schedDelta); +extern void schedRetainHsim(MPS* pMPS, scalar sv, scalar pv); +extern void updateRetainHsim(MPS* pMPS,scalar sv, scalar pv); +extern void hsimCountXEdges(void* record, scalar s); +extern void hsimRegisterEdge(void* sm, scalar s); +extern U pvcsGetPartId(); +extern void HsimPVCSPartIdCheck(U instNo); +extern void debug_func(U partId, struct dummyq_struct* pQ, EBLK* EblkLastEventx); +extern struct dummyq_struct* pvcsGetQ(U thid); +extern EBLK* pvcsGetLastEventEblk(U thid); +extern void insertTransEvent(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, int re, UB* predd, U fpdd); +extern void insertNtcEventRF(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, U* delays); +extern U doTimingViolation(RmaTimeStamp ts,RP* pdata, U fskew, U limit, U floaded, U fcondopt, RmaTimeStamp tsNochange); +extern void sched_gate_hsim(EBLK* peblk, unsigned t, RP* offset, U gd_info, U encodeInPcode, void* propValue); +extern int getCurSchedRegion(); +extern FP getRoutPtr(RP, U); +extern U rmaChangeCheckAndUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern void rmaUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaChangeCheckAndUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaLhsPartSelUpdateE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaUpdateWithForceSelectorE(scalar* pvalDst, scalar* pvalSrc, U cbits, U* pforceSelector); +extern void rmaUpdateWFromE(vec32* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaLhsPartSelWithChangeCheckE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaLhsPartSelWFromE(vec32* pvalDst, scalar* pvalSrc, U index,U width); +extern U rmaChangeCheckAndUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void *VCSCalloc(size_t size, size_t count); +extern void *VCSMalloc(size_t size); +extern void VCSFree(void *ptr); +extern U rmaLhsPartSelWithChangeCheckW(vec32* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern U rmaLhsPartSelWithChangeCheckEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelUpdateW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void rmaEvalWunionW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWorW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWandW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalUnionE(scalar* dst, scalar* src, U cbits, U count, RP ptable); +typedef U RmaCgFunctionType; +extern RmaIbfPcode* rmaEvalPartSelectsW(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWLe32(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWToE(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern RmaIbfPcode* rmaEvalPartSelectsEToE(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsEToW(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern U rmaEvalBitPosEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U VcsForceVecVCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U/*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecVCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecWCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecWCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecECg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecACg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecCg(UB* pcode, UB* pvDst, U ibeginDst, U width, U /*RmaValueType*/ type,U fisRoot, UB* prhsDst, U frhs, U* pforcedbits); +extern U VcsDriveBitsAndDoChangeCheckV(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckW(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckE(scalar* pvSel, scalar* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern void cgvecDebug_Eblk(UB* pcode); +extern U rmaCmpW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void copyVec32ArrMask(vec32* pv1, vec32* pv2, U len, U* mask); +extern void* memcpy(void*, const void*, size_t); +extern int memcmp(const void*, const void*, size_t); +extern void propagateScanOptPathVal(EBLK *peblk); +extern UB* rmaProcessScanSwitches(UB* pcode, scalar val); +extern UB* rmaProcessScanSwitchesV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanoptDump(UB* pcode, scalar val); +extern UB* rmaProcessScanoptDumpV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanChainOptSeqPrims(UB* pcode, scalar val); +extern void rmaProcessPvcsCcn(UB* pcode, scalar val); +extern void rmaProcessPvcsCcnE(UB* pcode, scalar* val); +extern void rmaProcessPvcsCcnW(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnV(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnCompiledS(UB* pcode, U offset, scalar ibnval); +extern void rmaProcessPvcsCcnCompiledV(UB* pcode, U offset, vec32* pval); +extern void schedResetRecoveryDbs(U cedges, EBLK* peblkFirst); +extern UB* rmaEvalUnaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVOneFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVLargeFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalAndOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpV(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpV(UB* pcode, vec32* value); +extern UB* rmaEvalTernaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalTernaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalBinaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpS(UB* pcode, scalar val); +extern scalar rmaGetScalarFromWCg(vec32* pval, U index); +extern void rmaSetScalarInWCg(vec32* pval, U index, scalar s); +extern void rmaSetWInW(vec32* dst, vec32* src, U index, U indexSrc, U width); +extern void rmaCountRaptorBits(void* pval, void* pvalPrev, U cbits, U vt); +extern void setHsimFunc(void* ip); +extern void unsetHsimFunc(void* ip); +extern UB* getEvcdStatusByFlagsE(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsV(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsW(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsS(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table); +extern UB* getSingleDrvEvcdStatusS(UB value, U fTBDriver); +extern UB* getSingleDrvEvcdStatusE(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusV(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusW(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getEvcdStatusByDrvEvcdStatus(UB* pdrvevcdStatus, U cdrivers, UB* table, U cbits); +extern void evcdCallback(UP pcode, U cbits); +extern UB* getSavedEvcdStatus(void); +extern void saveEvcdStatus(UB*); +extern void mhdlMarkExport(void*, U); +extern void levelInsertQueue(int); +extern void VcsRciRtl(RP pcode); +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; +extern void rtSched0LoopDectDumpProcess(void* e, void* rtn, void* PQ); +extern void pushHsimRtnCtxt(void* pcode); +extern void popHsimRtnCtxt(); +extern EBLK* loopReportInlinedSched0Wrapper(EBLK *peblk); +extern void loopReportSched0Wrapper(EBLK *peblk, unsigned int sfType, unsigned int fTH, struct dummyq_struct* pq); +extern void loopReportSchedSemiLerWrapper(EBLK *peblk, int sfType); +extern void CallGraphPushNodeAndAddToGraph(UP flatNode, UP instNum, U dummy); +extern void CallGraphPopNode(void); +extern RP elabGetIpTpl(U in); +extern U rmaEvalBitBothEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQXW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval01EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval0XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval10EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval1XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX1EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX0EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitPosEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitBothEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern void rmaScheduleNbaGate(RP pcode, scalar val); +extern void rmaEvalRtlEdgeLoads(RmaRtlEdgeBlockHdr *phdr, US clkEdge, scalar clkVal, scalar prevClkVal, scalar val4, scalar prevval4, scalar master4val); +extern void rmaEvaluateDynamicGateLoadsCg(RP p, scalar s); +extern void rmaEvaluateFusedWithDynamicGateLoadsCg(RP p, scalar s); +extern void rmaScheduleGatedClockEdgeLoadNew(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaScheduleGatedClockEdgeLoad(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaRemoveNonEdgeLoads(UB* pcode); +extern void rmaRecordEvents(HsimNodeRecord *pnr); +extern void handlePCBs(UB* p, U i); +extern void markMasterClkOvaLists(U fdbs, RP p); +extern void rmaChildClockPropAfterWrite(UB* p); +extern void rmaSchedChildClockPropAfterWrite(UB* p, UB* pmasterList, UB val); +extern void HDLCosimProcessDUTInputChange(U inputId, void* val); +extern void rmaChangeListForMovedGates(UB clkVal, UB f10Edge, UB* subMasterVal, UB* plist, RP* p, U count); +extern void rmaEvalSeqPrimLoadsByteArray(UB* pcode, UB val, UB prevval4); +extern void rmaEvalSeqPrimLoadsByteArrayX(UB* pcode, UB val, UB prevval4); +extern void vcsRmaEvalSeqPrimLoadsByteArraySCT(UB* pcode, UB val, UB prevval4, U c); +extern void vcsAbortForBadEBlk(void); +extern scalar edgeChangeLookUp[4][4]; +extern void Wsvvar_sched_virt_intf_eval(RP* ptr); +extern void vcs_hwcosim_drive_dut_scalar(uint id, char val); +extern void vcs_hwcosim_drive_dut_vector_4state(uint id, vec32* val); +extern U vcs_rmaGetClkValForSeqUdpLayoutOnClkOpt(UB* poutput); +extern U rmaIsS2State(scalar s); +extern U rmaIsV2State(vec32* pval, U cbits); +extern U rmaIsW2State(vec32* pval, U cbits); +extern U rmaIsE2State(scalar* pval, U cbits); +extern void rmaUpdateRecordFor2State(HsimNodeRecord* record, U f2state); +typedef void (*FuncPtr)(); +static inline U asm_bsf (U in) +{ +#if defined(linux) + U out; +#if !defined(__aarch64__) + asm ("movl %1, %%eax; bsf %%eax, %%eax; movl %%eax, %0;" + :"=r"(out) + :"r"(in) + :"%eax" + ); +#else + out = ffs(in) - 1; +#endif + return out; +#else + return 0; +#endif +} + + +#ifdef __cplusplus +extern "C" { +#endif +void hs_0_M_0_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_0_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_1_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_1_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_2_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_2_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_3_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_3_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_4_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_4_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_5_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_5_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_5_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_6_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_7_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_7_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_8_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_8_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_9_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_10_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_11_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_12_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_13_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_14_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_15_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_17_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_18_0__simv_daidir (UB * pcode, scalar val); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + } +#endif +#endif /*__DO_RMAHDR_*/ + diff --git a/sim/therm_chip_top/csrc/rmapats.m b/sim/therm_chip_top/csrc/rmapats.m new file mode 100644 index 0000000..e69de29 diff --git a/sim/therm_chip_top/csrc/rmapats.o b/sim/therm_chip_top/csrc/rmapats.o new file mode 100644 index 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+// stubs for Hil functions +#ifdef __cplusplus +extern "C" { +#endif +void __Hil__Static_Init_Func__(void) {} +#ifdef __cplusplus +} +#endif + diff --git a/sim/therm_chip_top/csrc/rmar.h b/sim/therm_chip_top/csrc/rmar.h new file mode 100644 index 0000000..77865aa --- /dev/null +++ b/sim/therm_chip_top/csrc/rmar.h @@ -0,0 +1,18 @@ +#ifndef _RMAR1_H_ +#define _RMAR1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __DO_RMAHDR_ +#include "rmar0.h" +#endif /*__DO_RMAHDR_*/ + +extern UP rmaFunctionRtlArray[]; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/sim/therm_chip_top/csrc/rmar.o b/sim/therm_chip_top/csrc/rmar.o new file mode 100644 index 0000000000000000000000000000000000000000..1989370b590c66b6e560361c3b68a8b3beb9b454 GIT binary patch literal 1232 zcmbu7OHKko5Qb|26(0*UE=+JSx)BoTAc8S2%tXRNV_f)HcbZ`gLzCg{d1cm$5& z-b;85;{mh^x}hD$jaC9x^>zJK{g~&U1b$htl0 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+Verdi_1\qBaseWindowNextStateGroup\5\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\size=@Size(1017 706) +Verdi_1\qBaseWindowNextStateGroup\5\geometry_x=-10 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_y=20 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_width=1017 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_height=706 + +[qBaseWindow_saveRestoreSession_group] +10=/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=453 +Verdi_1\position.y=103 +Verdi_1\width=1017 +Verdi_1\height=706 diff --git a/sim/therm_chip_top/novas.rc b/sim/therm_chip_top/novas.rc new file mode 100644 index 0000000..aff56d4 --- /dev/null +++ b/sim/therm_chip_top/novas.rc @@ -0,0 +1,1310 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwWarnMsgDlg = 650,407,600,250 +QwUserAskDlg = 809,434,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/verdiLog/novas_autosave.ses +2 = /home/shbyang/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VCS +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = 453 103 1017 706 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 1017 282 100 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/shbyang/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = shbyang +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1017 282 100 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/sim/therm_chip_top/novas_dump.log b/sim/therm_chip_top/novas_dump.log new file mode 100644 index 0000000..c87e0bc --- /dev/null +++ b/sim/therm_chip_top/novas_dump.log @@ -0,0 +1,347 @@ +####################################################################################### +# log primitive debug message of FSDB dumping # +# This is for R&D to analyze when there are issues happening when FSDB dump # +####################################################################################### +ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status') +ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback') +ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback') +ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name') +ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info') +ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info') +ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback') +ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info') +ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle') +ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle') +ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle') +ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent') +ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope') +ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled') +ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted') +ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue') +ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue') +ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue') +ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb') +ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb') +ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode') +ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info') +ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init') +ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk') +ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores') +ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode') +ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion') +ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp') +ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady') +ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback') +ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle') +ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst') +ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle') +ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig') +ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo') +ANF: msvRelease('./simv: undefined symbol: msvRelease') +ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc') +ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback') +ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback') +ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback') +ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue') +ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback') +ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe') +ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo') +ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo') +ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit') +ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync') +ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile') +ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback') +ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback') +ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback') +ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback') +ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus') +ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type') +ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key') +ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info') +ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info') +ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info') +ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info') +ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module') +ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope') +ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable') +ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi') +ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id') +ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi') +ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free') +ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope') +ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable') +ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi') +ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone') +ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free') +ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key') +ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare') +ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr') +ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback') +ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback') +ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force') +ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback') +ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback') +ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback') +ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data') +ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback') +ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr') +ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr') +ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted') +ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi') +ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id') +ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type') +ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback') +ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name') +ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt') +ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option') +ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode') +ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var') +ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis') +ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id') +ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback') +ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback') +ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr') +VCS compile option: + option[0]: ./simv + option[1]: sync:busywait + option[2]: -l + option[3]: /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 + option[4]: -Mcc=gcc + option[5]: -Mcplusplus=g++ + option[6]: -Masflags= + option[7]: -Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + option[8]: -Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include + option[9]: -Mldflags= -rdynamic + option[10]: -Mout=simv + option[11]: -Mamsrun= + option[12]: -Mvcsaceobjs= + option[13]: -Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so + option[14]: -Mexternalobj= + option[15]: -Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + option[16]: -Mcrt0= + option[17]: -Mcrtn= + option[18]: -Mcsrc= + option[19]: -Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl + option[20]: -l + option[21]: compile.log + option[22]: -full64 + option[23]: -j8 + option[24]: +lint=TFIPC-L + option[25]: +v2k + option[26]: -debug_access+pp + option[27]: +vpi + option[28]: +vcsd1 + option[29]: +itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab + option[30]: -lca + option[31]: -q + option[32]: -timescale=1ns/1ps + option[33]: +nospecify + option[34]: -cm + option[35]: line+cond+fsm+tgl+branch + option[36]: -cm_dir + option[37]: ./coverage/simv.vdb + option[38]: -picarchive + option[39]: -P + option[40]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab + option[41]: -fsdb + option[42]: -sverilog + option[43]: -gen_obj + option[44]: -f + option[45]: filelist_vlg.f + option[46]: -load + option[47]: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd + option[48]: timescale=1ns/1ps +Chronologic Simulation VCS Release O-2018.09-SP2_Full64 +Linux 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64 +CPU cores: 96 +Limit information: +====================================== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8192 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +====================================== +(Special)Runtime environment variables: + +Runtime environment variables: +INNOVUS_HOME=/opt/cadence/INNOVUS181 +VNCDESKTOP=cryo1:17 (shbyang) +MGC_PDF_REDER=evince +XDG_SESSION_ID=c5 +SSH_AGENT_PID=6119 +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +HOSTNAME=cryo1 +IMSETTINGS_INTEGRATE_DESKTOP=yes +CDSROOT=/opt/cadence/IC618 +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +HOST=cryo1 +TERM=xterm-256color +XDG_MENU_PREFIX=gnome- +VTE_VERSION=5204 +SHELL=/bin/csh +MAKEFLAGS= +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/33c4f0fe_b1af_4925_918d_f401e6285844 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +CDS_LOAD_ENV=CWD +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +QTDIR=/usr/lib64/qt-3.3 +QTINC=/usr/lib64/qt-3.3/include +MENTOR_HOME=/opt/mentor +IMSETTINGS_MODULE=none +QT_GRAPHICSSYSTEM_CHECKED=1 +GROUP=cryo +USER=shbyang +LD_LIBRARY_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/shared/pkgs/icv/tools/calibre_client/lib/64 +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +GNOME_TERMINAL_SERVICE=:1.2258 +W3264_NO_HOST_CHECK=1 +CDS=/opt/cadence/IC618 +HOSTTYPE=x86_64-linux +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +MAKELEVEL=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/5094,unix/unix:/tmp/.ICE-unix/5094 +SNPSLMD_LICENSE_FILE=27050@192.168.1.77 +MFLAGS= +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +GNOME_SHELL_SESSION_MODE=classic +GENUS_HOME=/opt/cadence/GENUS152 +MAIL=/var/spool/mail/shbyang +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +PATH=/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/opt/compiler/V0P100:/opt/synopsys/fpga/K-2015.09/bin:/opt/synopsys/vc_stat/vc_static/V-2023.12/bin:/opt/synopsys/wv/N-2017.12-SP2/bin:/opt/synopsys/hspice/N-2017.12-SP2/hspice/bin:/opt/synopsys/idq/O-2018.06-SP1/linux64/iddq/bin:/opt/synopsys/txs/O-2018.06-SP1/bin:/opt/synopsys/lc/O-2018.06-SP1/bin:/opt/synopsys/starrc/O-2018.06-SP1/bin:/opt/synopsys/fm/L-2016.03-SP1/bin:/opt/synopsys/pwr/O-2018.06-SP3/bin:/opt/synopsys/pts/O-2018.06-SP1/bin:/opt/synopsys/syn/O-2018.06-SP1/bin:/opt/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve/bin:/opt/synopsys/vcs-mx/O-2018.09-SP2/bin:/opt/synopsys/scl/2018.06/linux64/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/:/opt/cadence/IC618/tools/bin:/opt/cadence/IC618/tools/dfII/bin:/opt/cadence/IC618/tools/plot/bin:/opt/cadence/SPECTRE181/bin:/opt/cadence/SPECTRE181/tools/bin:/opt/cadence/INNOVUS181/bin:/opt/cadence/INNOVUS181/tools/bin:/opt/cadence/GENUS152/bin:/opt/cadence/GENUS152/tools/bin:/opt/cadence/INCISIVE152/bin:/opt/cadence/INCISIVE152/tools/bin:/opt/cadence/INCISIVE152/tools.lnx86/bin:/opt/cadence/INCISIVE152/tools/dfII/bin:/opt/cadence/INCISIVE152/tools.lnx86/dfII/bin:/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/bin:/opt/xilinx/Vivado/2019.2//bin:/opt/xilinx/Vivado/2019.2//bin/unwrapped/lnx64.o/ +SPECTRE_DEFAULTS=-E +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +QT_IM_MODULE=ibus +_=./simv +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +CDS_SPECTRERF_FBENABLE=1 +CADENCE_DIR=/opt/cadence/IC618 +PWD=/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top +CDSDIR=/opt/cadence/IC618 +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +XMODIFIERS=@im=ibus +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +LANG=C +VRST_HOME=/opt/cadence/INCISIVE152 +CDSHOME=/opt/cadence/IC618 +CDS_Netlisting_Mode=Analog +SYNOPSYS=/opt/synopsys +AMS_ENABLE_NOISE=YES +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +DBUS_STARTER_BUS_TYPE=session +SHLVL=5 +HOME=/home/shbyang +OSTYPE=linux +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +CDS_AUTO_64BIT=ALL +CADHOME=/opt/cadence +VENDOR=unknown +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +LOGNAME=shbyang +MACHTYPE=x86_64 +QTLIB=/usr/lib64/qt-3.3/lib +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67 +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +CDS_LIC_FILE=/opt/cadence/license/license.dat +MOZILLA_HOME=/usr/bin/firefox +LESSOPEN=||/usr/bin/lesspipe.sh %s +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +SCL_HOME=/opt/synopsys/scl/2018.06 +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +CDS_ENABLE_VMS=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +DISPLAY=unix:17 +XDG_RUNTIME_DIR=/run/user/1019 +CDS_LIC_ONLY=1 +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +CDS_ROOT=/opt/cadence/IC618 +XILINX_HOME=/opt/xilinx +INCISIVE_HOME=/opt/cadence/INCISIVE152 +XDG_CURRENT_DESKTOP=GNOME +CDS_SPECTRE_FBENABLE=1 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +CDS_INST_DIR=/opt/cadence/IC618 +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +COLORTERM=truecolor +VCS_HEAP_EXEC=true +VCS_PATHMAP_PRELOAD_DONE=1 +VCS_STACK_EXEC=true +VCS_EXEC_DONE=1 +LC_ALL=C +DVE=/opt/synopsys/vcs-mx/O-2018.09-SP2/gui/dve +SPECMAN_OUTPUT_TO_TTY=1 +Runtime command line arguments: +argv[0]=./simv +argv[1]=sync:busywait +argv[2]=-l +291 profile - 100 + CPU/Mem usage: 0.050 sys, 0.220 user, 282.41M mem +292 Tue Apr 7 09:38:20 2026 +293 pliAppInit +294 FSDB_GATE is set. +295 FSDB_RTL is set. +296 Enable Parallel Dumping. +297 pliAppMiscSet: New Sim Round +298 pliEntryInit +299 LIBSSCORE=found /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting. +300 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +301 (C) 1996 - 2019 by Synopsys, Inc. +302 sps_call_fsdbDumpfile_main at 0 : ./TB.sv(22) +303 argv[0]: (wave.fsdb) +304 *Verdi* : Create FSDB file 'wave.fsdb' +305 compile option from '/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/vcs_rebuild'. +306 "vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1" +307 FSDB_VCS_ENABLE_FAST_VC is enable +308 sps_call_fsdbDumpvars_vd_main at 0 : ./TB.sv(23) +309 [spi_vcs_vd_ppi_create_root]: no upf option +310 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. +311 *Verdi* : Begin traversing the scopes, layer (0). +312 *Verdi* : End of traversing. +313 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.080 sys, 0.230 user, 378.79M mem + incr: 0.000 sys, 0.010 user, 8.98M mem + accu: 0.000 sys, 0.010 user, 8.98M mem + accu incr: 0.000 sys, 0.010 user, 8.98M mem + + Count usage: 224 var, 123 idcode, 86 callback + incr: 224 var, 123 idcode, 86 callback + accu: 224 var, 123 idcode, 86 callback + accu incr: 224 var, 123 idcode, 86 callback +314 Tue Apr 7 09:38:20 2026 +315 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.080 sys, 0.230 user, 379.84M mem + incr: 0.000 sys, 0.000 user, 1.05M mem + accu: 0.000 sys, 0.010 user, 10.04M mem + accu incr: 0.000 sys, 0.000 user, 1.05M mem + + Count usage: 224 var, 123 idcode, 86 callback + incr: 0 var, 0 idcode, 0 callback + accu: 224 var, 123 idcode, 86 callback + accu incr: 0 var, 0 idcode, 0 callback +316 Tue Apr 7 09:38:20 2026 +317 End of simulation at 17814400000 +318 Tue Apr 7 09:38:21 2026 +319 Begin FSDB profile info: +320 FSDB Writer : bc1(1815118) bcn(1365370) mtf/stf(0/1) +FSDB Writer elapsed time : flush(0.171826) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) +FSDB Writer cpu time : MT Compression : 0 +321 End FSDB profile info +322 Parallel profile - Flush:3 Expand:0 ProduceWait:0 ConsumerWait:27 BlockUsed:34 +323 ProduceTime:1.172810727 ConsumerTime:0.465192911 Buffer:64MB +324 SimExit +325 Sim process exit diff --git a/sim/therm_chip_top/rx_data.txt b/sim/therm_chip_top/rx_data.txt new file mode 100644 index 0000000..1254b7e --- /dev/null +++ b/sim/therm_chip_top/rx_data.txt @@ -0,0 +1,8 @@ +20260406 +000003e8 +025800a0 +0000c350 +00fff060 +00000b02 +aa000b02 +00000b02 diff --git a/sim/therm_chip_top/sim.log b/sim/therm_chip_top/sim.log new file mode 100644 index 0000000..74a6feb --- /dev/null +++ b/sim/therm_chip_top/sim.log @@ -0,0 +1,61 @@ +Chronologic VCS simulator copyright 1991-2018 +Contains Synopsys proprietary information. +Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Apr 7 09:38 2026 +*Verdi* Loading libsscore_vcs201809.so +FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +(C) 1996 - 2019 by Synopsys, Inc. +*Verdi* : Create FSDB file 'wave.fsdb' +*Verdi* : Begin traversing the scopes, layer (0). +*Verdi* : End of traversing. +------- Step 1: Configure Thermometer Regs ------- +[ 775170000] Byte 0: 0x20 +[ 862030000] Byte 1: 0x26 +[ 948890000] Byte 2: 0x04 +[ 1035750000] Byte 3: 0x06 +[ 1035750000] Packet (32-bit): 0x20260406 +[ 1469570000] Byte 0: 0x00 +[ 1556430000] Byte 1: 0x00 +[ 1643290000] Byte 2: 0x03 +[ 1730150000] Byte 3: 0xe8 +[ 1730150000] Packet (32-bit): 0x000003e8 +[ 2163970000] Byte 0: 0x02 +[ 2250830000] Byte 1: 0x58 +[ 2337690000] Byte 2: 0x00 +[ 2424550000] Byte 3: 0xa0 +[ 2424550000] Packet (32-bit): 0x025800a0 +[ 2858370000] Byte 0: 0x00 +[ 2945230000] Byte 1: 0x00 +[ 3032090000] Byte 2: 0xc3 +[ 3118950000] Byte 3: 0x50 +[ 3118950000] Packet (32-bit): 0x0000c350 +------- Step 2: Running Concurrent Tasks ------- +[3474400000] Start generating signal: 400 kHz +[ 3552770000] Byte 0: 0x00 +[ 3639630000] Byte 1: 0xff +[ 3726490000] Byte 2: 0xf0 +[ 3813350000] Byte 3: 0x60 +[ 3813350000] Packet (32-bit): 0x00fff060 +[ 5474400000] TX: Sending Read Request during active reporting... +[ 6247170000] Byte 0: 0x00 +[ 6334030000] Byte 1: 0x00 +[ 6420890000] Byte 2: 0x0b +[ 6507750000] Byte 3: 0x02 +[ 6507750000] Packet (32-bit): 0x00000b02 +[ 8330370000] Byte 0: 0xaa +[ 8417230000] Byte 1: 0x00 +[ 8504090000] Byte 2: 0x0b +[ 8590950000] Byte 3: 0x02 +[ 8590950000] Packet (32-bit): 0xaa000b02 +[ 9054770000] Byte 0: 0x00 +[ 9141630000] Byte 1: 0x00 +[ 9228490000] Byte 2: 0x0b +[ 9315350000] Byte 3: 0x02 +[ 9315350000] Packet (32-bit): 0x00000b02 +Test Done. +$finish called from file "./TB.sv", line 221. +[RX] File closed at 17814400000 +$finish at simulation time 17814400000 + V C S S i m u l a t i o n R e p o r t +Time: 17814400000 ps +CPU Time: 1.630 seconds; Data structure size: 0.0Mb +Tue Apr 7 09:38:21 2026 diff --git a/sim/therm_chip_top/simv b/sim/therm_chip_top/simv new file mode 100644 index 0000000000000000000000000000000000000000..096a7ae7577012c147e45811c81f460a1d284f77 GIT binary patch literal 923936 zcmdSCd0s|e{%?KNEn@yPG>aaS-}y(@~I z(NvGHX57T{Gj5v4`071x8Y7jydjud+k0`1aGn&_n8O`gdcO7*EmwH$GM}4DopAdIn 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++itf+/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab ++lint=TFIPC-L ++nospecify ++v2k ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so +-Mout=simv +-Msaverestoreobj=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/opt/synopsys/vcs-mx/O-2018.09-SP2/include +-P +-cm +-cm_dir +-debug_access+pp +-f filelist_vlg.f +-fsdb +-full64 +-gen_obj +-l +-lca +-picarchive +-q +-sverilog +-timescale=1ns/1ps +./coverage/simv.vdb +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcs1 +/opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +compile.log +line+cond+fsm+tgl+branch +105 +sysc_uni_pwd=/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top +starRC_HOME=/opt/synopsys/starrc/O-2018.06-SP1 +XMODIFIERS=@im=ibus +XILINX_HOME=/opt/xilinx +XDG_SESSION_ID=c5 +XDG_RUNTIME_DIR=/run/user/1019 +XDG_MENU_PREFIX=gnome- +XDG_CURRENT_DESKTOP=GNOME +WV_HOME=/opt/synopsys/wv/N-2017.12-SP2 +W3264_NO_HOST_CHECK=1 +VTE_VERSION=5204 +VRST_HOME=/opt/cadence/INCISIVE152 +VNCDESKTOP=cryo1:17 (shbyang) +VMR_MODE_FLAG=64 +VIVADO_HOME=/opt/xilinx/Vivado/2019.2/ +VERDI_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +VENDOR=unknown +VC_STATIC_HOME=/opt/synopsys/vc_stat/vc_static/V-2023.12 +VCS_MX_HOME_INTERNAL=1 +VCS_MODE_FLAG=64 +VCS_LOG_FILE=compile.log +VCS_LCAMSG_PRINT_OFF=1 +VCS_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH=linux64 +UNAME=/bin/uname +TXS_HOME=/opt/synopsys/txs/O-2018.06-SP1 +TOOL_HOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64 +SYN_HOME=/opt/synopsys/syn/O-2018.06-SP1 +SYNOPSYS=/opt/synopsys +SSH_AUTH_SOCK=/run/user/1019/keyring/ssh +SSH_AGENT_PID=6119 +SPECTRE_HOME=/opt/cadence/SPECTRE181 +SPECTRE_DEFAULTS=-E +SPECMAN_HOME=/opt/cadence/INCISIVE152/components/sn +SPECMAN_DIR=/opt/cadence/INCISIVE152/components/sn +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/5094,unix/unix:/tmp/.ICE-unix/5094 +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/opt/synopsys/scl/2018.06 +QT_IM_MODULE=ibus +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib64/qt-3.3/lib +QTINC=/usr/lib64/qt-3.3/include +QTDIR=/usr/lib64/qt-3.3 +PWR_HOME=/opt/synopsys/pwr/O-2018.06-SP3 +PT_HOME=/opt/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +OSTYPE=linux +OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44x +NOVAS_HOME=/opt/synopsys/verdi/Verdi_O-2018.09-SP2 +MOZILLA_HOME=/usr/bin/firefox +MGLS_LICENSE_FILE=/opt/mentor/license/license.dat +MGC_PDF_REDER=evince +MGC_LIB_PATH=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11/lib +MGC_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +MGC_CALIBRE_SAVE_ALL_RUNSET_VALUES=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_SAVE_MESSENGER_CELL=1 +MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED=1 +MFLAGS= +MENTOR_HOME=/opt/mentor +MAKELEVEL=1 +MAKEFLAGS= +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_HOME=/opt/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +INNOVUS_HOME=/opt/cadence/INNOVUS181 +INCISIVE_HOME=/opt/cadence/INCISIVE152 +IMSETTINGS_MODULE=none +IMSETTINGS_INTEGRATE_DESKTOP=yes +IDQ_HOME=/opt/synopsys/idq/O-2018.06-SP1 +HSPICE_HOME=/opt/synopsys/hspice/N-2017.12-SP2 +HOSTTYPE=x86_64-linux +GROUP=cryo +GNOME_TERMINAL_SERVICE=:1.2258 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/33c4f0fe_b1af_4925_918d_f401e6285844 +GNOME_SHELL_SESSION_MODE=classic +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +GENUS_HOME=/opt/cadence/GENUS152 +FPGA_HOME=/opt/synopsys/fpga/K-2015.09 +FM_HOME=/opt/synopsys/fm/L-2016.03-SP1 +DBUS_STARTER_BUS_TYPE=session +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-u35dU5UhQE,guid=93d267a29dee2a5090398c3969bcbf67 +COLORTERM=truecolor +CDS_SPECTRE_FBENABLE=1 +CDS_SPECTRERF_FBENABLE=1 +CDS_ROOT=/opt/cadence/IC618 +CDS_Netlisting_Mode=Analog +CDS_LOAD_ENV=CWD +CDS_LIC_ONLY=1 +CDS_LIC_FILE=/opt/cadence/license/license.dat +CDS_INST_DIR=/opt/cadence/IC618 +CDS_ENABLE_VMS=1 +CDS_AUTO_64BIT=ALL +CDSROOT=/opt/cadence/IC618 +CDSHOME=/opt/cadence/IC618 +CDSDIR=/opt/cadence/IC618 +CDS=/opt/cadence/IC618 +CALIBRE_HOME=/opt/mentor/Calibre2019/aoj_cal_2019.3_15.11 +CALIBRE_ENABLE_SKILL_PEXBA_MODE=1 +CADHOME=/opt/cadence +CADENCE_DIR=/opt/cadence/IC618 +AMS_ENABLE_NOISE=YES +0 +14 +1775464866 ./TB.sv +1775377742 ../../rtl/therm/pulse_cnt.v +1775454778 ../../rtl/therm/digital_thermometer.v +1774925224 ../../rtl/uart/uart_byte_tx.v +1775370228 ../../rtl/uart/uart_top_32bit.v +1775459928 ../../rtl/uart/uart_ctrl_sysreg.v +1774924538 ../../rtl/uart/uart_byte_rx.v +1775525487 ../../rtl/digital_top.v +1774930574 ../../rtl/systemregfile/sirv_gnrl_dffs.v +1775525827 ../../rtl/systemregfile/my_systemregfile.v +1551421444 /opt/synopsys/vcs-mx/O-2018.09-SP2/include/cm_vcsd.tab +1775464043 filelist_vlg.f +1550753332 /opt/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1551421246 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab +4 +1551422344 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvirsim.so +1551421792 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/liberrorinf.so +1551421768 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so +1551421789 /opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/libvfs.so +1775525900 simv.daidir +-1 partitionlib diff --git a/sim/therm_chip_top/simv.daidir/_131020_archive_1.so b/sim/therm_chip_top/simv.daidir/_131020_archive_1.so new file mode 100644 index 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M_EQU AND RET +bcid 2 2 WIDTH,30 CALL_ARG_VAL,2,0 OPT_CONST,216 WIDTH,1 M_EQU WIDTH,4 CALL_ARG_VAL,3,0 OPT_CONST,9 WIDTH,1 M_EQU AND RET +bcid 3 3 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 4 4 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 5 5 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 6 6 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 7 7 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 8 8 WIDTH,25 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 9 9 WIDTH,24 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,1000 MULTIPLY WIDTH,24 CALL_ARG_VAL,3,0 WIDTH,32 PAD DIVIDE OPT_CONST,0 WIDTH,24 SLICE,1 RET +bcid 10 10 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET diff --git a/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file b/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/sim/therm_chip_top/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/sim/therm_chip_top/simv.daidir/cgname.json b/sim/therm_chip_top/simv.daidir/cgname.json new file mode 100644 index 0000000..7cac6e2 --- /dev/null +++ b/sim/therm_chip_top/simv.daidir/cgname.json @@ -0,0 +1,50 @@ +{ + "TB": [ + "TB", + "sH4Fc", + "module", + 7 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 4 + ], + "std": [ + "std", + "reYIK", + "module", + 1 + ], + "sirv_gnrl_dffrs": [ + "sirv_gnrl_dffrs", + "QHiet", + "module", + 5 + ], + "sirv_gnrl_dfflrs": [ + "sirv_gnrl_dfflrs", + "ZJgwY", + "module", + 2 + ], + "sirv_gnrl_dfflrd": [ + "sirv_gnrl_dfflrd", + "Uye5v", + "module", + 3 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 6 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 8 + ] +} \ No newline at end of file diff --git a/sim/therm_chip_top/simv.daidir/covg_defs b/sim/therm_chip_top/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/.version b/sim/therm_chip_top/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..ff98673 --- /dev/null +++ b/sim/therm_chip_top/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-SP2_Full64 +Build Date = Feb 28 2019 22:34:30 +RedHat +Compile Location: /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/sim/therm_chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000000000000000000000000000000000000..8f08730f31e604f6cb7754cc59b68e62c235eda4 GIT binary patch literal 2271 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-0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/opt/synopsys/vcs-mx/O-2018.09-SP2/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib:/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/opt/synopsys/vcs-mx/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_ik1qVk.xml.gz" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db b/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100644 index 0000000..46692b0 --- /dev/null +++ b/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../../../.. +fi + +if [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat b/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_ik1qVk.xml.gz b/sim/therm_chip_top/simv.daidir/debug_dump/fsearch/idents_ik1qVk.xml.gz new file mode 100644 index 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100644 index 0000000..0909dc0 --- /dev/null +++ b/sim/therm_chip_top/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-j8' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+pp' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-cm' 'line+cond+fsm+tgl+branch' '-cm_dir' './coverage/simv.vdb' '-f' 'filelist_vlg.f' 2>&1 diff --git a/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db b/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..b58f7c9 --- /dev/null +++ b/sim/therm_chip_top/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,691 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 13 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 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b/sim/therm_chip_top/verdiLog/compiler.log new file mode 100644 index 0000000..703c596 --- /dev/null +++ b/sim/therm_chip_top/verdiLog/compiler.log @@ -0,0 +1,26 @@ +*design* DebussyLib (btIdent Verdi_O-2018.09-SP2) +Command arguments: + +define+verilog + -sverilog + -f filelist_vlg.f + ../../rtl/systemregfile/my_systemregfile.v + ../../rtl/systemregfile/sirv_gnrl_dffs.v + ../../rtl/digital_top.v + ../../rtl/uart/uart_byte_rx.v + ../../rtl/uart/uart_ctrl_sysreg.v + ../../rtl/uart/uart_top_32bit.v + ../../rtl/uart/uart_byte_tx.v + ../../rtl/therm/digital_thermometer.v + ../../rtl/therm/pulse_cnt.v + ./TB.sv + -top + TB + +Highest level modules: +sirv_gnrl_dfflrs +sirv_gnrl_dffl +sirv_gnrl_dffrs +sirv_gnrl_ltch +TB + +Total 0 error(s), 0 warning(s) diff --git a/sim/therm_chip_top/verdiLog/exe.log b/sim/therm_chip_top/verdiLog/exe.log new file mode 100644 index 0000000..e69de29 diff --git a/sim/therm_chip_top/verdiLog/novas.log b/sim/therm_chip_top/verdiLog/novas.log new file mode 100644 index 0000000..157ce72 --- /dev/null +++ b/sim/therm_chip_top/verdiLog/novas.log @@ -0,0 +1,10 @@ +Verdi (R) + +Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit) -- Thu Feb 21 04:40:56 PDT 2019 + +Copyright (c) 1999 - 2019 Synopsys, Inc. +This software and the associated documentation are proprietary to Synopsys, Inc. +This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. +All other use, reproduction, or distribution of this software is strictly prohibited. + + diff --git a/sim/therm_chip_top/verdiLog/novas.rc b/sim/therm_chip_top/verdiLog/novas.rc new file mode 100644 index 0000000..497f96f --- /dev/null +++ b/sim/therm_chip_top/verdiLog/novas.rc @@ -0,0 +1,1306 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwWarnMsgDlg = 650,407,600,250 +QwUserAskDlg = 953,554,324,130 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/verdiLog/novas_autosave.ses +2 = /home/shbyang/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = 0 0 1017 706 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 1017 282 100 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/shbyang/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = shbyang +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1017 282 100 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/sim/therm_chip_top/verdiLog/novas_autosave.ses b/sim/therm_chip_top/verdiLog/novas_autosave.ses new file mode 100644 index 0000000..116bad9 --- /dev/null +++ b/sim/therm_chip_top/verdiLog/novas_autosave.ses @@ -0,0 +1,83 @@ +@verdi rc file Version 1.0 +[General] +saveDB = TRUE +relativePath = FALSE +saveSingleView = FALSE +saveNWaveWinId = +VerdiVersion = Verdi_O-2018.09-SP2 +[KeyNote] +Line1 = Automatic Backup 0 +Line2 = Save Open Database Information: Yes +Line3 = Path Option: Absolute Paths +Line4 = Windows Option: All Windows +[TestBench] +ConstrViewShow = 0 +InherViewShow = 0 +FSDBMsgShow = 0 +AnnotationShow = 0 +Console = FALSE +powerDumped = 0 +[hb] +postSimFile = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb +syncTime = 8000570000 +viewport = 453 103 1017 706 0 0 256 1015 +activeNode = "TB.u_digital_top" +activeScope = "TB.u_digital_top" +activeFile = "../../rtl/digital_top.v" +interactiveMode = False +viewType = Source +simulatorMode = False +sourceBeginLine = 81 +baMode = False +srcLineNum = True +AutoWrap = True +IdentifyFalseLogic = False +syncSignal = False +traceMode = Hierarchical +showTraceInSchema = True +paMode = False +funcMode = False +powerAwareAnnot = True +amsAnnot = True +traceCrossHier = True +DnDtraceCrossHierOnly = True +traceIncTopPort = False +leadingZero = False +signalPane = False +Scope1 = "TB.u_digital_top" +Scope2 = "TB" +multipleSelection = 1 85 5 0 0 +sdfCheckUndef = FALSE +simFlow = FALSE +[hb.design] +importCmd = "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +invokeDir = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top +[hb.sourceTab.1] +scope = TB.u_digital_top +File = /home/shbyang/Desktop/workplace/therm_design/rtl/digital_top.v +Line = 82 +[nMemoryManager] +WaveformFile = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb +UserActionNum = 0 +nMemWindowNum = 0 +[wave.0] +viewPort = 0 27 1017 282 100 65 +primaryWindow = TRUE +SessionFile = /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/verdiLog/novas_autosave.ses.wave.0 +displayGrid = FALSE +hierarchicalName = FALSE +snap = TRUE +displayLeadingZeros = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +highlightGlitchs = FALSE +waveformSyncCursorMarker = FALSE +waveformSyncHorizontalRange = FALSE +waveformSyncVerticalscroll = FALSE +displayErrors = TRUE +displayMsgSymbols = TRUE +showMsgDescriptions = TRUE +autoFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE diff --git a/sim/therm_chip_top/verdiLog/novas_autosave.ses.config b/sim/therm_chip_top/verdiLog/novas_autosave.ses.config new file mode 100644 index 0000000..5d626fd --- /dev/null +++ b/sim/therm_chip_top/verdiLog/novas_autosave.ses.config @@ -0,0 +1,55 @@ +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 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zdU$%KkGh=7_0ni#cI&*-`WX%VCNKko*>e27tDynPj=7>#Bl@?UsMjC+#uokDu!hfJtyZ+kMkRu6xk9L41@JggW# zd*-B{ocDb-f_gsCTxIpCn#xfQ`Uqi)A7_x^L05Nh&C?+|tG?3w5+8#8O9ep%t1W|@NJ z)7nE9{H|^hkDEdC-XcwbZ9Cs6!fRyfTZEGU)>17K<``Kv9-*T1nwRl4Z=VmNv-u8d z!xv~|O!b<%x99aMr=+oCHsTB~?FPKW-|!QAWfHhABU>mR+zceJI5kU?fEEMMh> zNyv@4$iA1gxs9X9gzk4gPnN$!=sC@2&5ZV_BlQpJ{hE9+|FI>L2{NR1^XiRxF;(w~ zdHm2?y_P{DRutmEmi6Y_$I{plu2qdB{X6up3nbUk}Uzxzir=Q+mN z1*U))HJaHK0slUgzEeZXJNhMw^QiX5XywzL?uu7OZI;2cDt#0um!Wu>JdaR~C%;w{qeC z?O=QzNk}LDI_L4 +viewPort 0 27 1017 282 100 65 + +; File list: +; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name +openDirFile -d / "" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb" + +; file time scale: +; fileTimeScale ### s|ms|us|ns|ps + +; signal spacing: +signalSpacing 5 + +; windowTimeUnit is used for zoom, cursor & marker +; waveform viewport range +zoom 0.000000 17992544000.000000 +cursor 8000570000.000000 +marker 0.000000 + +; user define markers +; userMarker time_pos marker_name color linestyle +; visible top row signal index +top 4 +; marker line index +markerPos 11 + +; event list +; addEvent event_name event_expression +; curEvent event_name + + + +COMPLEX_EVENT_BEGIN + + +COMPLEX_EVENT_END + + + +; toolbar current search type +; curSTATUS search_type +curSTATUS ByChange + + +addGroup "G1" +activeDirFile "" "/home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb" +addSignal -h 15 /TB/u_digital_top/w_wrdata[31:0] +addSignal -h 15 -holdScope w_addr[24:0] +addSignal -h 15 -holdScope w_wren +addSignal -h 15 -holdScope w_rden +addSignal -h 15 -holdScope w_rddata[31:0] +addSignal -h 15 -holdScope rep_gap_us[23:0] +addSignal -h 15 -holdScope report_en +addSignal -h 15 -holdScope therm_out[23:0] +addSignal -h 15 -holdScope therm_vld +addSignal -h 15 -holdScope temp_85_fre_k[15:0] +addSignal -h 15 -holdScope win_us[23:0] +addGroup "G2" + +; getSignalForm Scope Hierarchy Status +; active file of getSignalForm + diff --git a/sim/therm_chip_top/verdiLog/pes.bat b/sim/therm_chip_top/verdiLog/pes.bat new file mode 100644 index 0000000..7c6e4ac --- /dev/null +++ b/sim/therm_chip_top/verdiLog/pes.bat @@ -0,0 +1,3 @@ +where +detach +quit diff --git a/sim/therm_chip_top/verdiLog/turbo.log b/sim/therm_chip_top/verdiLog/turbo.log new file mode 100644 index 0000000..8c840e3 --- /dev/null +++ b/sim/therm_chip_top/verdiLog/turbo.log @@ -0,0 +1,3 @@ +Command Line: /opt/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -sverilog -f filelist_vlg.f -top TB -ssf wave.fsdb -nologo +uname(Linux cryo1 3.10.0-1160.92.1.el7.x86_64 #1 SMP Tue Jun 20 11:48:01 UTC 2023 x86_64) +au time 105.920698 9.035237 2.165473 delta 1143836672 1143836672 total 1568927744 1568927744 diff --git a/sim/therm_chip_top/verdiLog/verdi.cmd b/sim/therm_chip_top/verdiLog/verdi.cmd new file mode 100644 index 0000000..5746b1d --- /dev/null +++ b/sim/therm_chip_top/verdiLog/verdi.cmd @@ -0,0 +1,66 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "filelist_vlg.f" "-top" "TB" +debLoadSimResult \ + /home/shbyang/Desktop/workplace/therm_design/sim/therm_chip_top/wave.fsdb +wvCreateWindow +srcHBSelect "TB.Unnamed_\$TB_sv_88" -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sig_in" -line 16 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "uart_tx" -line 32 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sig_in" -line 33 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "uart_tx" -line 32 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcAction -pos 99 9 4 -win $_nTrace1 -name "rx_byte" -ctrlKey off +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.u_digital_top" -delim "." +srcHBSelect "TB.u_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "w_wrdata" -line 54 -pos 1 -win $_nTrace1 +srcSelect -signal "w_addr" -line 55 -pos 1 -win $_nTrace1 +srcSelect -signal "w_wren" -line 56 -pos 1 -win $_nTrace1 +srcSelect -signal "w_rden" -line 57 -pos 1 -win $_nTrace1 +srcSelect -signal "w_rddata" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 644769131.234867 -snap {("G1" 5)} +wvSetCursor -win $_nWave2 1381025774.334140 -snap {("G1" 5)} +wvSetCursor -win $_nWave2 2104212772.881356 -snap {("G1" 5)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_neg_40_fre_k" -line 75 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rep_gap_us" -line 77 -pos 2 -win $_nTrace1 +srcSelect -signal "report_en" -line 76 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 78 -pos 2 -win $_nTrace1 +srcSelect -signal "therm_vld" -line 79 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 7863569472.154963 -snap {("G1" 9)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "therm_out" -line 92 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "temp_85_fre_k" -line 88 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "win_us" -line 86 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +debExit diff --git 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-////////////////////////////////////////////////////////////////////////////////// - - -`timescale 1ns / 1ps - -module tb_digital_thermometer; - - reg clk; - reg rst_n; - reg vin; - reg mode; - wire [19:0] freq_x100hz; - wire [15:0] temp_out; - wire temp_valid; - - // 例化待测模块 - digital_thermometer uut ( - .clk (clk), - .rst_n (rst_n), - .vin (vin), - .mode (mode), - .freq_x100hz (freq_x100hz), - .temp_out (temp_out), - .temp_valid (temp_valid) - ); - - // 时钟：50MHz - initial clk = 0; - always #10 clk = ~clk; - - - - -// 测试流程 - initial begin - // 复位 - rst_n = 0; - mode = 0; - #100; - rst_n = 1; - gen_pulse(52,20); - gen_pulse(74,20); - gen_pulse(104.7,20); - gen_pulse(130,20); - mode = 1; - gen_pulse(52,20); - gen_pulse(74,20); - gen_pulse(104.7,20); - gen_pulse(130,20); - - #10000; - $finish; - end - -// -task gen_pulse; - input real freq_kHz; - input [7:0] time_ms; - integer cycles; - integer i; - begin - //操控reg vin - cycles = time_ms * freq_kHz; - vin = 0; - for (i = 0; i < cycles; i = i + 1) begin - vin = 1; - #(500000/freq_kHz); - vin = 0; - #(500000/freq_kHz); - end - end -endtask - - - -endmodule