480 lines
16 KiB
Systemverilog
480 lines
16 KiB
Systemverilog
`timescale 1ns/1ps
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module TB;
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// ====================================================
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// Parameters
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// ====================================================
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parameter FIFO_DEPTH = 64;
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parameter SCRAMBLER_SEED = 32'hFFFFFFFF;
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parameter CLK_PERIOD = 10; // 10ns
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parameter PATN_COUNT = 20'd10; // Training match count
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parameter TAP_STEP = 3'd3; // Delay adjustment step
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// ====================================================
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// Constants (moved to top for visibility)
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// ====================================================
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localparam [31:0] TRAINING_PATN = 32'h68666E6C; // "hfnl"
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localparam [31:0] TRAINING_EXIT = 32'h65786974; // "exit"
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localparam [31:0] FRAME_HEADER = 32'hBCBCBCBC;
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initial begin
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$fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000);
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$fsdbDumpvars();
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$fsdbDumpMDA();
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end
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// ====================================================
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// Signals
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// ====================================================
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logic clk;
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logic rst_n;
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logic [3:0] serial_in;
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logic [19:0] patn_count;
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logic [2:0] tap_step;
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logic link_down;
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logic [2:0] delay_tap;
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logic [12:0] wr_addr;
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logic [511:0] wr_data;
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logic wr_en;
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logic [63:0] byte_mask;
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logic crc_error;
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logic [2 :0] tap_adj_mask = 3'b111; // Delay adjustment mask
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logic [0 :0] tap_force = 1'b0 ; // Delay force to tap_step
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logic tap_adj_req ;
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logic frame_done ;
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logic [31 :0] train_status ;
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logic [31 :0] frame_status ;
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logic always_on = 1'b0 ;
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logic prefilling ;
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logic prefill_start;
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// Added for scrambler test
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logic descram_en;
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logic [31:0] lfsr_lane[0:3]; // 4 independent LFSRs for scrambling
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logic train_ready;
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logic force_train; // Force Training
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// ====================================================
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// DUT Instance
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// ====================================================
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ulink_rx #(
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.FIFO_DEPTH ( FIFO_DEPTH )
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,.SCRAMBLER_SEED ( SCRAMBLER_SEED )
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) dut (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.serial_in ( serial_in )
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,.patn_count ( patn_count )
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,.tap_step ( tap_step )
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,.descram_en ( descram_en ) // now variable
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,.link_down ( link_down )
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,.delay_tap ( delay_tap )
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,.wr_addr ( wr_addr )
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,.wr_data ( wr_data )
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,.wr_en ( wr_en )
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,.byte_mask ( byte_mask )
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,.crc_error ( crc_error )
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,.tap_adj_mask ( tap_adj_mask )
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,.tap_force ( tap_force )
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,.tap_adj_req ( tap_adj_req )
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,.frame_done ( frame_done )
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,.train_status ( train_status )
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,.frame_status ( frame_status )
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,.always_on ( always_on )
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,.prefilling ( prefilling )
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,.prefill_start ( prefill_start )
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,.train_ready ( train_ready )
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,.force_train ( force_train )
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);
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// ====================================================
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// Clock Generation
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// ====================================================
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initial begin
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clk = 0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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// ====================================================
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// Tasks for Stimulus Generation
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// ====================================================
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// Reset task
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task reset;
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begin
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rst_n = 0;
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repeat(5) @(posedge clk);
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rst_n = 1;
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repeat(2) @(posedge clk);
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end
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endtask
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// Send one 128-bit block over 32 cycles
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task send_block;
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input [127:0] block;
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begin
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integer i;
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for (i = 31; i >= 0; i = i - 1) begin
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serial_in[0] = block[i];
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serial_in[1] = block[32 + i];
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serial_in[2] = block[64 + i];
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serial_in[3] = block[96 + i];
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@(posedge clk);
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#0.1;
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end
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end
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endtask
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// Send multiple identical blocks
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task send_blocks;
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input [127:0] block;
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input integer count;
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begin
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repeat(count) send_block(block);
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end
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endtask
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// Send a sequence of 32-bit words (packed into 128-bit blocks)
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task send_words;
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input integer num_words;
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input [31:0] words[0:255];
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begin
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integer word_idx;
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integer j;
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reg [127:0] block;
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word_idx = 0;
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while (word_idx < num_words) begin
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block = 128'h0;
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for (j = 0; j < 4; j = j + 1) begin
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if (word_idx < num_words) begin
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block[32*j +: 32] = words[word_idx];
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word_idx = word_idx + 1;
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end
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end
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send_block(block);
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end
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end
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endtask
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// ====================================================
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// Scrambler tasks (used when descram_en=1)
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// ====================================================
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// Original scrambler (all lanes scrambled)
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task scramble_block;
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input [127:0] original;
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output [127:0] scrambled;
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integer i;
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reg [31:0] lane_word;
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begin
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scrambled = 128'h0;
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for (i = 0; i < 4; i = i + 1) begin
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lane_word = original[32*i +: 32];
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scrambled[32*i +: 32] = lane_word ^ lfsr_lane[i];
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// Update LFSR: feedback = lfsr[31]^lfsr[30]^lfsr[29]^lfsr[28]
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lfsr_lane[i] = {lfsr_lane[i][30:0],
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lfsr_lane[i][31] ^ lfsr_lane[i][30] ^
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lfsr_lane[i][29] ^ lfsr_lane[i][28]};
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end
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end
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endtask
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// New scrambler with per-lane mask (1=scramble that lane)
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task scramble_block_masked;
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input [127:0] original;
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input [3:0] mask; // 1=scramble this lane
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output [127:0] scrambled;
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integer i;
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reg [31:0] lane_word;
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begin
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scrambled = 128'h0;
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for (i = 0; i < 4; i = i + 1) begin
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lane_word = original[32*i +: 32];
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if (mask[i]) begin
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scrambled[32*i +: 32] = lane_word ^ lfsr_lane[i];
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// Update LFSR only for scrambled lanes
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lfsr_lane[i] = {lfsr_lane[i][30:0],
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lfsr_lane[i][31] ^ lfsr_lane[i][30] ^
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lfsr_lane[i][29] ^ lfsr_lane[i][28]};
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end else begin
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scrambled[32*i +: 32] = lane_word;
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// No LFSR update for unscrambled lanes
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end
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end
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end
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endtask
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// ====================================================
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// CRC32 Computation Functions
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// ====================================================
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function automatic [31:0] crc32_next;
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input [31:0] crc;
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input [31:0] data;
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reg [31:0] new_crc;
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reg b;
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integer i;
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begin
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new_crc = crc;
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for (i = 0; i < 32; i = i + 1) begin
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b = new_crc[31] ^ data[31-i];
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new_crc = {new_crc[30:0], 1'b0};
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if (b) new_crc = new_crc ^ 32'h04C11DB7;
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end
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crc32_next = new_crc;
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end
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endfunction
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function automatic [31:0] crc32_compute;
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input [31:0] words[0:255];
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input integer num;
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reg [31:0] crc;
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integer i;
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begin
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crc = 32'hFFFFFFFF;
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for (i = 0; i < num; i = i + 1) begin
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crc = crc32_next(crc, words[i]);
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end
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crc32_compute = crc;
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end
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endfunction
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// ====================================================
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// Test Variables (module level)
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// ====================================================
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integer data_words;
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reg [31:0] frame_words[0:255];
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integer frame_len;
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integer i;
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// ====================================================
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// Test Sequence
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// ====================================================
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initial begin
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// Initialize
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serial_in = 4'h0;
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patn_count = PATN_COUNT;
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tap_step = TAP_STEP;
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descram_en = 0; // default disabled
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force_train = 0;
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$display("========================================");
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$display("Testbench started at %0t", $time);
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$display("========================================");
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reset();
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wait(prefill_start == 1);
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repeat(10) @(posedge clk);
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prefilling = 1;
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repeat(100) @(posedge clk);
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prefilling = 0;
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// -------------------------------------------------
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// Phase 1: Link Training (successful)
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// -------------------------------------------------
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$display("Phase 1: Training with correct patterns...");
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send_blocks({4{TRAINING_PATN}}, PATN_COUNT - 0);
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send_blocks({4{TRAINING_EXIT}}, 1);
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wait(dut.u_train.train_ready == 1);
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$display("Link ready at %0t", $time);
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// -------------------------------------------------
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// Phase 2: Send a correct frame
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// -------------------------------------------------
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$display("Phase 2: Sending a correct frame...");
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data_words = 20;
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frame_len = 2 + data_words + 1;
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frame_words[0] = FRAME_HEADER;
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frame_words[1] = (32'h1235 << 16) | data_words;
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for (i = 0; i < data_words; i = i + 1) begin
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frame_words[2+i] = 32'hA0000000 + i;
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end
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// Compute CRC over addr_len and data (1 + data_words words)
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begin
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reg [31:0] crc_tmp[0:255];
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integer k;
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for (k = 0; k < 1 + data_words; k = k + 1) begin
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crc_tmp[k] = frame_words[1 + k];
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end
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frame_words[2 + data_words] = crc32_compute(crc_tmp, 1 + data_words);
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end
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send_words(frame_len, frame_words);
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fork
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begin
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@(posedge wr_en);
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$display("Write detected: addr=%0d data=%h mask=%h", wr_addr, wr_data, byte_mask);
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if (wr_addr !== 13'h123) $error("Unexpected write address: %0d", wr_addr);
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if (byte_mask[31:0] !== 32'hFFFF_0000) $error("Byte mask mismatch: %h", byte_mask);
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if (byte_mask[63:32] !== 32'hFFFF_FFFF) $error("Byte mask high part not zero: %h", byte_mask[63:32]);
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$display("Correct frame write verified.");
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end
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join_none
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repeat(100) @(posedge clk);
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// -------------------------------------------------
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// Phase 3: Send a frame with bad CRC
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// -------------------------------------------------
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$display("Phase 3: Sending a frame with bad CRC...");
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frame_words[2+data_words] = ~frame_words[2+data_words];
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send_words(frame_len, frame_words);
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@(posedge crc_error);
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$display("CRC error detected at %0t", $time);
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repeat(10) @(posedge clk);
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if (link_down) $display("Link down as expected.");
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else $error("Link not down after CRC error.");
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// -------------------------------------------------
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// Phase 4: Re-train and send another correct frame
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// -------------------------------------------------
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$display("Phase 4: Re-training...");
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send_blocks({4{TRAINING_PATN}}, PATN_COUNT - 0);
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send_blocks({4{TRAINING_EXIT}}, 1);
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wait(dut.u_train.train_ready == 1);
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$display("Link ready again.");
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// Compute CRC over addr_len and data (1 + data_words words)
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begin
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reg [31:0] crc_tmp[0:255];
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integer k;
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for (k = 0; k < 1 + data_words; k = k + 1) begin
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crc_tmp[k] = frame_words[1 + k];
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end
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frame_words[2 + data_words] = crc32_compute(crc_tmp, 1 + data_words);
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end
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send_words(frame_len, frame_words);
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repeat(100) @(posedge clk);
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// -------------------------------------------------
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// Phase 5: Test delay_tap adjustment on match failure
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// -------------------------------------------------
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$display("Phase 5: Testing delay_tap adjustment...");
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force_train = 1;
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repeat(1) @(posedge clk);
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force_train = 0;
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send_blocks(128'h0, 5);
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repeat(200) @(posedge clk);
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$display("Final delay_tap = %0d", delay_tap);
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// -------------------------------------------------
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// Phase 6: Test with scrambler enabled (header not scrambled)
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// -------------------------------------------------
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$display("Phase 6: Testing with descrambler enabled (header not scrambled)...");
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// Reset and train with descram_en=0 (training patterns are not scrambled)
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descram_en = 0;
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force_train = 1;
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repeat(1) @(posedge clk);
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force_train = 0;
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send_blocks({4{TRAINING_PATN}}, PATN_COUNT - 0);
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send_blocks({4{TRAINING_EXIT}}, 1);
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wait(dut.u_train.train_ready == 1);
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$display("Link ready for scrambled data.");
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// Enable descrambler in DUT and initialize LFSRs for transmission
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descram_en = 1;
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for (i = 0; i < 4; i = i + 1) lfsr_lane[i] = SCRAMBLER_SEED;
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// Construct a simple frame (small data length)
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data_words = 10;
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frame_len = 2 + data_words + 1;
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frame_words[0] = FRAME_HEADER;
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frame_words[1] = (32'h1234 << 16) | data_words; // base_addr=0x1234, offset=0, len=10
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for (i = 0; i < data_words; i = i + 1) begin
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frame_words[2+i] = 32'hB0000000 + i; // different pattern from Phase 2
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end
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// Compute CRC over addr_len and data (1 + data_words words)
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begin
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reg [31:0] crc_tmp[0:255];
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integer k;
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for (k = 0; k < 1 + data_words; k = k + 1) begin
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crc_tmp[k] = frame_words[1 + k];
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end
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frame_words[2 + data_words] = crc32_compute(crc_tmp, 1 + data_words);
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end
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// Now scramble each 128-bit block and send
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begin
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integer word_idx;
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integer j;
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integer block_num;
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reg [127:0] orig_block, scrambled_block;
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reg [3:0] block_mask;
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word_idx = 0;
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block_num = 0;
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while (word_idx < frame_len) begin
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orig_block = 128'h0;
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// Fill block with up to 4 words, pad with 0 if needed
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for (j = 0; j < 4; j = j + 1) begin
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if (word_idx < frame_len) begin
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orig_block[32*j +: 32] = frame_words[word_idx];
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word_idx = word_idx + 1;
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end else begin
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orig_block[32*j +: 32] = 32'h0; // pad with 0
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end
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end
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// Determine mask: first block leaves lane0 unscrambled (header), others all scrambled
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block_mask = (block_num == 0) ? 4'b1110 : 4'b1111;
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scramble_block_masked(orig_block, block_mask, scrambled_block);
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send_block(scrambled_block);
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block_num = block_num + 1;
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end
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end
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// Monitor writes
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fork
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begin
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@(posedge wr_en);
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$display("Scrambled test write: addr=%0d data=%h mask=%h", wr_addr, wr_data, byte_mask);
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end
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join_none
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repeat(200) @(posedge clk);
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// Check that no CRC error happened
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if (crc_error) $error("CRC error in scrambled test");
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else $display("Scrambled test passed (no CRC error).");
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// Disable scrambler for rest of test
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descram_en = 0;
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// -------------------------------------------------
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// End of test
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// -------------------------------------------------
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repeat(50) @(posedge clk);
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$display("========================================");
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$display("Testbench finished at %0t", $time);
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$display("========================================");
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$finish;
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end
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// ====================================================
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// Monitor and Assertions
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// ====================================================
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always @(posedge clk) begin
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if (wr_en) $display("WRITE: addr=%0d data=%h mask=%h", wr_addr, wr_data, byte_mask);
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if (crc_error) $display("CRC_ERROR pulse at %0t", $time);
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end
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always @(posedge clk) begin
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if (dut.u_train.train_ready && link_down)
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$error("Inconsistent state: train_ready and link_down both high");
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end
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endmodule
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