72 lines
1.3 KiB
Verilog
72 lines
1.3 KiB
Verilog
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module bhv_spram (
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clka,
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ena,
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dina,
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addra,
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clkb,
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enb,
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doutb,
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addrb
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);
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//=================================================
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function integer clog2(input integer depth);
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begin
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for(clog2=0;depth>0;clog2=clog2+1)
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depth =depth>>1;
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end
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endfunction
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//=================================================
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parameter width = 16;
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parameter depth = 1024;
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localparam aw = clog2(depth-1);
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//=================================================
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input clka ;
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input ena ;
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input [width-1:0] dina ;
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input [aw-1:0] addra ;
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input clkb ;
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input enb ;
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output [width-1:0] doutb ;
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input [aw-1:0] addrb ;
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//================================================
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wire clka;
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wire ena;
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wire [width-1:0] dina;
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wire [aw-1:0] addra;
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wire clkb;
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wire enb;
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reg [width-1:0] doutb;
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wire [aw-1:0] addrb;
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//================================================
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reg [width-1:0] mem[0:depth-1];
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always@(posedge clka)begin
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if(ena)begin
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mem[addra] <=dina;
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end
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end
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always@(posedge clkb)begin
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if(enb)begin
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doutb <=mem[addrb];
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end
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//else begin
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// doutb <=0;
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//end
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end
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endmodule
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