117 lines
2.8 KiB
Verilog
117 lines
2.8 KiB
Verilog
module DA4008_DEM_Parallel_PRBS_1CH ( clk,
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data_in,
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prbs_en,
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set,
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MSB_DUM_IN,
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DEM_LSB_OUT,
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DEM_MSB_OUT,
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DEM_MSB_DUM
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);
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input clk, prbs_en;
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input [7:0] data_in;
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input [14:0] set;
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input MSB_DUM_IN;
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output [4:0] DEM_LSB_OUT;
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output [6:0] DEM_MSB_OUT;
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output DEM_MSB_DUM;
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reg [14:0]r_shift_data;
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always @(posedge clk or negedge prbs_en)
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begin
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if(!prbs_en)
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r_shift_data <=set;
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else
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begin
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r_shift_data[0] <=r_shift_data[3];
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r_shift_data[1] <= r_shift_data[4];
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r_shift_data[2] <= r_shift_data[5];
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r_shift_data[3] <= r_shift_data[6];
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r_shift_data[4] <= r_shift_data[7];
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r_shift_data[5] <= r_shift_data[8];
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r_shift_data[6] <= r_shift_data[9];
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r_shift_data[7] <= r_shift_data[10];
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r_shift_data[8] <= r_shift_data[11];
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r_shift_data[9] <= r_shift_data[12];
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r_shift_data[10] <= r_shift_data[13];
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r_shift_data[11] <= r_shift_data[14];
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r_shift_data[12] <= r_shift_data[0]^r_shift_data[1];
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r_shift_data[13] <= r_shift_data[2]^r_shift_data[1];
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r_shift_data[14] <= r_shift_data[3]^r_shift_data[2];
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end
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end
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wire [2:0]dd;
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assign dd = {r_shift_data[0],r_shift_data[1], r_shift_data[2]};
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reg [6:0] r_MSB_BUF0;
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always @(posedge clk)
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begin
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case(dd[2:0])
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3'd0: r_MSB_BUF0 <= {data_in[7],data_in[7],data_in[7],data_in[7],data_in[6],data_in[6],data_in[5]};
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3'd1: r_MSB_BUF0 <= {data_in[7],data_in[7],data_in[7],data_in[6],data_in[6],data_in[5],data_in[7]};
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3'd2: r_MSB_BUF0 <= {data_in[7],data_in[7],data_in[6],data_in[6],data_in[5],data_in[7],data_in[7]};
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3'd3: r_MSB_BUF0 <= {data_in[7],data_in[6],data_in[6],data_in[5],data_in[7],data_in[7],data_in[7]};
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3'd4: r_MSB_BUF0 <= {data_in[6],data_in[6],data_in[5],data_in[7],data_in[7],data_in[7],data_in[7]};
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3'd5: r_MSB_BUF0 <= {data_in[6],data_in[5],data_in[7],data_in[7],data_in[7],data_in[7],data_in[6]};
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3'd6: r_MSB_BUF0 <= {data_in[5],data_in[7],data_in[7],data_in[7],data_in[7],data_in[6],data_in[6]};
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3'd7: r_MSB_BUF0 <= {data_in[7],data_in[7],data_in[7],data_in[7],data_in[6],data_in[6],data_in[5]};
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endcase
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end
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reg [4:0] r_LSB_BUF0;
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reg r_DUM_BUF;
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always @(posedge clk)
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begin
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r_LSB_BUF0 <= {data_in[4],data_in[3],data_in[2],data_in[1],data_in[0]};
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r_DUM_BUF <= MSB_DUM_IN;
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end
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assign DEM_LSB_OUT = r_LSB_BUF0;
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assign DEM_MSB_DUM = r_DUM_BUF;
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assign DEM_MSB_OUT = r_MSB_BUF0;
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endmodule
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