16 lines
373 B
Verilog
16 lines
373 B
Verilog
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//`undef BEHAVIOR_SIM
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//`undef XILINX_FPGA
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`undef TSMC_IC
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//Is the chip a 4-channel one?
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//`undef CHANNEL_IS_FOUR
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//Setting the Number of SPI Slave Devices
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`undef SLVNUM
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//Whether SPI Bus Commands Are Buffered
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`undef SPIBUS_CMD_REG
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//Whether SPI Bus Readout Are Buffered
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`undef SPIBUS_OUT_REG
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//Whether Mod mux dout Are Buffered
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//`undef MODDOUT_MUX_REG
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