84 lines
2.7 KiB
Verilog
84 lines
2.7 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : dacif.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.4 2024-03-12 PWY
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// 0.9 2024-06-19 PWY Add 2x, 4x, and 8x interpolation modes to EZQ2.0S.
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module dacif (
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input clk
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,input rstn
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,input din_vld
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,output dout_vld
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//mixer data input
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,input [7:0] din [63:0]
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//data output
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,output [7:0] dout[63:0]
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);
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wire[1 :0] dacif_vld_dly;
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sirv_gnrl_dffr #(2) dacif_vld_dffr ({dacif_vld_dly[0], din_vld}, dacif_vld_dly, clk, rstn);
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////////////////////////////////////////////////////
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// regs
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////////////////////////////////////////////////////
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wire[7:0] mux_p [63:0];
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wire[7:0] dout_w [63:0];
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genvar k;
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generate
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for(k = 0; k < 64; k = k + 1) begin
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sirv_gnrl_dfflr #(8) mux_dfflr (1'b1, {~din[k][7], din[k][6:0]}, mux_p[k], clk, rstn);
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end
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endgenerate
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genvar m;
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generate
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////////////////////////////////////////////////////
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// mode select
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////////////////////////////////////////////////////
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for(m = 0; m < 64; m = m + 1) begin
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assign dout_w[m] = mux_p [m] ;
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sirv_gnrl_dfflrd #(8) dout_dfflrd (8'h80, 1'b1, dout_w[m], dout[m], clk, rstn);
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end
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endgenerate
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assign dout_vld = dacif_vld_dly[1];
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endmodule
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