600 lines
29 KiB
Verilog
600 lines
29 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/02/28 19:57:30
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// Design Name:
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// Module Name: dac_regfile
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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// Revision Date: 2026/02/28 19:57:30
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// -----------------------------------------------------------
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// -- Register address offset macros
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// -----------------------------------------------------------
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//Prbs_en Ctrl Register
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`define CCALRSTNR 8'h00
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`define CCLKDCCENR 8'h04
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`define CASCLKCTR 8'h08
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`define CCALDCCQECPIR 8'h0C
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`define CCALQECCTR1 8'h10
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`define CCALDCCCTR1 8'h14
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`define CCALPICTR 8'h18
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`define CCALCROSSCTR 8'h1C
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`define CCALRSVR0 8'h20
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`define CCALRSVR1 8'h24
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`define SELCK10GDR 8'h28
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`define SELCK2P5GDR 8'h2C
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`define SELCK625MDR 8'h30
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`define P2SDATAENR 8'h34
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`define ENALLPR 8'h38
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`define ENPIPR 8'h3C
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`define CLKDIVRSTNR 8'h40
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`define P2SRSVR0 8'h44
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`define P2SRSVR1 8'h48
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`define CKRXSWR 8'h4C
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`define RSTCKR 8'h50
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`define CTRLZINR 8'h54
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module clk_regfile (
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//system port
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input clk // System Main Clock
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,input rstn // Spi Reset active low
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//rw op port
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,input [31 :0] wrdata // write data
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,input wren // write enable
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,input [7 :0] rwaddr // read & write address
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,input rden // read enable
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,output [31 :0] rddata // read data
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,output [0 :0] CcalRstn
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,output [3 :0] EnAllP
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,output [0 :0] DccEn
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,output [0 :0] CasGateCkCtrl
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,output [0 :0] SpiEnPi
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,output [0 :0] SpiEnQec
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,output [0 :0] SpiEnDcc
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,output [4 :0] SpiQecCtrlIp
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,output [4 :0] SpiQecCtrlIn
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,output [4 :0] SpiQecCtrlQp
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,output [4 :0] SpiQecCtrlQn
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,output [5 :0] SpiDccCtrlIup
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,output [5 :0] SpiDccCtrlIdn
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,output [5 :0] SpiDccCtrlQup
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,output [5 :0] SpiDccCtrlQdn
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,output [7 :0] SpiSiqNOut
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,output [7 :0] SpiSiqPOut
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,output [3 :0] SpiSiPOut
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,output [3 :0] SpiSqPOut
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,output [2 :0] CrtlCrossOverN
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,output [2 :0] CrtlCrossOverP
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,output [31 :0] CcalRsv0
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,output [31 :0] CcalRsv1
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,output [3 :0] SelCk10GDig
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,output [3 :0] SelCk2p5GDig
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,output [8 :0] SelCk625MDig
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,output [15 :0] P2sDataEn
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,output [15 :0] P2sEnAllP
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,output [15 :0] EnPiP
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,output [15 :0] CkDivRstn
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,output [31 :0] p2srsv0
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,output [31 :0] p2srsv1
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,output [15 :0] CkRxSw
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,output [15 :0] RstnCk
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,output [15 :0] CtrlZin
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);
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localparam L = 1'b0,
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H = 1'b1;
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// ------------------------------------------------------
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// -- Register Default Vaule
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// ------------------------------------------------------
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wire [0 :0] ccalrstnrdft = 1'b0 ; // CCALRSTNR 16'h0000
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wire [4 :0] cclkdccenrdft = 5'b0 ; // CCLKDCCENR 16'h0004
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wire [0 :0] casclkctrdft = 1'b1 ; // CASCLKCTR 16'h0008
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wire [2 :0] ccaldccqecpirdft = 3'b0 ; // CCALDCCQECPIR 16'h000C
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wire [19:0] ccalqecctr1dft = {5'b10001,5'b10001,5'b10000,5'b10000} ; // CCALQECCTR1 16'h0010
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wire [23:0] ccaldccctr1dft = {6'b111111,6'b000000,6'b111111,6'b000000} ; // CCALDCCCTR1 16'h0014
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wire [23:0] ccalpictrdft = {8'b11111111,8'b00000000,4'b0011,4'b0000} ; // CCALPICTR 16'h0018
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wire [5 :0] ccalcrossctrdft = {3'b100,3'b110} ; // CCALCROSSCTR 16'h001C
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wire [31:0] ccalrsvr0dft = 32'h0 ; // CCALRSVR0 16'h0020
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wire [31:0] ccalrsvr1dft = 32'h0 ; // CCALRSVR1 16'h0024
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wire [3 :0] selck10gdrdft = 4'b0001 ; // SELCK10GDR 16'h0028
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wire [3 :0] selck2p5gdrdft = 4'b0010 ; // SELCK2P5GDR 16'h002C
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wire [8 :0] selck625mdrdft = 9'b100001010 ; // SELCK625MDR 16'h0030
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wire [15:0] p2sdataenrdft = 16'h1 ; // P2SDATAENR 16'h0034
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wire [15:0] enallprdft = 16'h1 ; // ENALLPR 16'h0038
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wire [15:0] enpiprdft = 16'h1 ; // ENPIPR 16'h003C
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wire [15:0] clkdivrstnrdft = 16'h1 ; // CLKDIVRSTNR 16'h0040
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wire [31:0] p2srsvr0dft = 32'h0 ; // P2SRSVR0 16'h0044
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wire [31:0] p2srsvr1dft = 32'h0 ; // P2SRSVR1 16'h0048
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wire [15:0] ckrxswrdft = 16'h1 ; // CKRXSWR 16'h004C
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wire [15:0] rstckrdft = 16'h1 ; // RSTCKR 16'h0050
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wire [15:0] ctrzinrdft = 16'h1 ; // CTRLZINR 16'h0054
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// ------------------------------------------------------
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// -- Register enable (select) wires
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// ------------------------------------------------------
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wire ccalrstnren ; // CCALRSTNR Enable
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wire cclkdccenren ; // CCLKDCCEN Enable
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wire casclkctren ; // CASCLKCTR Enable
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wire ccaldccqecpiren ; // CCALDCCQECPIR Enable
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wire ccalqecctr1en ; // CCALQECCTR1 Enable
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wire ccaldccctr1en ; // CCALDCCCTR1 Enable
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wire ccalpictren ; // CCALPICTR Enable
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wire ccalcrossctren ; // CCALCROSSCTR Enable
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wire ccalrsvr0en ; // CCALRSVR0 Enable
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wire ccalrsvr1en ; // CCALRSVR1 Enable
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wire selck10gdren ; // SELCK10GDR Enable
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wire selck2p5gdren ; // SELCK2P5GDR Enable
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wire selck625mdren ; // SELCK625MDR Enable
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wire p2sdataenren ; // P2SDATAENR Enable
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wire enallpren ; // ENALLPR Enable
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wire enpipren ; // ENPIPR Enable
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wire clkdivrstnren ; // CLKDIVRSTNR Enable
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wire p2srsvr0en ; // P2SRSVR0 Enable
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wire p2srsvr1en ; // P2SRSVR1 Enable
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wire ckrxswren ; // CKRXSWR Enable
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wire rstckren ; // RSTCKR Enable
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wire ctrzinren ; // CTRLZINR Enable
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// ------------------------------------------------------
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// -- Register write enable wires
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// ------------------------------------------------------
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wire ccalrstnrwe ; // CCALRSTNR Write Enable
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wire cclkdccenrwe ; // CCLKDCCEN Write Enable
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wire casclkctrwe ; // CASCLKCTR Write Enable
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wire ccaldccqecpirwe ; // CCALDCCQECPIR Write Enable
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wire ccalqecctr1we ; // CCALQECCTR1 Write Enable
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wire ccaldccctr1we ; // CCALDCCCTR1 Write Enable
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wire ccalpictrwe ; // CCALPICTR Write Enable
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wire ccalcrossctrwe ; // CCALCROSSCTR Write Enable
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wire ccalrsvr0we ; // CCALRSVR0 Write Enable
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wire ccalrsvr1we ; // CCALRSVR1 Write Enable
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wire selck10gdrwe ; // SELCK10GDR Write Enable
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wire selck2p5gdrwe ; // SELCK2P5GDR Write Enable
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wire selck625mdrwe ; // SELCK625MDR Write Enable
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wire p2sdataenrwe ; // P2SDATAENR Write Enable
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wire enallprwe ; // ENALLPR Write Enable
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wire enpiprwe ; // ENPIPR Write Enable
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wire clkdivrstnrwe ; // CLKDIVRSTNR Write Enable
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wire p2srsvr0we ; // P2SRSVR0 Write Enable
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wire p2srsvr1we ; // P2SRSVR1 Write Enable
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wire ckrxswrwe ; // CKRXSWR Write Enable
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wire rstckrwe ; // RSTCKR Write Enable
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wire ctrzinrwe ; // CTRLZINR Write Enable
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// ------------------------------------------------------
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// -- Misc Registers
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// ------------------------------------------------------
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wire [0 :0] ccalrstnr ; // CCALRSTNR Register, Default vaule is 1'b0
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wire [4 :0] cclkdccenr ; // CCLKDCCEN Register, Default vaule is 5'b0
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wire [0 :0] casclkctr ; // CASCLKCTR Register, Default vaule is 1'b1
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wire [2 :0] ccaldccqecpir ; // CCALDCCQECPIR Register, Default vaule is 3'b0
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wire [19:0] ccalqecctr1 ; // CCALQECCTR1 Register, Default vaule is {5'b10001,5'b10001,5'b10000,5'b10000}
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wire [23:0] ccaldccctr1 ; // CCALDCCCTR1 Register, Default vaule is {6'b111111,6'b000000,6'b111111,6'b000000}
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wire [23:0] ccalpictr ; // CCALPICTR Register, Default vaule is {8'b11111111,8'b00000000,4'b0011,4'b0011}
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wire [5 :0] ccalcrossctr ; // CCALCROSSCTR Register, Default vaule is {3'b100,3'b110}
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wire [31:0] ccalrsvr0 ; // CCALRSVR0 Register, Default vaule is 32'h0
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wire [31:0] ccalrsvr1 ; // CCALRSVR1 Register, Default vaule is 32'h0
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wire [3 :0] selck10gdr ; // SELCK10GDR Register, Default vaule is 4'b0001
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wire [3 :0] selck2p5gdr ; // SELCK2P5GDR Register, Default vaule is 4'b0010
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wire [8 :0] selck625mdr ; // SELCK625MDR Register, Default vaule is 9'b100001010
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wire [15:0] p2sdataenr ; // P2SDATAENR Register, Default vaule is 16'h1
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wire [15:0] enallpr ; // ENALLPR Register, Default vaule is 16'h1
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wire [15:0] enpipr ; // ENPIPR Register, Default vaule is 16'h1
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wire [15:0] clkdivrstnr ; // CLKDIVRSTNR Register, Default vaule is 16'h1
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wire [31:0] p2srsvr0 ; // P2SRSVR0 Register, Default vaule is 32'h0
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wire [31:0] p2srsvr1 ; // P2SRSVR1 Register, Default vaule is 32'h0
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wire [15:0] ckrxswr ; // CKRXSWR Register, Default vaule is 16'h1
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wire [15:0] rstckr ; // RSTCKR Register, Default vaule is 16'h1
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wire [15:0] ctrzinr ; // CTRLZINR Register, Default vaule is 16'h1
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reg [31 :0] rddata_reg ;
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// ------------------------------------------------------
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// -- Address decoder
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//
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// Decodes the register address offset input(reg_addr)
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// to produce enable (select) signals for each of the
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// SW-registers in the macrocell. The reg_addr input
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// is bits [15:0] of the paddr bus.
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// ------------------------------------------------------
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assign ccalrstnren = (rwaddr[7:2] == `CCALRSTNR >>2) ? 1'b1 : 1'b0; // CCALRSTNR Enable
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assign cclkdccenren = (rwaddr[7:2] == `CCLKDCCENR >>2) ? 1'b1 : 1'b0; // CCLKDCCEN Enable
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assign casclkctren = (rwaddr[7:2] == `CASCLKCTR >>2) ? 1'b1 : 1'b0; // CASCLKCTR Enable
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assign ccaldccqecpiren = (rwaddr[7:2] == `CCALDCCQECPIR >>2) ? 1'b1 : 1'b0; // CCALDCCQECPIR Enable
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assign ccalqecctr1en = (rwaddr[7:2] == `CCALQECCTR1 >>2) ? 1'b1 : 1'b0; // CCALQECCTR1 Enable
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assign ccaldccctr1en = (rwaddr[7:2] == `CCALDCCCTR1 >>2) ? 1'b1 : 1'b0; // CCALDCCCTR1 Enable
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assign ccalpictren = (rwaddr[7:2] == `CCALPICTR >>2) ? 1'b1 : 1'b0; // CCALPICTR Enable
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assign ccalcrossctren = (rwaddr[7:2] == `CCALCROSSCTR >>2) ? 1'b1 : 1'b0; // CCALCROSSCTR Enable
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assign ccalrsvr0en = (rwaddr[7:2] == `CCALRSVR0 >>2) ? 1'b1 : 1'b0; // CCALRSVR0 Enable
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assign ccalrsvr1en = (rwaddr[7:2] == `CCALRSVR1 >>2) ? 1'b1 : 1'b0; // CCALRSVR1 Enable
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assign selck10gdren = (rwaddr[7:2] == `SELCK10GDR >>2) ? 1'b1 : 1'b0; // SELCK10GDR Enable
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assign selck2p5gdren = (rwaddr[7:2] == `SELCK2P5GDR >>2) ? 1'b1 : 1'b0; // SELCK2P5GDR Enable
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assign selck625mdren = (rwaddr[7:2] == `SELCK625MDR >>2) ? 1'b1 : 1'b0; // SELCK625MDR Enable
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assign p2sdataenren = (rwaddr[7:2] == `P2SDATAENR >>2) ? 1'b1 : 1'b0; // P2SDATAENR Enable
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assign enallpren = (rwaddr[7:2] == `ENALLPR >>2) ? 1'b1 : 1'b0; // ENALLPR Enable
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assign enpipren = (rwaddr[7:2] == `ENPIPR >>2) ? 1'b1 : 1'b0; // ENPIPR Enable
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assign clkdivrstnren = (rwaddr[7:2] == `CLKDIVRSTNR >>2) ? 1'b1 : 1'b0; // CLKDIVRSTNR Enable
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assign p2srsvr0en = (rwaddr[7:2] == `P2SRSVR0 >>2) ? 1'b1 : 1'b0; // P2SRSVR0 Enable
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assign p2srsvr1en = (rwaddr[7:2] == `P2SRSVR1 >>2) ? 1'b1 : 1'b0; // P2SRSVR1 Enable
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assign ckrxswren = (rwaddr[7:2] == `CKRXSWR >>2) ? 1'b1 : 1'b0; // CKRXSWR Enable
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assign rstckren = (rwaddr[7:2] == `RSTCKR >>2) ? 1'b1 : 1'b0; // RSTCKR Enable
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assign ctrzinren = (rwaddr[7:2] == `CTRLZINR >>2) ? 1'b1 : 1'b0; // CTRLZINR Enable
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// ------------------------------------------------------
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// -- Write enable signals
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//
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// Write enable signals for writable SW-registers.
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// The write enable for each register is the ANDed
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// result of the register enable and the input reg_wren
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// ------------------------------------------------------
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assign ccalrstnrwe = ccalrstnren & wren; // CCALRSTNR Write Enable
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assign cclkdccenrwe = cclkdccenren & wren; // CCLKDCCEN Write Enable
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assign casclkctrwe = casclkctren & wren; // CASCLKCTR Write Enable
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assign ccaldccqecpirwe = ccaldccqecpiren & wren; // CCALDCCQECPIR Write Enable
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assign ccalqecctr1we = ccalqecctr1en & wren; // CCALQECCTR1 Write Enable
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assign ccaldccctr1we = ccaldccctr1en & wren; // CCALDCCCTR1 Write Enable
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assign ccalpictrwe = ccalpictren & wren; // CCALPICTR Write Enable
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assign ccalcrossctrwe = ccalcrossctren & wren; // CCALCROSSCTR Write Enable
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assign ccalrsvr0we = ccalrsvr0en & wren; // CCALRSVR0 Write Enable
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assign ccalrsvr1we = ccalrsvr1en & wren; // CCALRSVR1 Write Enable
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assign selck10gdrwe = selck10gdren & wren; // SELCK10GDR Write Enable
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assign selck2p5gdrwe = selck2p5gdren & wren; // SELCK2P5GDR Write Enable
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assign selck625mdrwe = selck625mdren & wren; // SELCK625MDR Write Enable
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assign p2sdataenrwe = p2sdataenren & wren; // P2SDATAENR Write Enable
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assign enallprwe = enallpren & wren; // ENALLPR Write Enable
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assign enpiprwe = enpipren & wren; // ENPIPR Write Enable
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assign clkdivrstnrwe = clkdivrstnren & wren; // CLKDIVRSTNR Write Enable
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assign p2srsvr0we = p2srsvr0en & wren; // P2SRSVR0 Write Enable
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assign p2srsvr1we = p2srsvr1en & wren; // P2SRSVR1 Write Enable
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assign ckrxswrwe = ckrxswren & wren; // CKRXSWR Write Enable
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assign rstckrwe = rstckren & wren; // RSTCKR Write Enable
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assign ctrzinrwe = ctrzinren & wren; // CTRLZINR Write Enable
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// ------------------------------------------------------
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// -- ccalrstnr Register
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//
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// Write ccalrstnr for 'CCALRSTNR' : 1-bit register
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// Register is split into the following bit fields
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//
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// [0:0] --> ccalrstnr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(1) ccalrstnr_dfflrd (ccalrstnrdft, ccalrstnrwe, wrdata[0], ccalrstnr, clk, rstn);
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// ------------------------------------------------------
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// -- cclkdccenr Register
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//
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// Write cclkdccenr for 'CCLKDCCEN' : 5-bit register
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// Register is split into the following bit fields
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//
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// [4:0] --> cclkdccenr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(5) cclkdccenr_dfflrd (cclkdccenrdft, cclkdccenrwe, wrdata[4:0], cclkdccenr, clk, rstn);
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// ------------------------------------------------------
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// -- casclkctr Register
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//
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// Write casclkctr for 'CASCLKCTR' : 1-bit register
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// Register is split into the following bit fields
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//
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// [0:0] --> casclkctr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(1) casclkctr_dfflrd (casclkctrdft, casclkctrwe, wrdata[0], casclkctr, clk, rstn);
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// ------------------------------------------------------
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// -- ccaldccqecpir Register
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//
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// Write ccaldccqecpir for 'CCALDCCQECPIR' : 3-bit register
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// Register is split into the following bit fields
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//
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// [2:0] --> ccaldccqecpir
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(3) ccaldccqecpir_dfflrd (ccaldccqecpirdft, ccaldccqecpirwe, wrdata[2:0], ccaldccqecpir, clk, rstn);
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// ------------------------------------------------------
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// -- ccalqecctr1 Register
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//
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// Write ccalqecctr1 for 'CCALQECCTR1' : 20-bit register
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// Register is split into the following bit fields
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//
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// [19:0] --> ccalqecctr1
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(20) ccalqecctr1_dfflrd (ccalqecctr1dft, ccalqecctr1we, wrdata[19:0], ccalqecctr1, clk, rstn);
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// ------------------------------------------------------
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// -- ccaldccctr1 Register
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//
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// Write ccaldccctr1 for 'CCALDCCCTR1' : 24-bit register
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// Register is split into the following bit fields
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//
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// [23:0] --> ccaldccctr1
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(24) biasct3r_dfflrd (ccaldccctr1dft, ccaldccctr1we, wrdata[23:0], ccaldccctr1, clk, rstn);
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// ------------------------------------------------------
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// -- ccalpictr Register
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//
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// Write ccalpictr for 'CCALPICTR' : 24-bit register
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// Register is split into the following bit fields
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//
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// [23:0] --> ccalpictr
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|
// ------------------------------------------------------
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sirv_gnrl_dfflrd #(24) ccalpictr_dfflrd (ccalpictrdft, ccalpictrwe, wrdata[23:0], ccalpictr, clk, rstn);
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// ------------------------------------------------------
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// -- ccalcrossctr Register
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//
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// Write ccalcrossctr for 'CCALCROSSCTR' : 6-bit register
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// Register is split into the following bit fields
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//
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// [5:0] --> ccalcrossctr
|
|
// ------------------------------------------------------
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|
sirv_gnrl_dfflrd #(6) ccalcrossctr_dfflrd (ccalcrossctrdft, ccalcrossctrwe, wrdata[5:0], ccalcrossctr, clk, rstn);
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// ------------------------------------------------------
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// -- ccalrsvr0 Register
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//
|
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// Write ccalrsvr0 for 'CCALRSVR0' : 32-bit register
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// Register is split into the following bit fields
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//
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// [31:0] --> ccalrsvr0
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(32) ccalrsvr0_dfflrd (ccalrsvr0dft, ccalrsvr0we, wrdata[31:0], ccalrsvr0, clk, rstn);
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// ------------------------------------------------------
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// -- ccalrsvr1 Register
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//
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// Write ccalrsvr1 for 'CCALRSVR1' : 32-bit register
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// Register is split into the following bit fields
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//
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// [31:0] --> ccalrsvr1
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(32) ccalrsvr1_dfflrd (ccalrsvr1dft, ccalrsvr1we, wrdata[31:0], ccalrsvr1, clk, rstn);
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// ------------------------------------------------------
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// -- selck10gdr Register
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//
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// Write selck10gdr for 'SELCK10GDR' : 4-bit register
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// Register is split into the following bit fields
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//
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// [3:0] --> selck10gdr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(4) selck10gdr_dfflrd (selck10gdrdft, selck10gdrwe, wrdata[3:0], selck10gdr, clk, rstn);
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// ------------------------------------------------------
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// -- selck2p5gdr Register
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//
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// Write selck2p5gdr for 'SELCK2P5GDR' : 4-bit register
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// Register is split into the following bit fields
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//
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// [3:0] --> selck2p5gdr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(4) selck2p5gdr_dfflrd (selck2p5gdrdft, selck2p5gdrwe, wrdata[3:0], selck2p5gdr, clk, rstn);
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// ------------------------------------------------------
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// -- selck625mdr Register
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//
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// Write selck625mdr for 'SELCK625MDR' : 9-bit register
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// Register is split into the following bit fields
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//
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// [8:0] --> selck625mdr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(9) selck625mdr_dfflrd (selck625mdrdft, selck625mdrwe, wrdata[8:0], selck625mdr, clk, rstn);
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// ------------------------------------------------------
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// -- p2sdataenr Register
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//
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// Write p2sdataenr for 'P2SDATAENR' : 16-bit register
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// Register is split into the following bit fields
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//
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// [15:0] --> p2sdataenr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(16) p2sdataenr_dfflrd (p2sdataenrdft, p2sdataenrwe, wrdata[15:0], p2sdataenr, clk, rstn);
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// ------------------------------------------------------
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// -- enallpr Register
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//
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// Write enallpr for 'ENALLPR' : 16-bit register
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// Register is split into the following bit fields
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//
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// [15:0] --> enallpr
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(16) enallpr_dfflrd (enallprdft, enallprwe, wrdata[15:0], enallpr, clk, rstn);
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|
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// ------------------------------------------------------
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// -- enpipr Register
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//
|
|
// Write enpipr for 'ENPIPR' : 16-bit register
|
|
// Register is split into the following bit fields
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//
|
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// [15:0] --> enpipr
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|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(16) enpipr_dfflrd (enpiprdft, enpiprwe, wrdata[15:0], enpipr, clk, rstn);
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|
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// ------------------------------------------------------
|
|
// -- clkdivrstnr Register
|
|
//
|
|
// Write clkdivrstnr for 'CLKDIVRSTNR' : 16-bit register
|
|
// Register is split into the following bit fields
|
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//
|
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// [15:0] --> clkdivrstnr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(16) clkdivrstnr_dfflrd (clkdivrstnrdft, clkdivrstnrwe, wrdata[15:0], clkdivrstnr, clk, rstn);
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|
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// ------------------------------------------------------
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// -- p2srsvr0 Register
|
|
//
|
|
// Write p2srsvr0 for 'P2SRSVR0' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [31:0] --> p2srsvr0
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(32) p2srsvr0_dfflrd (p2srsvr0dft, p2srsvr0we, wrdata[31:0], p2srsvr0, clk, rstn);
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|
|
// ------------------------------------------------------
|
|
// -- p2srsvr1 Register
|
|
//
|
|
// Write p2srsvr1 for 'P2SRSVR1' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [31:0] --> p2srsvr1
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(32) p2srsvr1_dfflrd (p2srsvr1dft, p2srsvr1we, wrdata[31:0], p2srsvr1, clk, rstn);
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|
|
|
|
|
// ------------------------------------------------------
|
|
// -- ckrxswr Register
|
|
//
|
|
// Write ckrxswr for 'CKRXSWR' : 16-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [15:0] --> ckrxswr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(16) ckrxswr_dfflrd (ckrxswrdft, ckrxswrwe, wrdata[15:0], ckrxswr, clk, rstn);
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|
|
|
|
|
// ------------------------------------------------------
|
|
// -- rstckr Register
|
|
//
|
|
// Write rstckr for 'RSTCKR' : 16-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [15:0] --> rstckr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(16) rstckr_dfflrd (rstckrdft, rstckrwe, wrdata[15:0], rstckr, clk, rstn);
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|
|
|
// ------------------------------------------------------
|
|
// -- ctrzinr Register
|
|
//
|
|
// Write ctrzinr for 'CTRLZINR' : 16-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [15:0] --> ctrzinr
|
|
// ------------------------------------------------------
|
|
sirv_gnrl_dfflrd #(16) ctrzinr_dfflrd (ctrzinrdft, ctrzinrwe, wrdata[15:0], ctrzinr, clk, rstn);
|
|
|
|
// ------------------------------------------------------
|
|
// -- Read data mux
|
|
//
|
|
// -- The data from the selected register is
|
|
// -- placed on a zero-padded 32-bit read data bus.
|
|
// ------------------------------------------------------
|
|
always @(*) begin : RDDATA_PROC
|
|
rddata_reg = {32{1'b0}};
|
|
if(ccalrstnren == H ) rddata_reg[0 :0] = ccalrstnr[0 :0] ;
|
|
if(cclkdccenren == H ) rddata_reg[4 :0] = cclkdccenr[4 :0] ;
|
|
if(casclkctren == H ) rddata_reg[0 :0] = casclkctr[0 :0] ;
|
|
if(ccaldccqecpiren == H ) rddata_reg[2 :0] = ccaldccqecpir[2 :0] ;
|
|
if(ccalqecctr1en == H ) rddata_reg[19:0] = ccalqecctr1[19:0] ;
|
|
if(ccaldccctr1en == H ) rddata_reg[23:0] = ccaldccctr1[23:0] ;
|
|
if(ccalpictren == H ) rddata_reg[23:0] = ccalpictr[23:0] ;
|
|
if(ccalcrossctren == H ) rddata_reg[5 :0] = ccalcrossctr[5 :0] ;
|
|
if(ccalrsvr0en == H ) rddata_reg[31:0] = ccalrsvr0[31:0] ;
|
|
if(ccalrsvr1en == H ) rddata_reg[31:0] = ccalrsvr1[31:0] ;
|
|
if(selck10gdren == H ) rddata_reg[3 :0] = selck10gdr[3 :0] ;
|
|
if(selck2p5gdren == H ) rddata_reg[3 :0] = selck2p5gdr[3 :0] ;
|
|
if(selck625mdren == H ) rddata_reg[8 :0] = selck625mdr[8 :0] ;
|
|
if(p2sdataenren == H ) rddata_reg[15:0] = p2sdataenr[15:0] ;
|
|
if(enallpren == H ) rddata_reg[15:0] = enallpr[15:0] ;
|
|
if(enpipren == H ) rddata_reg[15:0] = enpipr[15:0] ;
|
|
if(clkdivrstnren == H ) rddata_reg[15:0] = clkdivrstnr[15:0] ;
|
|
if(p2srsvr0en == H ) rddata_reg[31:0] = p2srsvr0[31:0] ;
|
|
if(p2srsvr1en == H ) rddata_reg[31:0] = p2srsvr1[31:0] ;
|
|
if(ckrxswren == H ) rddata_reg[15:0] = ckrxswr[15:0] ;
|
|
if(rstckren == H ) rddata_reg[15:0] = rstckr[15:0] ;
|
|
if(ctrzinren == H ) rddata_reg[15:0] = ctrzinr[15:0] ;
|
|
end
|
|
|
|
//rddata
|
|
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rstn);
|
|
|
|
// ------------------------------------------------------
|
|
// -- Output signals assignment
|
|
// ------------------------------------------------------
|
|
assign CcalRstn = ccalrstnr ;
|
|
assign EnAllP = cclkdccenr ;
|
|
assign DccEn = casclkctr ;
|
|
assign CasGateCkCtrl = casclkctr ;
|
|
assign SpiEnPi = ccaldccqecpir[2] ;
|
|
assign SpiEnQec = ccaldccqecpir[1] ;
|
|
assign SpiEnDcc = ccaldccqecpir[0] ;
|
|
assign SpiQecCtrlIp = ccalqecctr1[19:15] ;
|
|
assign SpiQecCtrlIn = ccalqecctr1[14:10] ;
|
|
assign SpiQecCtrlQp = ccalqecctr1[9 : 5] ;
|
|
assign SpiQecCtrlQn = ccalqecctr1[4 : 0] ;
|
|
|
|
assign SpiDccCtrlIup = ccaldccctr1[23:18] ;
|
|
assign SpiDccCtrlIdn = ccaldccctr1[17:12] ;
|
|
assign SpiDccCtrlQup = ccaldccctr1[11: 6] ;
|
|
assign SpiDccCtrlQdn = ccaldccctr1[5 : 0] ;
|
|
|
|
assign SpiSiqNOut = ccalpictr[23:16] ;
|
|
assign SpiSiqPOut = ccalpictr[15: 8] ;
|
|
assign SpiSiPOut = ccalpictr[7 : 4] ;
|
|
assign SpiSqPOut = ccalpictr[3 : 0] ;
|
|
|
|
assign CrtlCrossOverN = ccalcrossctr[5:3] ;
|
|
assign CrtlCrossOverP = ccalcrossctr[2:0] ;
|
|
assign CcalRsv0 = ccalrsvr0 ;
|
|
assign CcalRsv1 = ccalrsvr0 ;
|
|
|
|
assign SelCk10GDig = selck10gdr ;
|
|
assign SelCk2p5GDig = selck2p5gdr ;
|
|
assign SelCk625MDig = selck625mdr ;
|
|
assign P2sDataEn = p2sdataenr ;
|
|
assign P2sEnAllP = enallpr ;
|
|
assign EnPiP = enpipr ;
|
|
assign CkDivRstn = clkdivrstnr ;
|
|
assign p2srsv0 = p2srsvr0 ;
|
|
assign p2srsv1 = p2srsvr1 ;
|
|
assign CkRxSw = ckrxswr ;
|
|
assign RstnCk = rstckr ;
|
|
assign CtrlZin = ctrzinr ;
|
|
|
|
endmodule
|
|
|
|
`undef CCALRSTNR
|
|
`undef CCLKDCCENR
|
|
`undef CASCLKCTR
|
|
`undef CCALDCCQECPIR
|
|
`undef CCALQECCTR1
|
|
`undef CCALDCCCTR1
|
|
`undef CCALPICTR
|
|
`undef CCALCROSSCTR
|
|
`undef CCALRSVR0
|
|
`undef CCALRSVR1
|
|
`undef SELCK10GDR
|
|
`undef SELCK2P5GDR
|
|
`undef SELCK625MDR
|
|
`undef P2SDATAENR
|
|
`undef ENALLPR
|
|
`undef ENPIPR
|
|
`undef CLKDIVRSTNR
|
|
`undef P2SRSVR0
|
|
`undef P2SRSVR1
|
|
`undef CKRXSWR
|
|
`undef RSTCKR
|
|
`undef CTRLZINR
|
|
`undef VERSIONR
|
|
|