159 lines
7.7 KiB
Verilog
159 lines
7.7 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : awg_ctrl.v
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// Department :
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// Author : hdzhang
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2026-02-28 hdzhang fifo-cmd controlled waveform output
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module awg_ctrl (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//sync signal
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,input start
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//cmd fifo read signal
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,output cmd_fifo_rd_en
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,input [31 :0] cmd_fifo_data
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,input cmd_fifo_empty
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//wave sram read signals
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,output sram_rd_en
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,output [12 :0] sram_rd_addr
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,input [511:0] sram_rd_data
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//output to dem module
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,output [511:0] wave_data_out
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,output wave_valid_out
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//state submit
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,output [2 :0] status
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,output wave_busy
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);
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localparam IDLE = 3'b0, CMD = 3'd1, WAVE = 3'd2, HOLD = 3'd3;
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wire [2 : 0] state_c;
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wire wave_cnt_add, wave_cnt_end;
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wire [4 : 0] wave_cnt_c;
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wire hold_cnt_add, hold_cnt_end;
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wire [30 : 0] hold_cnt_c;
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//wire cmd_fifo_has_empty = cmd_fifo_empty && cmd_fifo_rd_en;
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// ------------------------------------------------------
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// -- state machine
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// ------------------------------------------------------
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//jump conditions
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wire ilde2cmd = (state_c == IDLE) && start;
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wire cmd2wave = (state_c == CMD ) && ~cmd_fifo_data[31];
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wire cmd2hold = (state_c == CMD ) && cmd_fifo_data[31];
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wire wave2hold = (state_c == WAVE) && wave_cnt_end && cmd_fifo_data[31] && ~cmd_fifo_empty;
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wire wave2idle = (state_c == WAVE) && wave_cnt_end && cmd_fifo_empty;
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wire hold2wave = (state_c == HOLD) && hold_cnt_end && ~cmd_fifo_data[31] && ~cmd_fifo_empty;
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wire hold2idle = (state_c == HOLD) && hold_cnt_end && cmd_fifo_empty;
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//state_n
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wire [2 : 0] state_n = ((state_c == IDLE) && ilde2cmd ) ? CMD :
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((state_c == CMD ) && cmd2wave ) ? WAVE :
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((state_c == CMD ) && cmd2hold ) ? HOLD :
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((state_c == WAVE) && wave2hold ) ? HOLD :
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((state_c == WAVE) && wave2idle ) ? IDLE :
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((state_c == HOLD) && hold2wave ) ? WAVE :
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((state_c == HOLD) && hold2idle ) ? IDLE :
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state_c ;
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//state_c
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sirv_gnrl_dffr #(3) state_c_dffr (state_n, state_c, clk, rst_n);
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// ------------------------------------------------------
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// -- command decode
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// ------------------------------------------------------
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assign cmd_fifo_rd_en = ((state_c == CMD) || wave_cnt_end || hold_cnt_end) && ~cmd_fifo_empty;
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wire [4 : 0] cycle_num;
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wire [12 : 0] base_addr;
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wire [12 : 0] wave_leng;
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wire [30 : 0] hold_leng;
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sirv_gnrl_dfflr #( 5) cycle_num_dfflr (cmd_fifo_rd_en && ~cmd_fifo_data[31], cmd_fifo_data[30:26], cycle_num, clk, rst_n);
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sirv_gnrl_dfflr #(13) base_addr_dfflr (cmd_fifo_rd_en && ~cmd_fifo_data[31], cmd_fifo_data[25:13], base_addr, clk, rst_n);
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sirv_gnrl_dfflr #(13) wave_leng_dfflr (cmd_fifo_rd_en && ~cmd_fifo_data[31], cmd_fifo_data[12: 0], wave_leng, clk, rst_n);
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sirv_gnrl_dfflr #(31) hold_leng_dfflr (cmd_fifo_rd_en && cmd_fifo_data[31], cmd_fifo_data[30: 0], hold_leng, clk, rst_n);
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// ------------------------------------------------------
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// -- wave memory address count
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// ------------------------------------------------------
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wire [12 : 0] addr_cnt_c;
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wire addr_cnt_add = (state_c == WAVE);
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wire addr_cnt_end = addr_cnt_add && (addr_cnt_c == wave_leng - 1);
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wire [12 : 0] addr_cnt_n = addr_cnt_end ? 13'h0 :
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addr_cnt_add ? addr_cnt_c + 1'b1 :
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addr_cnt_c ;
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sirv_gnrl_dffr #(13) addr_cnt_c_dffr (addr_cnt_n, addr_cnt_c, clk, rst_n);
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// ------------------------------------------------------
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// -- wave repeat count
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// ------------------------------------------------------
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assign wave_cnt_add = addr_cnt_end;
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assign wave_cnt_end = wave_cnt_add && (wave_cnt_c == cycle_num - 1) && (cycle_num != 5'd0);
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wire [4 : 0] wave_cnt_n = wave_cnt_end ? 5'h0 :
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wave_cnt_add ? wave_cnt_c + 1'b1 :
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wave_cnt_c ;
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sirv_gnrl_dffr #( 5) wave_cnt_c_dffr (wave_cnt_n, wave_cnt_c, clk, rst_n);
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// ------------------------------------------------------
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// -- hold length count
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// ------------------------------------------------------
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assign hold_cnt_add = (state_c == HOLD);
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assign hold_cnt_end = hold_cnt_add && (hold_cnt_c == hold_leng - 1);
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wire [30 : 0] hold_cnt_n = hold_cnt_end ? 5'h0 :
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hold_cnt_add ? hold_cnt_c + 1'b1 :
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hold_cnt_c ;
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sirv_gnrl_dffr #(31) hold_cnt_c_dffr (hold_cnt_n, hold_cnt_c, clk, rst_n);
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// ------------------------------------------------------
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// -- read wave SRAM
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// ------------------------------------------------------
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sirv_gnrl_dffr #(1) sram_rd_en_dffr ((state_c == WAVE), sram_rd_en, clk, rst_n);
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sirv_gnrl_dffr #(13) sram_rd_addr_dffr (base_addr + addr_cnt_c, sram_rd_addr, clk, rst_n);
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wire last_sram_rd_en, last_wave_data_vld;
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wire [7 : 0] last_rddata;
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sirv_gnrl_dffr #(1) last_sram_rd_en_dffr (wave_cnt_end, last_sram_rd_en, clk, rst_n);
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sirv_gnrl_dffr #(1) last_wave_data_dffr (last_sram_rd_en, last_wave_data_vld, clk, rst_n);
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sirv_gnrl_dfflr #(8) last_rddata_dfflr (last_wave_data_vld, sram_rd_data[511:504], last_rddata, clk, rst_n);
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wire wave_vld, hold_vld_n, hold_vld;
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sirv_gnrl_dffr #(1) wave_vld_dffr (sram_rd_en, wave_vld, clk, rst_n);
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sirv_gnrl_dffr #(1) hold_vld_n_dffr ((state_c == HOLD), hold_vld_n, clk, rst_n);
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sirv_gnrl_dffr #(1) hold_vld_dffr (hold_vld_n, hold_vld, clk, rst_n);
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wire [511: 0] wave_data = wave_vld ? sram_rd_data :
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hold_vld ? {64{last_rddata}} :
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512'd0 ;
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sirv_gnrl_dffr #(1) wave_valid_dffr (wave_vld | hold_vld, wave_valid_out, clk, rst_n);
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sirv_gnrl_dfflr #(512) wave_data_dfflr (wave_vld | hold_vld | wave_valid_out, wave_data, wave_data_out, clk, rst_n);
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//status
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assign status = state_c;
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assign wave_busy = (state_c == WAVE) || (state_c == HOLD);
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endmodule
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