302 lines
12 KiB
Verilog
302 lines
12 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 2004 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: bruce dean June 26th. 2004
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//
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// VERSION: Simulation model
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//
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// DesignWare_version: 0d24140b
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// DesignWare_release: O-2018.06-DWBB_201806.1
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//----------------------------------------------------------------------------
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// ABSTRACT: Generic pulse sychronization block
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//
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//
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//----------------------------------------------------------------------------
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// Parameters: Valid Values
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// ========== ============
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// reg_event [ 0 => event_d will have combination logic
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// but latency will be 1 cycle sooner
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// 1 => event_d will be retimed so there will
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// be no logic between register & port
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// but event is delayed 1 cycle]
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// f_sync_type [ 0 = single clock design, no synchronizing stages implemented,
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// 1 = 2-stage synchronization w/ 1st stage neg-edge & 2nd stage pos-edge capturing,
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// 2 = 2-stage synchronization w/ both stages pos-edge capturing,
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// 3 = 3-stage synchronization w/ all stages pos-edge capturing ]
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// 4 = 4-stage synchronization w/ all stages pos-edge capturing ]
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// tst_mode [ 0 = no hold latch inserted,
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// 1 = insert hold 'latch' using a neg-edge triggered register
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// 2 = insert active-low hold latch ]
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// verif_en [ 0 = no sampling errors inserted,
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// 1 = sampling errors are randomly inserted with 0 or up to 1 destination clock cycle delays
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// 2 = sampling errors are randomly inserted with 0, 0.5, 1, or 1.5 destination clock cycle delays
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// 3 = sampling errors are randomly inserted with 0, 1, 2, or 3 destination clock cycle delays
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// 4 = sampling errors are randomly inserted with 0 or up to 0.5 destination clock cycle delays ]
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// pulse_mode [ 0 => single clock cycle pulse in produces
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// single clock cycle pulse out
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// 1 => rising edge transition in produces
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// 2 => falling edge transition in produces
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// single clock cycle pulse out
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// 3 => toggle transition in produces
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// single clock cycle pulse out]
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///
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// Input Ports: Size Description
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// =========== ==== ===========
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// clk_s 1 bit Source Domain Input Clock
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// rst_s_n 1 bit Source Domain Active Low Async. Reset
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// init_s_n 1 bit Source Domain Active Low Sync. Reset
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// send_s 1 bit Source Domain Active High Send Request
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// data_s N bits Source Domain Data Input
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// clk_d 1 bit Destination Domain Input Clock
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// rst_d_n 1 bit Destination Domain Active Low Async. Reset
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// init_d_n 1 bit Destination Domain Active Low Sync. Reset
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// test 1 bit Test input
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//
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// Output Ports Size Description
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// ============ ==== ===========
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// event_d 1 bit Dest Domain Active High Event Signal
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//
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// MODIFIED:
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//
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// RJK 3-08-17 Corrected port order to be consistent with synthesis
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//
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// DLL 9-21-11 Added tst_mode=2 checking and comments (not a functional change)
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//
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//----------------------------------------------------------------------------
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////////////////////////////////////////////////////////////////////////////////
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module DW_pulse_sync
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(
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clk_s,
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rst_s_n,
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init_s_n,
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event_s,
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clk_d,
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rst_d_n,
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init_d_n,
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event_d,
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test
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);
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parameter integer reg_event = 0; // 0 => event_d will have combination logic
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// but latency will be 1 cycle sooner
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// 1 => event_d will be retimed so there will
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// be no logic between register & port
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// but event is delayed 1 cycle
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parameter integer f_sync_type = 1; // 0 - 3
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// 0 => single clock design, i.e. clk_d == clk_s
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// 1 => first synchronization in clk_d domain is
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// done on the negative edge and the rest
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// on positive edge. This reduces latency
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// req. of synchronization slightly but
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// quicker metastability resolution for
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// the negative edge sensitive FF. It also
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// requires the technology library to
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// contain an acceptable negative edge
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// sensitive FF.
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// 2 => all synchronization in clk_d domain is
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// done on positive edges - 2 d flops in
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// destination domain
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// 3 => all synchronization in clk_d domain is
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// done on positive edges - 3 d flops in
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// destination domain
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// 4 => all synchronization in clk_d domain is
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// done on positive edges - 4 d flops in
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// destination domain
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parameter integer tst_mode = 0; // 0-2
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// 0 => no latch insertion
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// 1 => hold latch using neg edge flop
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// 2 => reserved unsupported
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parameter integer verif_en = 1; // 0-4
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// 0 => no sampling errors are used
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// 1 => random insertion of 0 or upt to 1 dest clk
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// 2 => random insertion of 0,0.5,1,or 1.5 dest clk
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// 3 => random insertion of 0,1,2,or 3 dest clk
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// 4 => random insertion of 0 or up to 0.5 dest clk
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parameter integer pulse_mode = 0; // 0 => single clock cycle pulse in produces
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// single clock cycle pulse out
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// 1 => rising edge transition in produces
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// 2 => falling edge transition in produces
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// single clock cycle pulse out
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// 3 => toggle transition in produces
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// single clock cycle pulse out
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input clk_s; // clock input for source domain
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input rst_s_n; // active low async. reset in clk_s domain
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input init_s_n; // active low sync. reset in clk_s domain
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input event_s; // event pulse input (active high event)
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input clk_d; // clock input for destination domain
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input rst_d_n; // active low async. reset in clk_d domain
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input init_d_n; // active low sync. reset in clk_d domain
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output event_d; // event pulse output (active high event)
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input test; // test 1 bit Test input
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initial begin
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if ((f_sync_type > 0)&&(f_sync_type < 8))
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$display("Information: *** Instance %m is the DW_pulse_sync Clock Domain Crossing Module ***");
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end
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// synopsys translate_off
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// Param check
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if ( (reg_event < 0) || (reg_event > 1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter reg_event (legal range: 0 to 1)",
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reg_event );
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end
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if ( ((f_sync_type & 7) < 0) || ((f_sync_type & 7) > 4) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter (f_sync_type & 7) (legal range: 0 to 4)",
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(f_sync_type & 7) );
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end
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if ( (tst_mode < 0) || (tst_mode > 2) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter tst_mode (legal range: 0 to 2)",
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tst_mode );
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end
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if ( (verif_en < 0) || (verif_en > 4) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter verif_en (legal range: 0 to 4)",
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verif_en );
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end
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if ( (pulse_mode < 0) || (pulse_mode > 3) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter pulse_mode (legal range: 0 to 3)",
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pulse_mode );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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wire O0I100OO;
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reg O1O10OI0;
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reg OO10OI10;
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reg [1:0] O0OlIO00;
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wire II1lIlI0;
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reg OOO01l10;
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reg O00O000l;
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wire O101lOO0;
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generate
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if (((f_sync_type&7)>1)&&(tst_mode==2)) begin : GEN_LATCH_frwd_hold_latch_PROC
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reg [1-1:0] OO10OI10;
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always @ (clk_s or O1O10OI0) begin : LATCH_frwd_hold_latch_PROC_PROC
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if (clk_s == 1'b0)
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OO10OI10 = O1O10OI0;
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end // LATCH_frwd_hold_latch_PROC_PROC
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assign O0I100OO = (test==1'b1)? OO10OI10 : O1O10OI0;
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end else begin : GEN_DIRECT_frwd_hold_latch_PROC
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assign O0I100OO = O1O10OI0;
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end
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endgenerate
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DW_sync #(1, f_sync_type+8, tst_mode, verif_en) SIM(
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.clk_d(clk_d),
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.rst_d_n(rst_d_n),
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.init_d_n(init_d_n),
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.data_s(O0I100OO),
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.test(test),
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.data_d(II1lIlI0) );
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assign O101lOO0 = pulse_mode === 0 ? event_s ^ O1O10OI0
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:(pulse_mode === 1? (event_s & ! O00O000l) ^ O1O10OI0
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:(pulse_mode === 2? (!event_s & O00O000l) ^ O1O10OI0
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:(pulse_mode === 3? (event_s ^ O00O000l) ^ O1O10OI0: 1'bx)));
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always @ ( posedge clk_s or negedge rst_s_n ) begin : a1000_PROC
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if(rst_s_n === 1'b0 ) begin
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O1O10OI0 <= 1'b0;
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O00O000l <= 1'b0;
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end else if(rst_s_n === 1'b1 ) begin
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if(init_s_n === 1'b0 ) begin
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O1O10OI0 <= 1'b0;
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O00O000l <= 1'b0;
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end else if(init_s_n === 1'b1 ) begin
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if(event_s === 1'b1) begin
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O1O10OI0 <= O101lOO0;
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O00O000l <= event_s;
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end else if(event_s !== 1'b0) begin
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O1O10OI0 <= 1'bx;
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O00O000l <= 1'bx;
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end else begin
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O1O10OI0 <= O101lOO0;
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O00O000l <= event_s;
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end
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end else begin
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O1O10OI0 <= 1'bx;
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O00O000l <= 1'bx;
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end
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end else begin
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O1O10OI0 <= 1'bx;
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O00O000l <= 1'bx;
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end
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end
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always @ ( posedge clk_d or negedge rst_d_n) begin : a1001_PROC
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if(rst_d_n === 1'b0 )
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O0OlIO00 <= 2'b00;
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else if(rst_d_n === 1'b1 )
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if(init_d_n === 1'b0)
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O0OlIO00 <= 2'b00;
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else if(init_d_n === 1'b1)
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O0OlIO00 <= {O0OlIO00[0] ^ II1lIlI0, II1lIlI0};
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else
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O0OlIO00 <= 2'bxx;
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else
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O0OlIO00 <= 2'bxx;
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end
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assign event_d = (reg_event) ? O0OlIO00[1] : O0OlIO00[0] ^ II1lIlI0 ;
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always @ (clk_d) begin : monitor_clk_d
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if ( (clk_d !== 1'b0) && (clk_d !== 1'b1) && ($time > 0) )
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$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk_d input.",
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$time, clk_d );
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end // monitor_clk_d
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always @ (clk_s) begin : monitor_clk_s
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if ( (clk_s !== 1'b0) && (clk_s !== 1'b1) && ($time > 0) )
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$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk_s input.",
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$time, clk_s );
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end // monitor_clk_s
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// synopsys translate_on
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endmodule
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